WO2012011207A1 - Semiconductor device manufacturing method comprising step of removing pad electrode for inspection - Google Patents

Semiconductor device manufacturing method comprising step of removing pad electrode for inspection Download PDF

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Publication number
WO2012011207A1
WO2012011207A1 PCT/JP2011/001515 JP2011001515W WO2012011207A1 WO 2012011207 A1 WO2012011207 A1 WO 2012011207A1 JP 2011001515 W JP2011001515 W JP 2011001515W WO 2012011207 A1 WO2012011207 A1 WO 2012011207A1
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Prior art keywords
chip
insulating film
interlayer insulating
wiring
forming
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PCT/JP2011/001515
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French (fr)
Japanese (ja)
Inventor
藤井政了
安井孝俊
平井健裕
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パナソニック株式会社
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Publication of WO2012011207A1 publication Critical patent/WO2012011207A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0392—Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step
    • H01L2224/03921—Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step by repairing the bonding area damaged by the probing step
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    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that enables probe inspection of an element to be measured during manufacture.
  • a first interlayer insulating film 2 made of a plurality of layers is formed on a semiconductor substrate 1 made of silicon on which a device under test (not shown) such as a transistor is formed.
  • the first metal wiring layer 4, the first contact plug 3, and the second metal wiring layer 5 that are electrically connected to the element to be measured are sequentially formed on each interlayer insulating film so as to be electrically connected to each other. To do.
  • a first metal pad 6 connected to the second metal wiring layer 5 is selectively formed on the first interlayer insulating film 2.
  • the probe 7 is brought into contact with the formed first metal pad 6, and the electrical characteristics of the element to be measured are measured.
  • a second layer composed of a plurality of layers is formed on the first interlayer insulating film 2 including the first metal pad 6.
  • the interlayer insulating film 11 is formed, and the second contact plug 10 and the third metal wiring layer 8 electrically connected to the second metal wiring layer 5 are sequentially electrically connected to each interlayer insulating film.
  • a second metal pad 9 connected to the third metal wiring layer 8 is formed on the second interlayer insulating film 11.
  • the probe 7 is brought into contact with the second metal pad 9 to measure various electrical characteristics of the finished product.
  • the probe 7 is brought into contact with the first metal pad 6 to measure the electrical characteristics of the element to be measured. At this time, a part of the surface of the first metal pad 6 is peeled off by contact with the probe 7, and as a result, particles that are metal powder are generated.
  • the process proceeds to the next process with the first metal pad 6 left, so the first metal pad 6 occupies.
  • the same metal wiring layer cannot be formed in the region. That is, the metal wiring layer that is the same layer as the first metal pad 6 needs to be formed avoiding the first metal pad 6, resulting in an increase in chip area. For this reason, there arises a problem that the number of chips taken per wafer is reduced and the manufacturing cost per chip is increased.
  • the first interlayer insulating film 2 formed at the end of the first metal pad 6 is left.
  • the wiring is formed in the upper layer due to the difference in level, a problem of manufacturing defects due to insufficient processing accuracy in the lithography process also occurs.
  • a step is formed in the vicinity of the first metal pad 6 on the surface of the resist film, and the focus during exposure may not be achieved.
  • the present invention can remove particles generated from a pad without damaging a semiconductor device even if probe inspection of an element to be measured is performed in the middle of manufacturing, and also increases the chip area and the chip. It aims to be able to prevent the decrease in the number of harvests.
  • a method for manufacturing a semiconductor device is configured such that an inspection pad electrode formed on an interlayer insulating film being manufactured is used and then the inspection pad electrode is removed.
  • the first method for manufacturing a semiconductor device includes a step (a) of forming a first interlayer insulating film on a semiconductor substrate on which an element to be measured is formed, and a first interlayer Forming a first via electrically connected to the device to be measured and a first wiring electrically connected to the first via in the insulating film; and a first interlayer A step (c) of forming an inspection pad electrode made of an organic conductive film on the insulating film so as to be connected to the first wiring, and a probe needle in contact with the inspection pad electrode A step (d) of measuring the electrical characteristics of the measuring element and a step (e) of removing the inspection pad electrode after the step (d) are provided.
  • the electrical characteristics of the element to be measured are measured in a state where the probe needle is in contact with the inspection pad electrode made of an organic conductive film, and then the inspection pad electrode is removed. . For this reason, even if probe inspection of the element under measurement is performed during manufacturing, the pad electrode for inspection can be easily and reliably removed without damaging the semiconductor device, and particles generated from the pad can be removed. In addition, since the same layer wiring as the pad can be arranged in the pad formation region, an increase in the chip area can be prevented.
  • the first semiconductor device manufacturing method includes a step (f) of forming a second interlayer insulating film on the first interlayer insulating film so as to cover the first wiring after the step (e). And (g) forming a second via electrically connected to the first wiring and a second wiring electrically connected to the second via in the second interlayer insulating film. And may be further provided.
  • the step (b) includes a step (b1) of forming a via hole exposing the device under test in the first interlayer insulating film, and embedding a conductive material in the formed via hole.
  • a step (b2) of forming a via hole exposing the device under test in the first interlayer insulating film, and embedding a conductive material in the formed via hole.
  • the step (b) is formed by a step (b5) of forming a via hole exposing the element to be measured in the first interlayer insulating film and a wiring groove in a region including the via hole. And a step (b6) of forming a first via and a first wiring by embedding a conductive material in the via hole and the wiring groove.
  • the manufacturing method of the first semiconductor device includes a step (f) of forming a chip connection electrode on the first interlayer insulating film so as to be connected to the first wiring after the step (e).
  • the method may further comprise the step (g) of holding the semiconductor substrate on the holding substrate and electrically connecting the semiconductor substrate and the holding substrate via the chip connection electrode.
  • the holding substrate is a printed board
  • the chip connecting electrode may be connected to the printed board by making the chip connecting electrode of the semiconductor substrate face the main surface of the printed board. Good.
  • the holding substrate has at least a through electrode
  • the chip connecting electrode is made to face the main surface of the holding substrate by causing the chip connecting electrode of the semiconductor substrate to face the holding substrate.
  • the step (h) of electrically connecting the holding substrate to the printed circuit board by causing the surface of the holding substrate opposite to the semiconductor substrate to face the main surface of the printed circuit board.
  • the second semiconductor device manufacturing method includes a step (a) of forming a first interlayer insulating film on a semiconductor substrate on which an element to be measured is formed, and a first interlayer insulating film, A step (b) of forming a first via electrically connected to the device to be measured and a first wiring electrically connected to the first via; and on the first interlayer insulating film (C) forming a chip connection electrode so as to be connected to the first wiring; and an inspection pad electrode made of an organic conductive film is formed on the first wiring on the first interlayer insulating film. More than the step (d), the step (e) of measuring the electrical characteristics of the device under test with the probe needle in contact with the test pad electrode, and the step (e).
  • the first chip that has been subjected to the step (f) of removing the pad electrode for inspection and the steps (a) to (f) The second chip that has been subjected to the steps (a) to (f) is prepared, and the first chip and the second chip are made to face each other, so that the chip connecting electrodes in the first chip and the second chip are connected to each other. And a step (g) of forming a laminated chip structure including the first chip and the second chip.
  • the organic conductive film may include a thiophene-based organic conductive material.
  • poly3,4-ethylenedioxythiophene can be used as the thiophene organic conductive material.
  • the inspection pad electrode can be easily and reliably removed without damaging the semiconductor device.
  • particles generated from the pad can be removed, and wiring in the same layer as the pad can be arranged in the pad formation region, so that an increase in chip area and a reduction in the number of chips can be prevented.
  • FIG. 1 is a cross-sectional view showing a process for forming a device under test, which is a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a plan view showing a device under test, which is a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 3A to FIG. 3F are cross-sectional views in order of steps showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4A to FIG. 4I are cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to a modification of the first embodiment of the present invention.
  • FIG. 5G are cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 6A is a plan view showing a conventional semiconductor device.
  • FIG. 6B is a plan view showing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 7 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to a modification of the second embodiment of the present invention.
  • FIG. 8 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the third embodiment of the present invention.
  • FIG. 9 is a plan view showing one step in the method of manufacturing a semiconductor device according to the third embodiment of the present invention.
  • FIG. 10A to FIG. 10D are cross-sectional views in order of steps showing a method of manufacturing a semiconductor device including probe inspection during manufacturing according to a conventional example.
  • a transistor as a device to be measured is formed on a semiconductor substrate 100 made of silicon.
  • the element isolation film 200 is selectively formed on the semiconductor substrate 100 to form an active region.
  • the gate insulating film 201 and the gate electrode 202 are formed on the active region, and the sidewalls 203 are formed on the side surfaces of the gate insulating film 201 and the gate electrode 202.
  • predetermined impurity ions are implanted into the active region to form source / drain regions 204 and 205, respectively.
  • a first interlayer insulating film 101 made of, for example, silicon oxide (SiO 2 ) or silicon oxycarbide (SiOC) is formed on the semiconductor substrate 100 so as to cover the transistor by chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • contact plugs 206 made of, for example, tungsten (W), which are electrically connected to the source / drain regions 204 and 205, are formed in the first interlayer insulating film 101 by CVD and chemical mechanical polishing (CMP), respectively.
  • CMP chemical mechanical polishing
  • a first metal wiring 102 made of, for example, copper (Cu) connected to the contact plug 206 is selectively formed on the first interlayer insulating film 101 by plating and CMP.
  • Fig. 2 shows the planar configuration of the transistor.
  • the gate electrode 202 is connected to the gate pad 208.
  • Three sets of source / drain regions 204 and 205 are formed in parallel and connected to the drain pad 209 and the source pad 210, respectively.
  • a second interlayer insulating film 101 A is formed on the first interlayer insulating film 101 so as to cover the first metal wiring 102.
  • a via plug 103 made of, for example, tungsten, copper, or aluminum (Al), which is electrically connected to the first metal wiring 102, is formed in the second interlayer insulating film 101A.
  • the transistor and the contact plug 206 are omitted to simplify the drawing.
  • an organic conductive film 104 is formed on the second interlayer insulating film 101A with the via plug 103 exposed on the upper surface.
  • the organic conductive film 104 is formed by, for example, dissolving a thiophene-based organic conductive material made of poly3,4-ethylenedioxythiophene in an organic solvent such as 1-butanol, followed by spin coating, followed by 100 ° C. It is formed by baking to a certain extent.
  • a resist pattern 105 that determines a formation region of a test pad is formed on the organic conductive film 104 by lithography.
  • the film thicknesses of the organic conductive film 104 and the resist pattern 105 are each about 1 ⁇ m.
  • the organic conductive film 104 is inspected by etching the organic conductive film 104 using the resist pattern 105 as a mask, for example, by selective dry etching using oxygen gas.
  • a pad electrode 104A is formed.
  • the size of the inspection pad electrode 104A is set to 30 ⁇ m or more on one side or the diameter so as to ensure a sufficient size for probing.
  • the specific resistance of the thiophene-based organic conductive material is as small as about 1000 ⁇ cm, which is sufficient for measuring the basic characteristics of the formed transistor.
  • the inspection pad electrode 104A is formed by the lithography method and the etching method. Instead, the inspection pad electrode 104A is formed by an offset printing method, an inkjet printing method, or the like. It can also be used. Further, if a photosensitive organic conductive film is used as the organic conductive film 104, the organic conductive film can be directly patterned.
  • thiophene organic conductive material a thiophene organic conductive material other than poly3,4-ethylenedioxythiophene can be used. Furthermore, even if carbon black or carbon fiber, which is a conductive material, is mixed with, for example, an amine-based non-photosensitive polymer and then patterned with a resist, an effect equivalent to that of a thiophene-based organic conductive material can be obtained. Can do.
  • the resist pattern 105 is also reduced by etching and eventually disappears. This is because there is almost no difference in film thickness and etching rate between the resist pattern 105 and the organic conductive material film 104. That is, because the patterning accuracy of the inspection pad electrode 104A is not required to be high, the etching selectivity between the organic conductive film 104 and the resist pattern 105 does not need to be so high. For this reason, it is not necessary to provide a process for removing the resist for patterning.
  • the film thickness of the resist pattern 105 when the film thickness of the resist pattern 105 is excessive, the resist remains on the organic conductive film 104, or conversely, the film thickness of the resist pattern 105 is insufficient and the organic conductive film 104 itself becomes
  • the surface of the organic conductive film 104 may be etched to form a surface oxide layer having a thickness of about 10 nm.
  • the probe needle breaks through the remaining resist pattern or surface oxide layer and comes into contact with the organic conductive film 104 (inspection pad electrode 104A) during the probe inspection in the next process. It does not interfere with probe inspection.
  • the probe needle 107 or the like is brought into contact with the inspection pad electrode 104A, and the probe inspection of the element to be measured is performed during the manufacturing process.
  • the probe inspection only those wafers whose semiconductor devices (chips) exhibiting abnormal electrical characteristics do not exceed a predetermined ratio or quantity are advanced to the next process, and defective wafers exceeding the predetermined ratio or quantity are subjected to this probe inspection.
  • the set value can be arbitrarily set.
  • the wafer treatment after being removed from the manufacturing process is usually discarded, but if it can be reused, the processing corresponding to that can be performed.
  • the transistor shown in FIG. 2 can be evaluated if the probe inspection during the manufacturing process is after the formation of at least one layer of the first metal wiring 102. That is, inspection of transistor characteristics such as threshold voltage and leakage current, parasitic resistance characteristics, contact characteristics, and junction characteristics can be performed. If the obtained characteristics are different from the desired characteristics as a result of the inspection, the corresponding chip is excluded from the inspection target chip at the time of the final probe inspection performed after the manufacturing process as a wafer, or the probe inspection is completed during the manufacturing process. Thus, the corresponding wafer is determined to be an abnormal wafer, and measures such as not proceeding to the next process are performed. In this way, it is possible to reduce the manufacturing material cost of the semiconductor device and the like, reduce the inspection cost, and improve the average yield per wafer after the completion of the semiconductor device. Furthermore, the production efficiency of the entire line can be improved, and the production quantity can be increased.
  • transistor characteristics such as threshold voltage and leakage current, parasitic resistance characteristics, contact characteristics, and junction characteristics can be performed. If the obtained characteristics are different from the
  • the basic circuit characteristics such as the SRAM circuit, the inverter circuit, and the analog circuit can be inspected. Subsequent processing of defective chips or processing of defective wafers is as described above.
  • determining the layout of the upper metal wiring based on this probe inspection. For example, when the signal processing (propagation) speed of a certain circuit is faster than other circuits as a result of probe inspection, a wiring delay circuit is added in the upper layer in the middle of the signal transmission element to other circuits. By omitting the delay circuit in the upper layer, the electrical characteristics of the entire chip can be corrected, and as a result, defects due to clock skew can be relieved and the yield can be maximized. it can.
  • the inspection pad electrode 104A made of an organic conductive material used in the probe inspection is removed by, for example, ashing using oxygen gas or etching using an organic solvent such as 1-butanol.
  • a second metal wiring 108 is formed on the second interlayer insulating film 101A to obtain a final product in a wafer state.
  • the second metal wiring 108 may be formed in a third interlayer insulating film formed on the second interlayer insulating film 101A.
  • the probe inspection is performed when the upper second metal wiring is formed in order to remove the inspection pad electrode after performing the probe inspection.
  • the area occupied by the inspection pad electrode can be effectively utilized. That is, since the increase in the chip area can be suppressed by removing the inspection pad electrode, the number of chips collected per wafer can be increased, and as a result, the semiconductor device can be manufactured at a lower cost.
  • the pad electrode for inspection can be selectively selected without damaging the underlying device or wiring layer that is the element to be measured. Can be removed.
  • the element to be measured is a transistor here, the transistor is only an example, and may be an active element and a passive element that generally constitute a semiconductor device.
  • This modification is different from the first embodiment in the formation method of the metal wiring. That is, in the first embodiment, the metal wiring is formed by using a so-called single damascene method in which the via plug and the metal wiring are separately formed. However, in this modification, the via plug and the metal wiring are formed at the same time. The metal wiring is formed using a so-called dual damascene method.
  • the same reference numerals are given to the same constituent materials as those shown in the first embodiment, and the description thereof is omitted.
  • the first metal wiring 102 is covered on the first interlayer insulating film 101 in the semiconductor substrate 100 on which the transistor shown in FIGS. 1 and 2 is formed.
  • a second interlayer insulating film 101A is formed.
  • the second metal wiring 110 is formed in the second interlayer insulating film 101A by burying, for example, tungsten, copper, or aluminum in the lower via portion connected to the first metal wiring 102 and the upper groove portion. To do.
  • a dielectric film 111 made of, for example, silicon oxide is formed so as to cover the second interlayer insulating film 101A including the second metal wiring 110.
  • an opening for exposing a part of the second metal wiring 110 is formed in the dielectric film 111 by lithography and dry etching, and the dielectric film 111 is formed. Then, a mask film 111a is formed.
  • the organic conductive film 104 is formed on the mask film 111a including the opening.
  • the organic conductive film 104 is spin-coated by dissolving a thiophene-based organic conductive material made of poly3,4-ethylenedioxythiophene in an organic solvent such as 1-butanol, as in the first embodiment. After that, it is formed by baking at about 100 ° C.
  • a resist pattern 105 is formed on the organic conductive film 104 to determine the formation area of the inspection pad by lithography.
  • the organic conductive film 104 is etched from the organic conductive film 104 by etching using the resist pattern 105 as a mask by selective dry etching using oxygen gas.
  • a pad electrode 104A is formed.
  • the probe needle 107 or the like is brought into contact with the inspection pad electrode 104A, and the probe inspection of the element to be measured is performed during the manufacturing process.
  • the inspection pad electrode 104A which is the organic conductive film 104 used in the probe inspection, is removed by, for example, ashing using oxygen gas or etching using an organic solvent such as 1-butanol.
  • a third interlayer insulating film 112 is formed on the mask film 111a including the second metal wiring 110, and then the second damascene method is used.
  • a third metal wiring 113 is formed in the third interlayer insulating film 112. Further, although not shown in the drawing, the third and subsequent metal wirings are formed by a dual damascene method to obtain a desired semiconductor device.
  • the probe pad electrode is removed after the probe inspection, and thereafter When the wiring layer is formed, particles generated during probe inspection can be removed. Further, since the inspection pad electrode is removed, the region occupied by the inspection pad electrode can be used effectively, and an increase in the chip area can be suppressed. Further, by using an organic conductive material for the inspection pad electrode, the inspection pad electrode can be selectively removed after the probe inspection without damaging the underlying device or wiring layer.
  • the case where probe inspection is performed on an element to be measured for example, a transistor, in the process of manufacturing one chip has been described.
  • the second embodiment when a chip is mounted on a printed board.
  • probe inspection of the element to be measured is performed during the manufacturing process. Specifically, in the second embodiment, after the uppermost metal wiring is formed, the probe inspection of the element to be measured is performed.
  • the via plug 103 and the second metal wiring 108 are selectively formed in the second interlayer insulating film 101A.
  • a third interlayer insulating film 101B is formed on the second interlayer insulating film 101A including the second metal wiring 108.
  • the via plug 103 and the third metal wiring 120 are sequentially formed in the third interlayer insulating film 101B.
  • a protective film 121 made of, for example, polybenzoxazole (PBO) for preventing moisture absorption from the chip surface is formed on the third interlayer insulating film 101B including the third metal wiring 120 which is the uppermost wiring.
  • a connection hole 121a that exposes the third metal wiring 120 is formed in the protective film 121 by lithography and dry etching.
  • a thiophene-based organic conductive material made of poly3,4-ethylenedioxythiophene is 1-butanol or the like.
  • the organic conductive film 104 is formed by dissolving in an organic solvent and spin coating, followed by baking at about 100 ° C.
  • a resist pattern 105 is formed by lithography on the region including the connection hole 121a in the organic conductive film 104 so as to cover the formation region of the inspection pad electrode.
  • the film thicknesses of the organic conductive film 104 and the resist pattern 105 are each about 1 ⁇ m.
  • the step of forming the organic conductive film 104 is not limited to the above-described procedure.
  • the wafer is diced and separated into chips, and a chip connection electrode described later is deposited, that is, the chip connection. It may be formed on the electrode. Further, it may be before the protective film 121 is formed.
  • the organic conductive film 104 is etched from the organic conductive film 104 by using, for example, selective dry etching using oxygen to mask the resist pattern 105 as a mask.
  • the electrode 104A is formed.
  • the resist pattern 105 is also reduced and eventually disappears.
  • the probe needle 107 or the like is brought into contact with the inspection pad electrode 104A, and the probe inspection of the element to be measured is performed during the manufacturing process.
  • the process proceeds to the next step. If the electrical characteristics of the device under test indicate abnormal characteristics, either exclude the chip from the target chip for probe inspection after the end of the manufacturing process, or determine that the wafer is an abnormal wafer and proceed to the next process. Take measures such as not moving. If it does in this way, while being able to reduce the manufacturing material cost including the assembly process which is a post process, or to improve the average yield after the assembly, it becomes possible to increase the production efficiency and the production quantity of the entire production line. .
  • test pad electrode 104A which is an organic conductive film used in the probe test, by, for example, ashing using oxygen gas or etching using an organic solvent such as 1-butanol.
  • a chip connection electrode 122 as a base metal layer is formed on the third metal wiring 120 by a vacuum deposition method. Thereafter, solder balls 123 are provided on the chip connection electrodes 122.
  • a solder ball is placed between the chip in the state shown in FIG. 5F between the chip connection electrode 122 and the electrode formed on the upper surface of the printed circuit board 130 as the holding substrate.
  • Mounting is performed by a so-called flip-chip method in which 123 is held in an intervening state.
  • a through electrode 131 made of silicon is formed inside the printed circuit board 130 so as to penetrate in the front and back direction of the printed circuit board 130, and solder balls 123 are also provided on the electrode exposed from the back surface. .
  • FIG. 6A is a conventional semiconductor device for comparison, and shows a planar configuration when the probe inspection is performed in a completed state of the chip 140.
  • the completed chip 140 has a normal pad forming area to which solder balls 123 each having a diameter of about 20 ⁇ m to 400 ⁇ m can be connected to ensure electrical continuity between the chips when connecting to other chips and the like. Is required.
  • the test pad electrode 104A made of an organic conductive material is formed on the third metal wiring 120 itself, and FIG. Probe inspection is performed in the step shown in FIG. 5B, and in the step shown in FIG. 5E, the inspection pad electrode 104A used as the pad electrode in the probe inspection is removed. Therefore, as shown in the plan configuration of FIG. 6B, in the second embodiment, it is not necessary to provide the pad electrode for inspection 141 for performing the probe inspection as in the prior art on the peripheral portion of the chip 140. Therefore, a region for routing the metal wiring 142 that electrically connects the normal pad electrode and the inspection pad electrode 141 is also unnecessary. For this reason, since the area of the chip 140 itself can be greatly reduced, a reduction in the number of chips can be prevented, and as a result, a semiconductor device can be manufactured at a lower cost.
  • This modified example is different from the second embodiment in the chip mounting form after the probe inspection is completed. That is, in the second embodiment, the chip is directly mounted on the printed circuit board 130. However, in this modified example, after the chip is mounted on the wiring board (interposer) 132 that is the holding board, the wiring board is further mounted. 132 is mounted on the printed circuit board 130.
  • the chip in the state shown in FIG. 5F is flip-chip mounted on the wiring substrate 132 on which the through electrode 133 made of, for example, silicon is formed with the solder balls 123 interposed.
  • the through electrode 133 made of, for example, silicon
  • a memory circuit, a logic circuit, or the like may be formed on the wiring board 132 in addition to the through electrode 133.
  • the wiring substrate 132 holding the chip is flip-chip mounted on the printed circuit board 130 with the solder balls 123 interposed therebetween, thereby completing a mounted product.
  • the inspection pad electrode for performing the conventional probe inspection is removed in order to remove the inspection pad electrode used as the pad electrode during the probe inspection. Need not be provided at the peripheral edge of the chip. Therefore, a region for routing the metal wiring that electrically connects the normal pad electrode and the inspection pad electrode becomes unnecessary. As a result, the area of the chip itself can be greatly reduced, so that a reduction in the number of chips can be prevented, and a semiconductor device can be manufactured at a lower cost.
  • the third embodiment is a method of manufacturing a semiconductor device formed by stacking a first chip 100a and a second chip 100b, which are semiconductor device chips, respectively.
  • the semiconductor device according to the third embodiment is configured, for example, by bonding a first chip 100a and a second chip 100b to each other via solder balls 123 and the like.
  • a plurality of metal wirings 120b formed on the surface of the metal wiring layer 114b as chip connection electrodes via solder balls 123, electrical signals between the two chips 100a and 100b can be exchanged.
  • the back surface of the second chip 100b is bonded to a lead frame 213 made of metal.
  • a bonding wire 212 made of gold or the like is wire-bonded to the bonding pad 211 provided on the surface of the second chip 100b.
  • the bonding pad 211 for wire bonding has a square shape with a side length of at least 50 ⁇ m, and the metal wirings 120a and 120b for exchanging electrical signals between the chips 100a and 100b are , Both are circular or square with a side length of about 10 ⁇ m.
  • the first chip 100a and the second chip 100b are formed by forming test pads made of an organic conductive material on the chips 100a and 100b before bonding to each other.
  • the inspection pad is removed after the inspection using the probe pad and the probe needle is carried out to determine the quality of each chip 100a, 100b.
  • solder balls 123 are respectively formed on the metal wirings 120b of the second chip 100b, and the metal wirings 120a of the first chip 100a and the metal wirings 120b of the second chip 100b are aligned and crimped together. To do.
  • the defective chips are excluded in advance.
  • FIG. 9 schematically shows, for example, a state when the first chip 100a is inspected.
  • the test pad 104a made of an organic material having conductivity according to the present invention includes, for example, a scribe region 301a, a region where no chip-to-chip metal wiring 120a is provided on the chip surface, or a chip surface. Is protected by an insulating film, it is formed over a region on the metal wiring 120a for chip-to-chip connection that is not used for inspection.
  • the size of the inspection pad is about 50 ⁇ m, and the minimum pitch of the pads is 60 ⁇ m.
  • the inspection method is the same as that described in the first embodiment, and repeated description thereof is omitted here.
  • each metal wiring 120a, 120b has a size of 10 ⁇ m or less, it is made of an organic material having conductivity around it.
  • the test pad 104a it is possible to determine the quality of each chip 100a, 100b. That is, as a result of individually inspecting each of the chips 100a and 100b, chips determined as non-defective products can be bonded together.
  • the surface of each metal wiring 120a, 120b is not in direct contact with the probe needle, damage to the wiring surface and particles are not generated, and a stable connection between chips can be achieved with a solder ball 123 or the like. realizable. As a result, the probability that the semiconductor device after bonding is defective can be extremely reduced, and the manufacturing cost can be greatly reduced.
  • the method for manufacturing a semiconductor device according to the present invention can remove particles generated from a pad without damaging the semiconductor device even if probe inspection of the element to be measured is performed in the middle of manufacturing, and also increases the chip area, and thus It is possible to prevent a reduction in the number of chips collected, and is particularly useful for a method for manufacturing a semiconductor device including in-line probe inspection of a semiconductor device.

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Abstract

First of all, a first interlayer insulating film (101) is formed on a semiconductor substrate (100) on which an element to be measured is formed. After that, a contact plug (206) that is electrically connected to the element to be measured and a first wiring line (102) that is electrically connected to the contact plug (206) are formed in the first interlayer insulating film (101). Next, a pad electrode for inspection (104A) that is composed of an organic conductive film is formed on the first interlayer insulating film (101) so as to be connected to the first wiring line (102). Following that, the electrical characteristics of the element to be measured are measured, while keeping a probe needle (107) in contact with the pad electrode for inspection (104A). After that, the pad electrode for inspection (104A) is removed.

Description

[規則37.2に基づきISAが決定した発明の名称]　検査用パッド電極を除去する工程を備える半導体装置の製造方法 [Title of Invention Determined by ISA Based on Rule 37.2] Method for Manufacturing Semiconductor Device Comprising Step of Removing Inspection Pad Electrode
　本発明は、半導体装置の製造方法に関し、特に、製造途中における被測定素子のプローブ検査を可能とする半導体装置の製造方法に関する。 The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that enables probe inspection of an element to be measured during manufacture.
　近年、半導体集積回路装置の高集積化、高機能化及び高速化を実現するために、金属配線パターンの微細化及び高層化が進んでいる。しかしながら、製品の製造ターンアラウンドタイム（Turn Around Time：ＴＡＴ）が数ヶ月と長いため、製造の比較的初期の工程で発生した異常を、ウエハの完成後に実施されるプローブ検査で発見するまでに長い時間を要する。その結果、不良の発生から最終検査で発見されるまでの間に不良品が作り続けられることになる。 In recent years, in order to realize high integration, high functionality, and high speed of semiconductor integrated circuit devices, miniaturization and higher layers of metal wiring patterns have been advanced. However, since the product manufacturing turnaround time (Turn Around Time: TAT) is as long as several months, it takes a long time to detect anomalies that occur in a relatively early manufacturing process in probe inspections after the wafer is completed. It takes time. As a result, defective products continue to be made between the occurrence of a defect and the discovery of the final inspection.
　これに対応するため、従来、金属配線の形成工程後の段階で電気特性試験を実施したり、製造工程の途中でパターン欠陥検査を実施したりして、電気的特性の異常又はパターン異常が発見された場合にはその時点で不良ウエハを廃棄する等の工夫がなされている。特に、金属配線の形成段階における電気特性試験については、下記の特許文献１に記載されている。 In order to cope with this, an electrical characteristic test or a pattern abnormality was discovered by conducting an electrical characteristic test at a stage after the metal wiring formation process or by performing a pattern defect inspection in the middle of the manufacturing process. In such a case, a measure is taken such as discarding the defective wafer at that time. In particular, the electrical characteristic test in the formation stage of the metal wiring is described in Patent Document 1 below.
　以下、従来例に係る、製造途中に被測定素子のプローブ検査を行う半導体装置の製造方法について図１０を参照しながら説明する。 Hereinafter, a method of manufacturing a semiconductor device according to a conventional example, in which a probe inspection of an element to be measured is performed during manufacturing, will be described with reference to FIG.
　まず、図１０（ａ）に示すように、トランジスタ等の被測定素子（図示せず）が形成されたシリコンからなる半導体基板１の上に、複数層からなる第１の層間絶縁膜２を形成すると共に、各層間絶縁膜に順次、被測定素子と電気的に接続される第１金属配線層４、第１コンタクトプラグ３及び第２金属配線層５を互いに電気的に接続されるように形成する。 First, as shown in FIG. 10A, a first interlayer insulating film 2 made of a plurality of layers is formed on a semiconductor substrate 1 made of silicon on which a device under test (not shown) such as a transistor is formed. In addition, the first metal wiring layer 4, the first contact plug 3, and the second metal wiring layer 5 that are electrically connected to the element to be measured are sequentially formed on each interlayer insulating film so as to be electrically connected to each other. To do.
　次に、図１０（ｂ）に示すように、第１の層間絶縁膜２の上に、第２金属配線層５と接続される第１の金属パッド６を選択的に形成する。 Next, as shown in FIG. 10B, a first metal pad 6 connected to the second metal wiring layer 5 is selectively formed on the first interlayer insulating film 2.
　次に、図１０（ｃ）に示すように、形成された第１の金属パッド６にプローブ７を接触させて、被測定素子の電気的特性を測定する。 Next, as shown in FIG. 10 (c), the probe 7 is brought into contact with the formed first metal pad 6, and the electrical characteristics of the element to be measured are measured.
　次に、図１０（ｄ）に示すように、被測定素子の電気的特性を測定した後、第１の金属パッド６を含む第１の層間絶縁膜２の上に、複数層からなる第２の層間絶縁膜１１を形成すると共に、各層間絶縁膜に順次、第２金属配線層５と電気的に接続される第２コンタクトプラグ１０及び第３金属配線層８を互いに電気的に接続されるように形成する。その後、第２層間絶縁膜１１の上に、第３金属配線層８と接続される第２の金属パッド９を形成する。 Next, as shown in FIG. 10 (d), after measuring the electrical characteristics of the element under measurement, a second layer composed of a plurality of layers is formed on the first interlayer insulating film 2 including the first metal pad 6. The interlayer insulating film 11 is formed, and the second contact plug 10 and the third metal wiring layer 8 electrically connected to the second metal wiring layer 5 are sequentially electrically connected to each interlayer insulating film. To form. Thereafter, a second metal pad 9 connected to the third metal wiring layer 8 is formed on the second interlayer insulating film 11.
　その後は、図示しないが、第２の金属パッド９にプローブ７を接触させて、完成した製品としての種々の電気的特性を測定する。 Thereafter, although not shown, the probe 7 is brought into contact with the second metal pad 9 to measure various electrical characteristics of the finished product.
特開平２００５－３３３１５８号公報Japanese Patent Laid-Open No. 2005-333158
　前記従来の半導体装置の製造方法は、図１０（ｃ）において、第１の金属パッド６にプローブ７を接触させて被測定素子の電気的特性の測定を行っている。このとき、プローブ７との接触によって第１の金属パッド６の表面の一部が剥がれ落ち、その結果、金属粉であるパーティクルが発生する。 In the conventional method of manufacturing a semiconductor device, in FIG. 10C, the probe 7 is brought into contact with the first metal pad 6 to measure the electrical characteristics of the element to be measured. At this time, a part of the surface of the first metal pad 6 is peeled off by contact with the probe 7, and as a result, particles that are metal powder are generated.
　また、図１０（ｃ）においてプローブ検査を行った後に、図１０（ｄ）に示すように、第１の金属パッド６を残した状態で次工程に進むため、第１の金属パッド６が占める領域に同層の金属配線層を形成することができない。すなわち、第１の金属パッド６と同層の金属配線層は第１の金属パッド６を回避して形成する必要があるため、結果的にチップ面積の増大につながる。このため、１ウエハ当たりのチップの採れ数が減少して、１チップ当たりの製造コストが増大するという問題が生じる。 Further, after performing the probe inspection in FIG. 10C, as shown in FIG. 10D, the process proceeds to the next process with the first metal pad 6 left, so the first metal pad 6 occupies. The same metal wiring layer cannot be formed in the region. That is, the metal wiring layer that is the same layer as the first metal pad 6 needs to be formed avoiding the first metal pad 6, resulting in an increase in chip area. For this reason, there arises a problem that the number of chips taken per wafer is reduced and the manufacturing cost per chip is increased.
　また、製造工程の途中に、厚さが１００ｎｍ程度の第１の金属パッド６を形成し、且つそれを残すため、第１の金属パッド６の端部で形成される第１の層間絶縁膜２との段差の影響により、上層に配線を形成する際に、リソグラフィ工程における加工精度の不足によって製造不良が発生するという問題も生じる。特に、短波長光源を用いる微細パターンの形成時に、レジスト膜の表面における第１の金属パッド６の近傍に段差が生じ、露光時の焦点が合わなくなるというおそれがある。 In addition, in order to form the first metal pad 6 having a thickness of about 100 nm and leave it in the middle of the manufacturing process, the first interlayer insulating film 2 formed at the end of the first metal pad 6 is left. When the wiring is formed in the upper layer due to the difference in level, a problem of manufacturing defects due to insufficient processing accuracy in the lithography process also occurs. In particular, when forming a fine pattern using a short wavelength light source, there is a possibility that a step is formed in the vicinity of the first metal pad 6 on the surface of the resist film, and the focus during exposure may not be achieved.
　本発明は、前記の問題に鑑み、製造の途中で被測定素子のプローブ検査を行っても、半導体装置にダメージを与えることなく、パッドから発生するパーティクルを除去できると共に、チップ面積の増大及びチップの採れ数の減少を防止できるようにすることを目的とする。 In view of the above problems, the present invention can remove particles generated from a pad without damaging a semiconductor device even if probe inspection of an element to be measured is performed in the middle of manufacturing, and also increases the chip area and the chip. It aims to be able to prevent the decrease in the number of harvests.
　前記の目的を達成するため、本発明は、半導体装置の製造方法を、製造途中の層間絶縁膜上に形成する検査用パッド電極を使用した後に、該検査用パッド電極を除去する構成とする。 To achieve the above object, according to the present invention, a method for manufacturing a semiconductor device is configured such that an inspection pad electrode formed on an interlayer insulating film being manufactured is used and then the inspection pad electrode is removed.
　具体的に、本発明に係る第１の半導体装置の製造方法は、被測定素子が形成された半導体基板の上に、第１の層間絶縁膜を形成する工程（ａ）と、第１の層間絶縁膜に、被測定素子と電気的に接続される第１のビアと、該第１のビアと電気的に接続される第１の配線とを形成する工程（ｂ）と、第１の層間絶縁膜の上に、有機導電性膜からなる検査用パッド電極を第１の配線と接続されるように形成する工程（ｃ）と、検査用パッド電極にプローブ針を接触させた状態で、被測定素子の電気的特性を測定する工程（ｄ）と、工程（ｄ）よりも後に、検査用パッド電極を除去する工程（ｅ）とを備えている。 Specifically, the first method for manufacturing a semiconductor device according to the present invention includes a step (a) of forming a first interlayer insulating film on a semiconductor substrate on which an element to be measured is formed, and a first interlayer Forming a first via electrically connected to the device to be measured and a first wiring electrically connected to the first via in the insulating film; and a first interlayer A step (c) of forming an inspection pad electrode made of an organic conductive film on the insulating film so as to be connected to the first wiring, and a probe needle in contact with the inspection pad electrode A step (d) of measuring the electrical characteristics of the measuring element and a step (e) of removing the inspection pad electrode after the step (d) are provided.
　第１の半導体装置の製造方法によると、有機導電性膜からなる検査用パッド電極にプローブ針を接触させた状態で被測定素子の電気的特性を測定し、その後、検査用パッド電極を除去する。このため、製造途中で被測定素子のプローブ検査を行っても、半導体装置にダメージを与えることなく、検査用パッド電極を容易に且つ確実に除去することができ、且つパッドから発生するパーティクルを除去できる共に、パッド形成領域にもパッドと同層の配線を配置できるので、チップ面積の増大を防止することができる。 According to the first method for manufacturing a semiconductor device, the electrical characteristics of the element to be measured are measured in a state where the probe needle is in contact with the inspection pad electrode made of an organic conductive film, and then the inspection pad electrode is removed. . For this reason, even if probe inspection of the element under measurement is performed during manufacturing, the pad electrode for inspection can be easily and reliably removed without damaging the semiconductor device, and particles generated from the pad can be removed. In addition, since the same layer wiring as the pad can be arranged in the pad formation region, an increase in the chip area can be prevented.
　第１の半導体装置の製造方法は、工程（ｅ）よりも後に、第１の層間絶縁膜の上に、第１の配線を覆うように第２の層間絶縁膜を形成する工程（ｆ）と、第２の層間絶縁膜に、第１の配線と電気的に接続される第２のビアと、該第２のビアと電気的に接続される第２の配線とを形成する工程（ｇ）とをさらに備えていてもよい。 The first semiconductor device manufacturing method includes a step (f) of forming a second interlayer insulating film on the first interlayer insulating film so as to cover the first wiring after the step (e). And (g) forming a second via electrically connected to the first wiring and a second wiring electrically connected to the second via in the second interlayer insulating film. And may be further provided.
　第１の半導体装置の製造方法において、工程（ｂ）は、第１の層間絶縁膜に被測定素子を露出するビアホールを形成する工程（ｂ１）と、形成されたビアホールに導電性材料を埋め込むことにより第１のビアを形成する工程（ｂ２）と、第１の層間絶縁膜における第１のビアを含む領域に配線溝を形成する工程（ｂ３）と、形成された配線溝に導電性材料を埋め込むことにより第１の配線を形成する工程（ｂ４）とを含んでいてもよい。 In the first method of manufacturing a semiconductor device, the step (b) includes a step (b1) of forming a via hole exposing the device under test in the first interlayer insulating film, and embedding a conductive material in the formed via hole. Forming a first via (b2), forming a wiring trench in a region including the first via in the first interlayer insulating film (b3), and forming a conductive material in the formed wiring trench And a step (b4) of forming a first wiring by embedding.
　第１の半導体装置の製造方法において、工程（ｂ）は、第１の層間絶縁膜に被測定素子を露出するビアホール及び該ビアホールを含む領域に配線溝を形成する工程（ｂ５）と、形成されたビアホール及び配線溝に導電性材料を埋め込むことにより第１のビア及び第１の配線を形成する工程（ｂ６）とを含んでいてもよい。 In the first method of manufacturing a semiconductor device, the step (b) is formed by a step (b5) of forming a via hole exposing the element to be measured in the first interlayer insulating film and a wiring groove in a region including the via hole. And a step (b6) of forming a first via and a first wiring by embedding a conductive material in the via hole and the wiring groove.
　第１の半導体装置の製造方法は、工程（ｅ）よりも後に、第１の層間絶縁膜の上に、第１の配線と接続されるようにチップ接続用電極を形成する工程（ｆ）と、保持基板の上に半導体基板を保持すると共に、チップ接続用電極を介して半導体基板と保持基板とを電気的に接続する工程（ｇ）とをさらに備えていてもよい。 The manufacturing method of the first semiconductor device includes a step (f) of forming a chip connection electrode on the first interlayer insulating film so as to be connected to the first wiring after the step (e). The method may further comprise the step (g) of holding the semiconductor substrate on the holding substrate and electrically connecting the semiconductor substrate and the holding substrate via the chip connection electrode.
　この場合に、保持基板は、プリント基板であり、工程（ｇ）において、半導体基板のチップ接続用電極をプリント基板の主面と対向させることにより、チップ接続用電極をプリント基板と接続してもよい。 In this case, the holding substrate is a printed board, and in the step (g), the chip connecting electrode may be connected to the printed board by making the chip connecting electrode of the semiconductor substrate face the main surface of the printed board. Good.
　また、この場合に、保持基板は、少なくとも貫通電極を有し、工程（ｇ）において、半導体基板のチップ接続用電極を保持基板の主面と対向させることにより、チップ接続用電極を前記保持基板と接続し、工程（ｇ）よりも後に、保持基板における半導体基板と反対側の面をプリント基板の主面と対向させることにより、保持基板をプリント基板と電気的に接続する工程（ｈ）をさらに備えていてもよい。 Further, in this case, the holding substrate has at least a through electrode, and in step (g), the chip connecting electrode is made to face the main surface of the holding substrate by causing the chip connecting electrode of the semiconductor substrate to face the holding substrate. And after the step (g), the step (h) of electrically connecting the holding substrate to the printed circuit board by causing the surface of the holding substrate opposite to the semiconductor substrate to face the main surface of the printed circuit board. Furthermore, you may provide.
　本発明に係る第２の半導体装置の製造方法は、被測定素子が形成された半導体基板の上に、第１の層間絶縁膜を形成する工程（ａ）と、第１の層間絶縁膜に、被測定素子と電気的に接続される第１のビアと、該第１のビアと電気的に接続される第１の配線とを形成する工程（ｂ）と、第１の層間絶縁膜の上に、第１の配線と接続されるようにチップ接続用電極を形成する工程（ｃ）と、第１の層間絶縁膜の上に、有機導電性膜からなる検査用パッド電極を第１の配線と接続されるように形成する工程（ｄ）と、検査用パッド電極にプローブ針を接触させた状態で、被測定素子の電気的特性を測定する工程（ｅ）と、工程（ｅ）よりも後に、検査用パッド電極を除去する工程（ｆ）と、工程（ａ）から工程（ｆ）までを実施された第１チップと、工程（ａ）から工程（ｆ）までを実施された第２チップとを準備し、第１チップ及び第２チップを互いに対向させることにより、第１チップ及び第２チップにおけるチップ接続用電極同士を接続し、第１のチップ及び第２チップからなる積層チップ構造を形成する工程（ｇ）とを備えている。 The second semiconductor device manufacturing method according to the present invention includes a step (a) of forming a first interlayer insulating film on a semiconductor substrate on which an element to be measured is formed, and a first interlayer insulating film, A step (b) of forming a first via electrically connected to the device to be measured and a first wiring electrically connected to the first via; and on the first interlayer insulating film (C) forming a chip connection electrode so as to be connected to the first wiring; and an inspection pad electrode made of an organic conductive film is formed on the first wiring on the first interlayer insulating film. More than the step (d), the step (e) of measuring the electrical characteristics of the device under test with the probe needle in contact with the test pad electrode, and the step (e). Later, the first chip that has been subjected to the step (f) of removing the pad electrode for inspection and the steps (a) to (f) The second chip that has been subjected to the steps (a) to (f) is prepared, and the first chip and the second chip are made to face each other, so that the chip connecting electrodes in the first chip and the second chip are connected to each other. And a step (g) of forming a laminated chip structure including the first chip and the second chip.
　第１又は第２の半導体装置の製造方法において、有機導電性膜は、チオフェン系有機導電性材料を含んでいてもよい。 In the first or second method for manufacturing a semiconductor device, the organic conductive film may include a thiophene-based organic conductive material.
　この場合に、チオフェン系有機導電性材料には、ポリ３，４－エチレンジオキシチオフェンを用いることができる。 In this case, poly3,4-ethylenedioxythiophene can be used as the thiophene organic conductive material.
　本発明の半導体装置の製造方法によると、製造途中で被測定素子のプローブ検査を行っても、半導体装置にダメージを与えることなく、検査用パッド電極を容易に且つ確実に除去することができ、且つパッドから発生するパーティクルを除去できる共に、パッド形成領域にもパッドと同層の配線を配置できるので、チップ面積の増大、ひいてはチップ採れ数の減少を防止することができる。 According to the method for manufacturing a semiconductor device of the present invention, even if a probe inspection of the element to be measured is performed during the manufacturing, the inspection pad electrode can be easily and reliably removed without damaging the semiconductor device. In addition, particles generated from the pad can be removed, and wiring in the same layer as the pad can be arranged in the pad formation region, so that an increase in chip area and a reduction in the number of chips can be prevented.
図１は本発明の第１の実施形態に係る半導体装置の製造方法であって、被測定素子を形成する一工程を示す断面図である。FIG. 1 is a cross-sectional view showing a process for forming a device under test, which is a method for manufacturing a semiconductor device according to a first embodiment of the present invention. 図２は本発明の第１の実施形態に係る半導体装置の製造方法であって、被測定素子を示す平面図である。FIG. 2 is a plan view showing a device under test, which is a method for manufacturing a semiconductor device according to the first embodiment of the present invention. 図３（ａ）～図３（ｆ）は本発明の第１の実施形態に係る半導体装置の製造方法を示す工程順の断面図である。FIG. 3A to FIG. 3F are cross-sectional views in order of steps showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 図４（ａ）～図４（ｉ）は本発明の第１の実施形態の一変形例に係る半導体装置の製造方法を示す工程順の断面図である。FIG. 4A to FIG. 4I are cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to a modification of the first embodiment of the present invention. 図５（ａ）～図５（ｇ）は本発明の第２の実施形態に係る半導体装置の製造方法を示す工程順の断面図である。FIG. 5A to FIG. 5G are cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention. 図６（ａ）は従来の半導体装置を示す平面図である。図６（ｂ）は本発明の第２の実施形態に係る半導体装置を示す平面図である。FIG. 6A is a plan view showing a conventional semiconductor device. FIG. 6B is a plan view showing a semiconductor device according to the second embodiment of the present invention. 図７は本発明の第２の実施形態の一変形例に係る半導体装置の製造方法の一工程を示す断面図である。FIG. 7 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to a modification of the second embodiment of the present invention. 図８は本発明の第３の実施形態に係る半導体装置の製造方法の一工程を示す断面図である。FIG. 8 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the third embodiment of the present invention. 図９は本発明の第３の実施形態に係る半導体装置の製造方法の一工程を示す平面図である。FIG. 9 is a plan view showing one step in the method of manufacturing a semiconductor device according to the third embodiment of the present invention. 図１０（ａ）～図１０（ｄ）は従来例に係る、製造途中にプローブ検査を含む半導体装置の製造方法を示す工程順の断面図である。FIG. 10A to FIG. 10D are cross-sectional views in order of steps showing a method of manufacturing a semiconductor device including probe inspection during manufacturing according to a conventional example.
　（第１の実施形態）
　本発明の第１の実施形態に係る半導体装置の製造方法について図１～図３を参照しながら説明する。 (First embodiment)
A method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.
　まず、図１に示すように、シリコンからなる半導体基板１００に、被測定素子であるトランジスタを形成する。具体的には、半導体基板１００の上部に素子分離膜２００を選択的に形成して活性領域を形成する。続いて、活性領域の上に、ゲート絶縁膜２０１及びゲート電極２０２を形成し、さらに、ゲート絶縁膜２０１及びゲート電極２０２の側面上にサイドウォール２０３を形成する。その後、ゲート電極２０２及びサイドウォール２０３をマスクとして、活性領域に所定の不純物イオンを注入して、ソースドレイン領域２０４、２０５をそれぞれ形成する。 First, as shown in FIG. 1, a transistor as a device to be measured is formed on a semiconductor substrate 100 made of silicon. Specifically, the element isolation film 200 is selectively formed on the semiconductor substrate 100 to form an active region. Subsequently, the gate insulating film 201 and the gate electrode 202 are formed on the active region, and the sidewalls 203 are formed on the side surfaces of the gate insulating film 201 and the gate electrode 202. Thereafter, by using the gate electrode 202 and the sidewall 203 as a mask, predetermined impurity ions are implanted into the active region to form source / drain regions 204 and 205, respectively.
　続いて、化学気相堆積（ＣＶＤ）法により、半導体基板１００の上にトランジスタを覆うように、例えば酸化シリコン（ＳｉＯ２）又は酸炭化シリコン（ＳｉＯＣ）等からなる第１の層間絶縁膜１０１を形成する。その後、ＣＶＤ法及び化学機械研磨（ＣＭＰ）法により、第１の層間絶縁膜１０１にソースドレイン領域２０４、２０５と電気的に接続される、例えばタングステン（Ｗ）等からなるコンタクトプラグ２０６をそれぞれ形成する。続いて、めっき法及びＣＭＰ法により、第１の層間絶縁膜１０１の上部にコンタクトプラグ２０６と接続される、例えば銅（Ｃｕ）からなる第１の金属配線１０２を選択的に形成する。 Subsequently, a first interlayer insulating film 101 made of, for example, silicon oxide (SiO 2 ) or silicon oxycarbide (SiOC) is formed on the semiconductor substrate 100 so as to cover the transistor by chemical vapor deposition (CVD). Form. Thereafter, contact plugs 206 made of, for example, tungsten (W), which are electrically connected to the source / drain regions 204 and 205, are formed in the first interlayer insulating film 101 by CVD and chemical mechanical polishing (CMP), respectively. To do. Subsequently, a first metal wiring 102 made of, for example, copper (Cu) connected to the contact plug 206 is selectively formed on the first interlayer insulating film 101 by plating and CMP.
　図２にトランジスタの平面構成を示す。例えば、ゲート電極２０２はゲートパッド２０８と接続されている。ソースドレイン領域２０４、２０５は３組が並列に形成され、それぞれドレインパッド２０９及びソースパッド２１０と接続されている。 Fig. 2 shows the planar configuration of the transistor. For example, the gate electrode 202 is connected to the gate pad 208. Three sets of source / drain regions 204 and 205 are formed in parallel and connected to the drain pad 209 and the source pad 210, respectively.
　次に、図３（ａ）に示すように、第１の層間絶縁膜１０１の上に、第１の金属配線１０２を覆うように第２の層間絶縁膜１０１Ａを形成する。続いて、第２の層間絶縁膜１０１Ａに、第１の金属配線１０２と電気的に接続される、例えばタングステン、銅又はアルミニウム（Ａｌ）からなるビアプラグ１０３を形成する。なお、図３（ａ）以降は、図面を簡単にするために、トランジスタ及びコンタクトプラグ２０６を省略する。 Next, as shown in FIG. 3A, a second interlayer insulating film 101 A is formed on the first interlayer insulating film 101 so as to cover the first metal wiring 102. Subsequently, a via plug 103 made of, for example, tungsten, copper, or aluminum (Al), which is electrically connected to the first metal wiring 102, is formed in the second interlayer insulating film 101A. In FIG. 3A and thereafter, the transistor and the contact plug 206 are omitted to simplify the drawing.
　次に、図３（ｂ）に示すように、上面にビアプラグ１０３が露出した第２の層間絶縁膜１０１Ａの上に、有機導電性膜１０４を形成する。ここで、有機導電性膜１０４は、例えば、ポリ３，４－エチレンジオキシチオフェンからなるチオフェン系の有機導電性材料を１－ブタノール等の有機溶剤に溶解してスピン塗布し、続いて１００℃程度のベーキングを行うことにより形成する。続いて、リソグラフィ法により、有機導電性膜１０４の上に、検査用パッドの形成領域を決定するレジストパターン１０５を形成する。ここで、有機導電性膜１０４及びレジストパターン１０５の膜厚は、それぞれ１μｍ程度である。 Next, as shown in FIG. 3B, an organic conductive film 104 is formed on the second interlayer insulating film 101A with the via plug 103 exposed on the upper surface. Here, the organic conductive film 104 is formed by, for example, dissolving a thiophene-based organic conductive material made of poly3,4-ethylenedioxythiophene in an organic solvent such as 1-butanol, followed by spin coating, followed by 100 ° C. It is formed by baking to a certain extent. Subsequently, a resist pattern 105 that determines a formation region of a test pad is formed on the organic conductive film 104 by lithography. Here, the film thicknesses of the organic conductive film 104 and the resist pattern 105 are each about 1 μm.
　次に、図３（ｃ）に示すように、例えば酸素ガスを用いた選択性ドライエッチングにより、レジストパターン１０５をマスクとして有機導電性膜１０４をエッチングすることにより、該有機導電性膜１０４から検査用パッド電極１０４Ａを形成する。ここで、検査用パッド電極１０４Ａの大きさは、プロービングのために十分な大きさを確保できるように、一辺又は径を３０μｍ以上としている。なお、チオフェン系の有機導電性材料の比抵抗は、１０００Ωｃｍ程度と小さく、形成されたトランジスタの基本特性を測定するには十分である。 Next, as shown in FIG. 3C, the organic conductive film 104 is inspected by etching the organic conductive film 104 using the resist pattern 105 as a mask, for example, by selective dry etching using oxygen gas. A pad electrode 104A is formed. Here, the size of the inspection pad electrode 104A is set to 30 μm or more on one side or the diameter so as to ensure a sufficient size for probing. Note that the specific resistance of the thiophene-based organic conductive material is as small as about 1000 Ωcm, which is sufficient for measuring the basic characteristics of the formed transistor.
　なお、第１の実施形態においては、リソグラフィ法及びエッチング法により検査用パッド電極１０４Ａを形成したが、これに代えて、検査用パッド電極１０４Ａの形成には、オフセット印刷法又はインクジェット印刷法等を用いることもできる。さらに、有機導電性膜１０４として、感光性有機導電性膜を用いれば、該有機導電性膜を直接にパターンニングして形成することも可能である。 In the first embodiment, the inspection pad electrode 104A is formed by the lithography method and the etching method. Instead, the inspection pad electrode 104A is formed by an offset printing method, an inkjet printing method, or the like. It can also be used. Further, if a photosensitive organic conductive film is used as the organic conductive film 104, the organic conductive film can be directly patterned.
　また、チオフェン系有機導電性材料としては、ポリ３，４－エチレンジオキシチオフェン以外のチオフェン系の有機導電性材料を用いることも可能である。さらには、導電性材料であるカーボンブラック又はカーボンファイバを、例えばアミン系の非感光性高分子に混合した後に、レジストによるパターニングを行っても、チオフェン系有機導電性材料と同等の効果を得ることができる。 As the thiophene organic conductive material, a thiophene organic conductive material other than poly3,4-ethylenedioxythiophene can be used. Furthermore, even if carbon black or carbon fiber, which is a conductive material, is mixed with, for example, an amine-based non-photosensitive polymer and then patterned with a resist, an effect equivalent to that of a thiophene-based organic conductive material can be obtained. Can do.
　なお、レジストパターン１０５でマスクして有機導電性膜１０４をエッチングする際に、レジストパターン１０５もエッチングにより膜減りして、最終的には消失する。これは、レジストパターン１０５と有機導電性材膜１０４の膜厚及びエッチングレートにほとんど差がないためである。すなわち、検査用パッド電極１０４Ａのパターニング精度に高い精度が要求されないことから、有機導電性膜１０４とレジストパターン１０５とのエッチング選択比をあまり高くしなくてもよいからである。このため、特にパターニング用のレジストを除去する工程を設ける必要はない。 Note that when the organic conductive film 104 is etched by masking with the resist pattern 105, the resist pattern 105 is also reduced by etching and eventually disappears. This is because there is almost no difference in film thickness and etching rate between the resist pattern 105 and the organic conductive material film 104. That is, because the patterning accuracy of the inspection pad electrode 104A is not required to be high, the etching selectivity between the organic conductive film 104 and the resist pattern 105 does not need to be so high. For this reason, it is not necessary to provide a process for removing the resist for patterning.
　また、例えば、レジストパターン１０５の膜厚が過剰であることにより、有機導電性膜１０４の上にレジストが残ったり、逆にレジストパターン１０５の膜厚が不足して、有機導電性膜１０４自体がエッチングされ、該有機導電性膜１０４の表面に厚さが１０ｎｍ程度の表面酸化層が形成されたりすることがある。しかしながら、本実施形態においては、次工程のプローブ検査時に、プローブ針が残存したレジストパターン又は表面酸化層を突き破って有機導電性膜１０４（検査用パッド電極１０４Ａ）と接触するため、これらの膜がプローブ検査に支障を与えることはない。 Further, for example, when the film thickness of the resist pattern 105 is excessive, the resist remains on the organic conductive film 104, or conversely, the film thickness of the resist pattern 105 is insufficient and the organic conductive film 104 itself becomes The surface of the organic conductive film 104 may be etched to form a surface oxide layer having a thickness of about 10 nm. However, in the present embodiment, the probe needle breaks through the remaining resist pattern or surface oxide layer and comes into contact with the organic conductive film 104 (inspection pad electrode 104A) during the probe inspection in the next process. It does not interfere with probe inspection.
　次に、図３（ｄ）に示すように、検査用パッド電極１０４Ａの上にプローブ針１０７等を接触させて、製造工程の途中における被測定素子のプローブ検査を実施する。プローブ検査の結果、電気的特性の異常を示す半導体装置（チップ）が所定の割合又は数量を超えないウエハのみを次工程に進め、該所定の割合又は数量を超える不良のウエハは、本プローブ検査の段階で製造工程から外す。なお、上記の設定値は任意に設定可能である。また、製造工程から外した後のウエハの処置については、通常は廃棄されるが、再利用が可能であれば、それに応じた処理を行うことができる。 Next, as shown in FIG. 3D, the probe needle 107 or the like is brought into contact with the inspection pad electrode 104A, and the probe inspection of the element to be measured is performed during the manufacturing process. As a result of probe inspection, only those wafers whose semiconductor devices (chips) exhibiting abnormal electrical characteristics do not exceed a predetermined ratio or quantity are advanced to the next process, and defective wafers exceeding the predetermined ratio or quantity are subjected to this probe inspection. At this stage, it is removed from the manufacturing process. Note that the set value can be arbitrarily set. Further, the wafer treatment after being removed from the manufacturing process is usually discarded, but if it can be reused, the processing corresponding to that can be performed.
　具体的には、製造工程途中におけるプローブ検査が、少なくとも１層の第１の金属配線１０２を形成した後であれば、例えば図２に示すトランジスタを評価することができる。すなわち、しきい値電圧及びリーク電流等のトランジスタ特性、寄生抵抗特性、コンタクト特性及び接合特性等の検査を行うことができる。検査の結果、得られた特性が所望の特性と異なる場合は、該当チップをウエハとしての製造工程終了後に行う最終プローブ検査時に検査対象チップから除外するか、又は製造工程途中のプローブ検査の終了時点で該当ウエハを異常ウエハと判断して、次工程に進めない等の処置を行う。このようにすれば、半導体装置の製造材料費等を削減できると共に検査費用を削減でき、半導体装置の完成後の１ウエハ当たりの平均歩留まりを向上することができる。さらには、ライン全体の生産効率を向上でき、且つ生産数量を増加させることが可能となる。 Specifically, for example, the transistor shown in FIG. 2 can be evaluated if the probe inspection during the manufacturing process is after the formation of at least one layer of the first metal wiring 102. That is, inspection of transistor characteristics such as threshold voltage and leakage current, parasitic resistance characteristics, contact characteristics, and junction characteristics can be performed. If the obtained characteristics are different from the desired characteristics as a result of the inspection, the corresponding chip is excluded from the inspection target chip at the time of the final probe inspection performed after the manufacturing process as a wafer, or the probe inspection is completed during the manufacturing process. Thus, the corresponding wafer is determined to be an abnormal wafer, and measures such as not proceeding to the next process are performed. In this way, it is possible to reduce the manufacturing material cost of the semiconductor device and the like, reduce the inspection cost, and improve the average yield per wafer after the completion of the semiconductor device. Furthermore, the production efficiency of the entire line can be improved, and the production quantity can be increased.
　また、製造工程途中におけるプローブ検査が、第１の金属配線１０２を２層以上形成した後であれば、ＳＲＡＭ回路、インバータ回路及びアナログ回路等の基本的な回路特性を検査することができる。その後の不良チップの処理又は不良ウエハの処理は上述したとおりである。 Further, if the probe inspection during the manufacturing process is after forming two or more layers of the first metal wiring 102, the basic circuit characteristics such as the SRAM circuit, the inverter circuit, and the analog circuit can be inspected. Subsequent processing of defective chips or processing of defective wafers is as described above.
　さらに、このプローブ検査に基づいて、上層の金属配線のレイアウトを決定する等の対応も可能である。例えば、プローブ検査の結果、ある回路の信号処理（伝播）スピードが他の回路より速いときは、他の回路への信号伝達素子の途中の上層において配線遅延回路を加え、逆に遅い場合には、上層において遅延回路を省略することにより、チップ全体の電気的特性を修正することができ、その結果、クロックスキューに起因する不良を救済でき、歩留まりの最大化を図る等の効果を得ることもできる。 Furthermore, it is possible to take measures such as determining the layout of the upper metal wiring based on this probe inspection. For example, when the signal processing (propagation) speed of a certain circuit is faster than other circuits as a result of probe inspection, a wiring delay circuit is added in the upper layer in the middle of the signal transmission element to other circuits. By omitting the delay circuit in the upper layer, the electrical characteristics of the entire chip can be corrected, and as a result, defects due to clock skew can be relieved and the yield can be maximized. it can.
　次に、図３（ｅ）に示すように、製造工程途中のプローブ検査が終了し、最終プローブ検査時における検査対象チップを決定するか、又は異常ウエハを除外する等の対応を行った後は、プローブ検査で用いた有機導電性材料からなる検査用パッド電極１０４Ａを例えば酸素ガスによるアッシング又は１－ブタノール等の有機溶剤を用いたエッチングにより除去する。 Next, as shown in FIG. 3 (e), after the probe inspection in the middle of the manufacturing process is completed and the inspection target chip at the time of the final probe inspection is determined or the abnormal wafer is excluded, etc. Then, the inspection pad electrode 104A made of an organic conductive material used in the probe inspection is removed by, for example, ashing using oxygen gas or etching using an organic solvent such as 1-butanol.
　ところで、プローブ検査時には、有機導電性膜である検査用パッド電極１０４Ａとプローブ針１０７との接触により、有機導電性材料からなるパーティクルが発生する。しかし、検査用パッド電極１０４Ａの除去時には、該パーティクルも一緒に除去される。また、下層の第１の金属配線１０２及び第２の層間絶縁膜１０１Ａが有機溶剤に溶解することがないため、有機材料からなる検査用パッド電極１０４Ａのみを選択的に除去することが可能となる。但し、このとき、第２の層間絶縁膜１０１Ａにおける有機導電性膜１０４で覆われていない領域もわずかにエッチングされ、有機導電性膜１０４で覆われる領域との間に１０ｎｍ程度の段差を生じるおそれがある。しかし、１０ｎｍ程度の段差は、上層に形成する配線のレジストパターニング時の加工精度を悪化させることはない。 By the way, at the time of probe inspection, particles made of an organic conductive material are generated by contact between the inspection pad electrode 104A, which is an organic conductive film, and the probe needle 107. However, when the inspection pad electrode 104A is removed, the particles are also removed together. In addition, since the lower first metal wiring 102 and the second interlayer insulating film 101A are not dissolved in the organic solvent, only the inspection pad electrode 104A made of an organic material can be selectively removed. . However, at this time, a region of the second interlayer insulating film 101A that is not covered with the organic conductive film 104 is also slightly etched, and a step of about 10 nm may occur between the region covered with the organic conductive film 104. There is. However, the step of about 10 nm does not deteriorate the processing accuracy at the time of resist patterning of the wiring formed in the upper layer.
　次に、図３（ｆ）に示すように、第２の層間絶縁膜１０１Ａの上部に第２の金属配線１０８を形成し、ウエハ状態での最終製品を得る。なお、第２の金属配線１０８は、第２の層間絶縁膜１０１Ａの上に形成した第３の層間絶縁膜に形成してもよい。 Next, as shown in FIG. 3F, a second metal wiring 108 is formed on the second interlayer insulating film 101A to obtain a final product in a wafer state. Note that the second metal wiring 108 may be formed in a third interlayer insulating film formed on the second interlayer insulating film 101A.
　以上説明したように、本実施形態に係る半導体装置の製造方法によると、プローブ検査を行った後に、検査用パッド電極を除去するため、上方の第２の金属配線を形成する際に、プローブ検査時に該検査用パッド電極が占有していた領域を有効に活用することができる。すなわち、検査用パッド電極を除去することによりチップ面積の増大を抑制できるので、１ウエハ当たりのチップの採れ数を増やすことができ、その結果、半導体装置をより低コストで製造することができる。 As described above, according to the manufacturing method of the semiconductor device according to the present embodiment, the probe inspection is performed when the upper second metal wiring is formed in order to remove the inspection pad electrode after performing the probe inspection. Sometimes, the area occupied by the inspection pad electrode can be effectively utilized. That is, since the increase in the chip area can be suppressed by removing the inspection pad electrode, the number of chips collected per wafer can be increased, and as a result, the semiconductor device can be manufactured at a lower cost.
　また、プローブ検査用のパッド電極に有機導電性材料を用いることにより、プローブ検査を行った後に、被測定素子である下層のデバイス又は配線層にダメージを与えることなく、検査用パッド電極を選択的に除去することが可能である。 In addition, by using an organic conductive material for the pad electrode for probe inspection, after performing the probe inspection, the pad electrode for inspection can be selectively selected without damaging the underlying device or wiring layer that is the element to be measured. Can be removed.
　また、ここでは、被測定素子をトランジスタとしたが、トランジスタは一例に過ぎず、一般に半導体装置を構成する能動素子及び受動素子であれば構わない。 In addition, although the element to be measured is a transistor here, the transistor is only an example, and may be an active element and a passive element that generally constitute a semiconductor device.
　（第１の実施形態の一変形例）
　以下、本発明の第１の実施形態の一変形例に係る半導体装置の製造方法について図４を参照しながら説明する。 (One modification of the first embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to a modification of the first embodiment of the present invention will be described with reference to FIG.
　本変形例は、第１の実施形態と比べて金属配線の形成方法が異なる。すなわち、第１の実施形態においては、ビアプラグと金属配線とを別々に形成する、いわゆるシングルダマシン法を用いて金属配線を形成したが、本変形例においては、ビアプラグと金属配線とを同時に形成する、いわゆるデュアルダマシン法を用いて金属配線を形成する。なお、本変形例及び第２の実施形態においては、第１の実施形態で示した構成材料と同一の構成材料には同一の符号を付すことにより説明を省略する。 This modification is different from the first embodiment in the formation method of the metal wiring. That is, in the first embodiment, the metal wiring is formed by using a so-called single damascene method in which the via plug and the metal wiring are separately formed. However, in this modification, the via plug and the metal wiring are formed at the same time. The metal wiring is formed using a so-called dual damascene method. In the present modification and the second embodiment, the same reference numerals are given to the same constituent materials as those shown in the first embodiment, and the description thereof is omitted.
　まず、図４（ａ）に示すように、図１及び図２に示したトランジスタが形成された半導体基板１００における第１の層間絶縁膜１０１の上に、第１の金属配線１０２を覆うように第２の層間絶縁膜１０１Ａを形成する。続いて、第２の層間絶縁膜１０１Ａに、第１の金属配線１０２と接続される下層のビア部とその上層の溝部に例えばタングステン、銅又はアルミニウムを埋め込むことにより第２の金属配線１１０を形成する。 First, as shown in FIG. 4A, the first metal wiring 102 is covered on the first interlayer insulating film 101 in the semiconductor substrate 100 on which the transistor shown in FIGS. 1 and 2 is formed. A second interlayer insulating film 101A is formed. Subsequently, the second metal wiring 110 is formed in the second interlayer insulating film 101A by burying, for example, tungsten, copper, or aluminum in the lower via portion connected to the first metal wiring 102 and the upper groove portion. To do.
　次に、図４（ｂ）に示すように、第２の金属配線１１０を含め第２の層間絶縁膜１０１Ａを覆うように、例えば酸化シリコンからなる誘電体膜１１１を形成する。 Next, as shown in FIG. 4B, a dielectric film 111 made of, for example, silicon oxide is formed so as to cover the second interlayer insulating film 101A including the second metal wiring 110.
　次に、図４（ｃ）に示すように、リソグラフィ法及びドライエッチング法により、誘電体膜１１１に第２の金属配線１１０の一部を露出する開口部を形成して、該誘電体膜１１１からマスク膜１１１ａを形成する。 Next, as shown in FIG. 4C, an opening for exposing a part of the second metal wiring 110 is formed in the dielectric film 111 by lithography and dry etching, and the dielectric film 111 is formed. Then, a mask film 111a is formed.
　次に、図４（ｄ）に示すように、開口部を含むマスク膜１１１ａの上に、有機導電性膜１０４を形成する。有機導電性膜１０４は、第１の実施形態と同様に、例えば、ポリ３，４－エチレンジオキシチオフェンからなるチオフェン系の有機導電性材料を１－ブタノール等の有機溶剤に溶解してスピン塗布し、その後、１００℃程度のベーキングを行って形成する。 Next, as shown in FIG. 4D, the organic conductive film 104 is formed on the mask film 111a including the opening. The organic conductive film 104 is spin-coated by dissolving a thiophene-based organic conductive material made of poly3,4-ethylenedioxythiophene in an organic solvent such as 1-butanol, as in the first embodiment. After that, it is formed by baking at about 100 ° C.
　次に、図４（ｅ）に示すように、リソグラフィ法により、有機導電性膜１０４の上に、検査用パッドの形成領域を決定するレジストパターン１０５を形成する。 Next, as shown in FIG. 4E, a resist pattern 105 is formed on the organic conductive film 104 to determine the formation area of the inspection pad by lithography.
　次に、図４（ｆ）に示すように、例えば酸素ガスを用いた選択性ドライエッチングにより、レジストパターン１０５をマスクとして有機導電性膜１０４をエッチングすることにより、有機導電性膜１０４から検査用パッド電極１０４Ａを形成する。 Next, as shown in FIG. 4F, for example, the organic conductive film 104 is etched from the organic conductive film 104 by etching using the resist pattern 105 as a mask by selective dry etching using oxygen gas. A pad electrode 104A is formed.
　次に、図４（ｇ）に示すように、検査用パッド電極１０４Ａの上にプローブ針１０７等を接触させて、製造工程の途中における被測定素子のプローブ検査を実施する。 Next, as shown in FIG. 4G, the probe needle 107 or the like is brought into contact with the inspection pad electrode 104A, and the probe inspection of the element to be measured is performed during the manufacturing process.
　次に、図４（ｈ）に示すように、最終プローブ検査時における検査対象チップを決定する、又は異常ウエハを除外する等の処置を行う。その後、プローブ検査で用いた有機導電性膜１０４である検査用パッド電極１０４Ａを、例えば酸素ガスによるアッシング又は１－ブタノール等の有機溶剤を用いたエッチングにより除去する。 Next, as shown in FIG. 4 (h), measures such as determining a chip to be inspected at the time of final probe inspection or excluding abnormal wafers are performed. Thereafter, the inspection pad electrode 104A, which is the organic conductive film 104 used in the probe inspection, is removed by, for example, ashing using oxygen gas or etching using an organic solvent such as 1-butanol.
　次に、図４（ｉ）に示すように、第２の金属配線１１０を含むマスク膜１１１ａの上に、第３の層間絶縁膜１１２を形成し、続いて、デュアルダマシン法を用いて、第３の層間絶縁膜１１２に第３の金属配線１１３を形成する。さらに、図示はしていないが、デュアルダマシン法による３層目以降の金属配線を形成して、所望の半導体装置を得る。 Next, as shown in FIG. 4I, a third interlayer insulating film 112 is formed on the mask film 111a including the second metal wiring 110, and then the second damascene method is used. A third metal wiring 113 is formed in the third interlayer insulating film 112. Further, although not shown in the drawing, the third and subsequent metal wirings are formed by a dual damascene method to obtain a desired semiconductor device.
　以上説明したように、本変形例に係る半導体装置の製造方法によると、金属配線の形成にデュアルダマシン法を用いた場合でも、プローブ検査を行った後に、検査用パッド電極を除去するため、その後の配線層の形成時に、プローブ検査中に生じたパーティクルを除去することができる。また、検査用パッド電極を除去することから、該検査用パッド電極が占有していた領域を有効に活用することができ、チップ面積の増大を抑制できる。さらに、検査用パッド電極に有機導電性材料を用いることにより、プローブ検査の後に、下層のデバイス又は配線層にダメージを与えることなく、検査用パッド電極を選択的に除去することが可能となる。 As described above, according to the method of manufacturing a semiconductor device according to the present modification, even when the dual damascene method is used for forming the metal wiring, the probe pad electrode is removed after the probe inspection, and thereafter When the wiring layer is formed, particles generated during probe inspection can be removed. Further, since the inspection pad electrode is removed, the region occupied by the inspection pad electrode can be used effectively, and an increase in the chip area can be suppressed. Further, by using an organic conductive material for the inspection pad electrode, the inspection pad electrode can be selectively removed after the probe inspection without damaging the underlying device or wiring layer.
　（第２の実施形態）
　以下、本発明の第２の実施形態に係る半導体装置の製造方法について図５を参照しながら説明する。 (Second Embodiment)
Hereinafter, a method for fabricating a semiconductor device according to the second embodiment of the present invention will be described with reference to FIG.
　第１の実施形態では、１つのチップを製造する途中の被測定素子、例えばトランジスタに対してプローブ検査を行う場合について説明したが、第２の実施形態においては、チップをプリント基板に実装する際に、その製造工程の途中における被測定素子のプローブ検査を行う場合について説明する。具体的には、第２の実施形態においては、最上層の金属配線を形成した後に被測定素子のプローブ検査を行う。 In the first embodiment, the case where probe inspection is performed on an element to be measured, for example, a transistor, in the process of manufacturing one chip has been described. However, in the second embodiment, when a chip is mounted on a printed board. Next, a case where probe inspection of the element to be measured is performed during the manufacturing process will be described. Specifically, in the second embodiment, after the uppermost metal wiring is formed, the probe inspection of the element to be measured is performed.
　まず、図５（ａ）に示すように、例えば、第１の実施形態と同様に、第２の層間絶縁膜１０１Ａにビアプラグ１０３及び第２の金属配線１０８を選択的に形成する。その後、第２の金属配線１０８を含む第２の層間絶縁膜１０１Ａの上に、第３の層間絶縁膜１０１Ｂを形成する。続いて、第３の層間絶縁膜１０１Ｂにビアプラグ１０３及び第３の金属配線１２０を順次形成する。その後、最上層の配線である第３の金属配線１２０を含む第３の層間絶縁膜１０１Ｂの上に、チップ表面からの吸湿を防止するための、例えばポリベンゾオキサゾール（ＰＢＯ）からなる保護膜１２１を形成する。続いて、リソグラフィ法及びドライエッチング法により、保護膜１２１に第３の金属配線１２０を露出する接続孔１２１ａを開口する。 First, as shown in FIG. 5A, for example, as in the first embodiment, the via plug 103 and the second metal wiring 108 are selectively formed in the second interlayer insulating film 101A. Thereafter, a third interlayer insulating film 101B is formed on the second interlayer insulating film 101A including the second metal wiring 108. Subsequently, the via plug 103 and the third metal wiring 120 are sequentially formed in the third interlayer insulating film 101B. Thereafter, a protective film 121 made of, for example, polybenzoxazole (PBO) for preventing moisture absorption from the chip surface is formed on the third interlayer insulating film 101B including the third metal wiring 120 which is the uppermost wiring. Form. Subsequently, a connection hole 121a that exposes the third metal wiring 120 is formed in the protective film 121 by lithography and dry etching.
　次に、図５（ｂ）に示すように、接続孔１２１ａを含む保護膜１２１の上に、例えば、ポリ３，４－エチレンジオキシチオフェンからなるチオフェン系の有機導電性材料を１－ブタノール等の有機溶剤に溶解してスピン塗布し、その後、１００℃程度のベーキングを行って有機導電性膜１０４として形成する。続いて、リソグラフィ法により、有機導電性膜１０４における接続孔１２１ａを含む領域の上に、検査用パッド電極の形成領域を覆うレジストパターン１０５を形成する。このとき、有機導電性膜１０４及びレジストパターン１０５の膜厚は、それぞれ１μｍ程度である。なお、有機導電性膜１０４を形成する工程は、上述の手順に限定されず、例えば、ウエハをダイシングして各チップに分離し、後述するチップ接続用電極を蒸着した後、すなわち、該チップ接続用電極の上に形成してもよい。さらには、保護膜１２１を形成する前であってもよい。 Next, as shown in FIG. 5B, on the protective film 121 including the connection hole 121a, for example, a thiophene-based organic conductive material made of poly3,4-ethylenedioxythiophene is 1-butanol or the like. The organic conductive film 104 is formed by dissolving in an organic solvent and spin coating, followed by baking at about 100 ° C. Subsequently, a resist pattern 105 is formed by lithography on the region including the connection hole 121a in the organic conductive film 104 so as to cover the formation region of the inspection pad electrode. At this time, the film thicknesses of the organic conductive film 104 and the resist pattern 105 are each about 1 μm. The step of forming the organic conductive film 104 is not limited to the above-described procedure. For example, the wafer is diced and separated into chips, and a chip connection electrode described later is deposited, that is, the chip connection. It may be formed on the electrode. Further, it may be before the protective film 121 is formed.
　次に、図５（ｃ）に示すように、例えば酸素を用いた選択性ドライエッチングにより、レジストパターン１０５をマスクとして有機導電性膜１０４をエッチングすることにより、有機導電性膜１０４から検査用パッド電極１０４Ａを形成する。なお、第１の実施形態と同様に、有機導電性膜１０４をエッチングする際に、レジストパターン１０５も膜減りし、最終的には消失する。 Next, as shown in FIG. 5C, the organic conductive film 104 is etched from the organic conductive film 104 by using, for example, selective dry etching using oxygen to mask the resist pattern 105 as a mask. The electrode 104A is formed. As in the first embodiment, when the organic conductive film 104 is etched, the resist pattern 105 is also reduced and eventually disappears.
　次に、図５（ｄ）に示すように、検査用パッド電極１０４Ａの上にプローブ針１０７等を接触させて、製造工程の途中における被測定素子のプローブ検査を実施する。このとき、第１の実施形態と同様に、被測定素子の電気的特性が所望の特性を示せば、次工程に移す。また、被測定素子の電気的特性が特性異常を示す場合には、該当チップを製造工程終了後のプローブ検査の対象チップから除外するか、またはそのウエハを異常ウエハと判断して、次工程に移さない等の処置を行う。このようにすると、後工程である組立工程を含む製造材料費等の削減又は組立後の平均歩留まりを向上することができると共に、製造ライン全体の生産効率及び生産数量を増加させることが可能となる。 Next, as shown in FIG. 5D, the probe needle 107 or the like is brought into contact with the inspection pad electrode 104A, and the probe inspection of the element to be measured is performed during the manufacturing process. At this time, as in the first embodiment, if the electrical characteristics of the element to be measured show desired characteristics, the process proceeds to the next step. If the electrical characteristics of the device under test indicate abnormal characteristics, either exclude the chip from the target chip for probe inspection after the end of the manufacturing process, or determine that the wafer is an abnormal wafer and proceed to the next process. Take measures such as not moving. If it does in this way, while being able to reduce the manufacturing material cost including the assembly process which is a post process, or to improve the average yield after the assembly, it becomes possible to increase the production efficiency and the production quantity of the entire production line. .
　次に、図５（ｅ）に示すように、製造工程の途中におけるプローブ検査が終了し、最終プローブ検査時における検査対象チップを決定するか、又は異常ウエハを除外する等の対応を行った後は、プローブ検査で用いた有機導電性膜である検査用パッド電極１０４Ａを例えば酸素ガスによるアッシング又は１－ブタノール等の有機溶剤を用いたエッチングにより除去する。 Next, as shown in FIG. 5 (e), after the probe inspection in the middle of the manufacturing process is completed and the inspection target chip at the time of the final probe inspection is determined, or the abnormal wafer is excluded, etc. Removes the test pad electrode 104A, which is an organic conductive film used in the probe test, by, for example, ashing using oxygen gas or etching using an organic solvent such as 1-butanol.
　前述したように、プローブ検査時には、検査用パッド電極１０４Ａとプローブ針１０７との接触により、有機導電性材料からなるパーティクルが発生するものの、検査用パッド電極１０４Ａの除去時には、該パーティクルも一緒に除去される。また、第３の金属配線１２０及び第３の層間絶縁膜１０１Ｂが有機溶剤には溶解しないため、有機材料からなる検査用パッド電極１０４Ａパッドのみを選択的に除去することが可能となる。但し、このとき、第３の層間絶縁膜１０１Ｂにおける有機導電性膜１０４で覆われていない領域もわずかにエッチングされ、有機導電性膜１０４で覆われる領域との間に１０ｎｍ程度の段差を生じる可能性がある。しかし、この程度の段差は、製品の特性に影響を与えることはない。 As described above, during probe inspection, particles made of an organic conductive material are generated due to contact between the inspection pad electrode 104A and the probe needle 107. However, when the inspection pad electrode 104A is removed, the particles are also removed together. Is done. In addition, since the third metal wiring 120 and the third interlayer insulating film 101B are not dissolved in the organic solvent, only the inspection pad electrode 104A pad made of an organic material can be selectively removed. However, at this time, a region of the third interlayer insulating film 101B that is not covered with the organic conductive film 104 is also slightly etched, and a step of about 10 nm can be generated between the region covered with the organic conductive film 104. There is sex. However, this level difference does not affect the product characteristics.
　次に、図５（ｆ）に示すように、ウエハ状の半導体基板１００の裏面をバックグラインドした後、各チップに分離する。その後、組立工程において、真空蒸着法により、第３の金属配線１２０の上に下地金属層であるチップ接続用電極１２２を形成する。その後、チップ接続用電極１２２の上に半田ボール１２３を設ける。 Next, as shown in FIG. 5F, after the back surface of the wafer-like semiconductor substrate 100 is back-ground, it is separated into chips. Thereafter, in an assembly process, a chip connection electrode 122 as a base metal layer is formed on the third metal wiring 120 by a vacuum deposition method. Thereafter, solder balls 123 are provided on the chip connection electrodes 122.
　次に、図５（ｇ）に示すように、図５（ｆ）の状態のチップを、チップ接続用電極１２２と保持基板であるプリント基板１３０の上面に形成された電極との間に半田ボール１２３を介在させた状態で保持する、いわゆるフリップチップ法により実装する。ここで、プリント基板１３０の内部には、シリコンからなる貫通電極１３１が該プリント基板１３０の表裏方向に貫通して形成されており、その裏面から露出する電極にも半田ボール１２３が設けられている。 Next, as shown in FIG. 5G, a solder ball is placed between the chip in the state shown in FIG. 5F between the chip connection electrode 122 and the electrode formed on the upper surface of the printed circuit board 130 as the holding substrate. Mounting is performed by a so-called flip-chip method in which 123 is held in an intervening state. Here, a through electrode 131 made of silicon is formed inside the printed circuit board 130 so as to penetrate in the front and back direction of the printed circuit board 130, and solder balls 123 are also provided on the electrode exposed from the back surface. .
　以下に、第２の実施形態に係る効果について図６を参照しながら説明する。 Hereinafter, the effects according to the second embodiment will be described with reference to FIG.
　図６（ａ）は比較用の従来の半導体装置であって、チップ１４０の完成状態でプローブ検査を行う場合の平面構成を示している。完成後のチップ１４０には、他のチップ等と接続する際のチップ間の電気的導通を確保するための、それぞれ直径が２０μｍ～４００μｍ程度の半田ボール１２３が接続可能な、通常のパッド形成領域が必要となる。さらに、従来の半導体装置においては、チップ１４０の周縁部に複数の検査用パッド電極１４１を設ける必要があり、また、半田ボール１２３の下に形成されている通常のパッド電極（図示せず）と検査用パッド電極１４１とを電気的に接続する金属配線１４２を引き回す領域が必要となる。 FIG. 6A is a conventional semiconductor device for comparison, and shows a planar configuration when the probe inspection is performed in a completed state of the chip 140. The completed chip 140 has a normal pad forming area to which solder balls 123 each having a diameter of about 20 μm to 400 μm can be connected to ensure electrical continuity between the chips when connecting to other chips and the like. Is required. Further, in the conventional semiconductor device, it is necessary to provide a plurality of inspection pad electrodes 141 on the peripheral portion of the chip 140, and a normal pad electrode (not shown) formed under the solder ball 123; A region for routing the metal wiring 142 that electrically connects the inspection pad electrode 141 is required.
　これに対し、第２の実施形態においては、図５（ｃ）に示す工程において、第３の金属配線１２０自体に有機導電性材料からなる検査用パッド電極１０４Ａを形成し、図５（ｄ）に示す工程においてプローブ検査を行い、図５（ｅ）に示す工程において、プローブ検査時にパッド電極として使用した検査用パッド電極１０４Ａを除去する。従って、図６（ｂ）の平面構成に示すように、第２の実施形態においては、従来のようなプローブ検査を行うための検査用パッド電極１４１をチップ１４０の周縁部に設ける必要がない。従って、通常のパッド電極と検査用パッド電極１４１とを電気的に接続する金属配線１４２を引き回す領域も不要となる。このため、チップ１４０自体の面積を大幅に低減することができるので、チップの採れ数の減少を防止でき、その結果、より低コストに半導体装置を製造することができる。 On the other hand, in the second embodiment, in the step shown in FIG. 5C, the test pad electrode 104A made of an organic conductive material is formed on the third metal wiring 120 itself, and FIG. Probe inspection is performed in the step shown in FIG. 5B, and in the step shown in FIG. 5E, the inspection pad electrode 104A used as the pad electrode in the probe inspection is removed. Therefore, as shown in the plan configuration of FIG. 6B, in the second embodiment, it is not necessary to provide the pad electrode for inspection 141 for performing the probe inspection as in the prior art on the peripheral portion of the chip 140. Therefore, a region for routing the metal wiring 142 that electrically connects the normal pad electrode and the inspection pad electrode 141 is also unnecessary. For this reason, since the area of the chip 140 itself can be greatly reduced, a reduction in the number of chips can be prevented, and as a result, a semiconductor device can be manufactured at a lower cost.
　（第２の実施形態の一変形例）
　以下、本発明の第２の実施形態の一変形例に係る半導体装置の製造方法について図７を参照しながら説明する。 (One Modification of Second Embodiment)
Hereinafter, a method for manufacturing a semiconductor device according to a modification of the second embodiment of the present invention will be described with reference to FIG.
　本変形例は、第２の実施形態と比べて、プローブ検査を終了した後のチップの実装形態が異なる。すなわち、第２の実施形態においては、チップをプリント基板１３０に直接に実装したが、本変形例においては、チップを保持基板である配線基板（インターポーザ）１３２に実装した後、さらに、該配線基板１３２をプリント基板１３０の上に実装する。 This modified example is different from the second embodiment in the chip mounting form after the probe inspection is completed. That is, in the second embodiment, the chip is directly mounted on the printed circuit board 130. However, in this modified example, after the chip is mounted on the wiring board (interposer) 132 that is the holding board, the wiring board is further mounted. 132 is mounted on the printed circuit board 130.
　具体的には、図５（ｆ）の状態のチップを、例えばシリコンからなる貫通電極１３３が形成された配線基板１３２の上に半田ボール１２３を介在させてフリップチップ実装する。なお、配線基板１３２には、貫通電極１３３に加え、メモリ回路又はロジック回路等が形成されていてもよい。その後、チップを保持した配線基板１３２を、プリント基板１３０の上に半田ボール１２３を介在させてフリップチップ実装し、実装品として完成させる。 Specifically, the chip in the state shown in FIG. 5F is flip-chip mounted on the wiring substrate 132 on which the through electrode 133 made of, for example, silicon is formed with the solder balls 123 interposed. Note that a memory circuit, a logic circuit, or the like may be formed on the wiring board 132 in addition to the through electrode 133. Thereafter, the wiring substrate 132 holding the chip is flip-chip mounted on the printed circuit board 130 with the solder balls 123 interposed therebetween, thereby completing a mounted product.
　このように、本変形例においても、第２の実施形態と同様に、プローブ検査時にパッド電極として使用した検査用パッド電極を除去するため、従来のようなプローブ検査を行うための検査用パッド電極をチップの周縁部に設ける必要がない。従って、通常のパッド電極と検査用パッド電極とを電気的に接続する金属配線を引き回す領域が不要となる。これにより、チップ自体の面積を大幅に低減することができるので、チップの採れ数の減少を防止でき、より低コストに半導体装置を製造することができる。
（第３の実施形態）
　以下、本発明の第３の実施形態に係る半導体装置の製造方法について図８を参照しながら説明する。 As described above, also in the present modification, in the same way as in the second embodiment, the inspection pad electrode for performing the conventional probe inspection is removed in order to remove the inspection pad electrode used as the pad electrode during the probe inspection. Need not be provided at the peripheral edge of the chip. Therefore, a region for routing the metal wiring that electrically connects the normal pad electrode and the inspection pad electrode becomes unnecessary. As a result, the area of the chip itself can be greatly reduced, so that a reduction in the number of chips can be prevented, and a semiconductor device can be manufactured at a lower cost.
(Third embodiment)
A method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described below with reference to FIG.
　第３の実施形態は、それぞれ半導体デバイスチップである第１のチップ１００ａと第２のチップ１００ｂとを互いに重ねることによって形成される半導体装置の製造方法である。 The third embodiment is a method of manufacturing a semiconductor device formed by stacking a first chip 100a and a second chip 100b, which are semiconductor device chips, respectively.
　図８に示すように、第３の実施形態に係る半導体装置は、例えば、第１のチップ１００ａと第２のチップ１００ｂとを、半田ボール１２３等を介して互いに貼り合わせて構成されている。 As shown in FIG. 8, the semiconductor device according to the third embodiment is configured, for example, by bonding a first chip 100a and a second chip 100b to each other via solder balls 123 and the like.
　具体的には、第１のチップ１００ａの素子形成面上の金属配線層１１４ａの表面に形成されたチップ接続用電極となる複数の金属配線１２０ａと、第２のチップ１００ｂの素子形成面上の金属配線層１１４ｂの表面に形成されたチップ接続用電極となる複数の金属配線１２０ｂとを半田ボール１２３を介して張り合わせることにより、２つのチップ１００ａ、１００ｂ同士の間の電気信号が交換可能となる。 Specifically, a plurality of metal wirings 120a serving as chip connection electrodes formed on the surface of the metal wiring layer 114a on the element formation surface of the first chip 100a, and an element formation surface of the second chip 100b. By bonding a plurality of metal wirings 120b formed on the surface of the metal wiring layer 114b as chip connection electrodes via solder balls 123, electrical signals between the two chips 100a and 100b can be exchanged. Become.
　第３の実施形態に係る半導体装置は、第２のチップ１００ｂの裏面が金属からなるリードフレーム２１３にボンディングされている。また、第２のチップ１００ｂの表面に設けられたボンディングパッド２１１には、金等からなるボンディングワイヤ２１２がワイヤボンディングされている。 In the semiconductor device according to the third embodiment, the back surface of the second chip 100b is bonded to a lead frame 213 made of metal. A bonding wire 212 made of gold or the like is wire-bonded to the bonding pad 211 provided on the surface of the second chip 100b.
　第３の実施形態においては、ワイヤボンディング用のボンディングパッド２１１は、一辺の長さが少なくとも５０μｍの正方形状であって、チップ１００ａ、１００ｂ間の電気信号を交換するための金属配線１２０ａ、１２０ｂは、いずれも一辺の長さが１０μｍ程度の円形状又は正方形状である。 In the third embodiment, the bonding pad 211 for wire bonding has a square shape with a side length of at least 50 μm, and the metal wirings 120a and 120b for exchanging electrical signals between the chips 100a and 100b are , Both are circular or square with a side length of about 10 μm.
　さらに、第３の実施形態においては、第１のチップ１００ａ及び第２のチップ１００ｂは、互いに貼り合わせる前に各チップ１００ａ、１００ｂに有機導電性材料からなる検査用パッドを形成し、形成した検査用パッドとプローブ針とを用いた検査を実施して、各チップ１００ａ、１００ｂの良否を判定した後に、この検査用パッドを除去する。その後、第２のチップ１００ｂの金属配線１２０ｂの上に半田ボール１２３をそれぞれ形成し、第１のチップ１００ａの金属配線１２０ａと第２のチップ１００ｂの金属配線１２０ｂとの位置合わせを行って互いに圧着する。 Furthermore, in the third embodiment, the first chip 100a and the second chip 100b are formed by forming test pads made of an organic conductive material on the chips 100a and 100b before bonding to each other. The inspection pad is removed after the inspection using the probe pad and the probe needle is carried out to determine the quality of each chip 100a, 100b. Thereafter, solder balls 123 are respectively formed on the metal wirings 120b of the second chip 100b, and the metal wirings 120a of the first chip 100a and the metal wirings 120b of the second chip 100b are aligned and crimped together. To do.
　この時点で、各チップ１００ａ、１００ｂは、検査によって不良ではないことが判明しているため、不良チップはあらかじめ除外されている。 At this point, since it is found that the chips 100a and 100b are not defective by inspection, the defective chips are excluded in advance.
　図９は、例えば第１のチップ１００ａの検査時の様子を模式的に表している。図９に示すように、本発明に係る導電性を有する有機材料からなる検査用パッド１０４ａは、例えばスクライブ領域３０１ａ、又はチップ表面におけるチップ間接続用の金属配線１２０ａを設けない領域、又はチップ表面が絶縁膜により保護されている場合は、検査に用いないチップ間接続用の金属配線１２０ａ上の領域に亘って形成されている。ここで、検査用パッドの大きさは５０μｍ程度であって、パッドの最小ピッチは６０μｍとしている。検査の方法は、第１の実施形態において説明したとおりであり、ここでの繰り返しの説明は省略する。 FIG. 9 schematically shows, for example, a state when the first chip 100a is inspected. As shown in FIG. 9, the test pad 104a made of an organic material having conductivity according to the present invention includes, for example, a scribe region 301a, a region where no chip-to-chip metal wiring 120a is provided on the chip surface, or a chip surface. Is protected by an insulating film, it is formed over a region on the metal wiring 120a for chip-to-chip connection that is not used for inspection. Here, the size of the inspection pad is about 50 μm, and the minimum pitch of the pads is 60 μm. The inspection method is the same as that described in the first embodiment, and repeated description thereof is omitted here.
　従来、このように２つのチップ同士を張り合わせる構造を形成する場合は、各チップを個別に電気的に検査することは困難である。その理由は、特にチップ間の電気信号を交換するための金属配線１２０ａの数が増えた場合に、金属配線１２０ａの寸法を小さくする必要があり、プローブ針を正確に金属配線１２０ａの上に接触させることができないためである。また、プローブ針を金属配線１２０ａ上に接触させることができたとしても、金属配線１２０ａの表面がプローブ針との接触による損傷、又はパーティクルの発生に起因して、後の貼り合わせ工程において接触抵抗が増加し、円滑なチップ間の電気信号の交換が困難となるためである。このため、半導体装置の電気的な検査は、チップを張り合わせた後に実施せざるを得ず、２つのチップの一方だけが不良であっても、張り合わせ後の半導体装置として不良となるため、大きなコストの損失を招く。 Conventionally, when forming a structure in which two chips are bonded to each other as described above, it is difficult to electrically inspect each chip individually. The reason is that, particularly when the number of metal wirings 120a for exchanging electrical signals between chips is increased, it is necessary to reduce the size of the metal wiring 120a, and the probe needle is accurately contacted on the metal wiring 120a. It is because it cannot be made to do. Even if the probe needle can be brought into contact with the metal wiring 120a, the surface of the metal wiring 120a is damaged due to contact with the probe needle or the generation of particles, so that the contact resistance in the subsequent bonding step This is because it becomes difficult to smoothly exchange electrical signals between chips. For this reason, electrical inspection of the semiconductor device must be performed after the chips are bonded together, and even if only one of the two chips is defective, it becomes a defective semiconductor device after bonding, resulting in a large cost. Incurs loss.
　しかしながら、第３の実施形態においては、第１の実施形態において説明したように、例えば、各金属配線１２０ａ、１２０ｂが１０μｍ以下の大きさであっても、その周囲に導電性を有する有機材料からなる検査用パッド１０４ａを形成することによって、各チップ１００ａ、１００ｂの良否を判定することが可能となる。すなわち、各チップ１００ａ、１００ｂのそれぞれを個別に検査した結果、良品と判定されたチップ同士を貼り合わせることが可能となる。さらに、各金属配線１２０ａ、１２０ｂの表面は、プローブ針と直接に接触しないため、配線表面の損傷及びパーティクルが発生することがなく、半田ボール１２３等によって、低抵抗で安定したチップ間の接続を実現できる。その結果、張り合わせを行った後の半導体装置が不良となる確率を極めて小さくすることができ、製造コストを大きく削減することができる。 However, in the third embodiment, as described in the first embodiment, for example, even if each metal wiring 120a, 120b has a size of 10 μm or less, it is made of an organic material having conductivity around it. By forming the test pad 104a, it is possible to determine the quality of each chip 100a, 100b. That is, as a result of individually inspecting each of the chips 100a and 100b, chips determined as non-defective products can be bonded together. Furthermore, since the surface of each metal wiring 120a, 120b is not in direct contact with the probe needle, damage to the wiring surface and particles are not generated, and a stable connection between chips can be achieved with a solder ball 123 or the like. realizable. As a result, the probability that the semiconductor device after bonding is defective can be extremely reduced, and the manufacturing cost can be greatly reduced.
　本発明に係る半導体装置の製造方法は、製造途中で被測定素子のプローブ検査を行っても、半導体装置にダメージを与えることなく、パッドから発生するパーティクルを除去できると共に、チップ面積の増大、ひいてはチップ採れ数の減少を防止することができ、特に、インラインでの半導体装置のプローブ検査を含む半導体装置の製造方法等に有用である。 The method for manufacturing a semiconductor device according to the present invention can remove particles generated from a pad without damaging the semiconductor device even if probe inspection of the element to be measured is performed in the middle of manufacturing, and also increases the chip area, and thus It is possible to prevent a reduction in the number of chips collected, and is particularly useful for a method for manufacturing a semiconductor device including in-line probe inspection of a semiconductor device.
１００　　半導体基板
１００ａ　第１のチップ
１００ｂ　第２のチップ
１０１　　第１の層間絶縁膜
１０１Ａ　第２の層間絶縁膜
１０１Ｂ　第３の層間絶縁膜
１０２　　第１の金属配線
１０３　　ビアプラグ
１０４　　有機導電性膜
１０４Ａ　検査用パッド電極
１０４ａ　検査用パッド
１０５　　レジストパターン
１０７　　プローブ針
１０８　　第２の金属配線
１１０　　第２の金属配線
１１１　　誘電体膜
１１１ａ　マスク膜
１１２　　第３の層間絶縁膜
１１３　　第３の金属配線
１１４ａ　多層配線層
１１４ｂ　多層配線層
１２０　　第３の金属配線
１２０ａ　金属配線（チップ接続用電極）
１２０ｂ　金属配線（チップ接続用電極）
１２１　　保護膜
１２１ａ　接続孔
１２２　　チップ接続用電極
１２３　　半田ボール
１３０　　プリント基板（保持基板）
１３１　　貫通電極
１３２　　配線基板（保持基板）
１３３　　貫通電極
２００　　素子分離膜
２０１　　ゲート絶縁膜
２０２　　ゲート電極
２０３　　サイドウォール
２０４　　ソースドレイン領域
２０５　　ソースドレイン領域
２０６　　コンタクトプラグ
２０８　　ゲートパッド
２０９　　ドレインパッド
２１０　　ソースパッド
２１１　　ボンディングパッド
２１２　　ボンディングワイヤ
２１３　　リードフレーム
３０１ａ　スクライブ領域 100 Semiconductor substrate 100a First chip 100b Second chip 101 First interlayer insulating film 101A Second interlayer insulating film 101B Third interlayer insulating film 102 First metal wiring 103 Via plug 104 Organic conductive film 104A For inspection Pad electrode 104a Inspection pad 105 Resist pattern 107 Probe needle 108 Second metal wiring 110 Second metal wiring 111 Dielectric film 111a Mask film 112 Third interlayer insulating film 113 Third metal wiring 114a Multi-layer wiring layer 114b Multi-layer Wiring layer 120 Third metal wiring 120a Metal wiring (chip connection electrode)
120b Metal wiring (chip connection electrode)
121 Protective Film 121a Connection Hole 122 Chip Connection Electrode 123 Solder Ball 130 Printed Circuit Board (Holding Board)
131 Through electrode 132 Wiring board (holding board)
133 Through-electrode 200 Element isolation film 201 Gate insulating film 202 Gate electrode 203 Side wall 204 Source drain region 205 Source drain region 206 Contact plug 208 Gate pad 209 Drain pad 210 Source pad 211 Bonding pad 212 Bonding wire 213 Lead frame 301a Scribe region

Claims (10)

  1. 　被測定素子が形成された半導体基板の上に、第１の層間絶縁膜を形成する工程（ａ）と、
    　前記第１の層間絶縁膜に、前記被測定素子と電気的に接続される第１のビアと、該第１のビアと電気的に接続される第１の配線とを形成する工程（ｂ）と、
    　前記第１の層間絶縁膜の上に、有機導電性膜からなる検査用パッド電極を前記第１の配線と接続されるように形成する工程（ｃ）と、
    　前記検査用パッド電極にプローブ針を接触させた状態で、前記被測定素子の電気的特性を測定する工程（ｄ）と、
    　前記工程（ｄ）よりも後に、前記検査用パッド電極を除去する工程（ｅ）とを備えている半導体装置の製造方法。     A step (a) of forming a first interlayer insulating film on the semiconductor substrate on which the device under measurement is formed;
    Forming a first via electrically connected to the device under test and a first wiring electrically connected to the first via in the first interlayer insulating film (b) When,
    Forming a test pad electrode made of an organic conductive film on the first interlayer insulating film so as to be connected to the first wiring;
    A step (d) of measuring electrical characteristics of the device under test in a state where a probe needle is in contact with the pad electrode for inspection;
    A method of manufacturing a semiconductor device, comprising: a step (e) of removing the inspection pad electrode after the step (d).
  2. 　請求項１において、
    　前記工程（ｅ）よりも後に、
    　前記第１の層間絶縁膜の上に、前記第１の配線を覆うように第２の層間絶縁膜を形成する工程（ｆ）と、
    　前記第２の層間絶縁膜に、前記第１の配線と電気的に接続される第２のビアと、該第２のビアと電気的に接続される第２の配線とを形成する工程（ｇ）とをさらに備えている半導体装置の製造方法。     In claim 1,
    After the step (e),
    Forming a second interlayer insulating film on the first interlayer insulating film so as to cover the first wiring;
    Forming a second via electrically connected to the first wiring and a second wiring electrically connected to the second via in the second interlayer insulating film (g) And a semiconductor device manufacturing method.
  3. 　請求項１又は２において、
    　前記工程（ｂ）は、
    　前記第１の層間絶縁膜に前記被測定素子を露出するビアホールを形成する工程（ｂ１）と、
    　形成された前記ビアホールに導電性材料を埋め込むことにより前記第１のビアを形成する工程（ｂ２）と、
    　前記第１の層間絶縁膜における前記第１のビアを含む領域に配線溝を形成する工程（ｂ３）と、
    　形成された前記配線溝に導電性材料を埋め込むことにより前記第１の配線を形成する工程（ｂ４）とを含む半導体装置の製造方法。     In claim 1 or 2,
    The step (b)
    Forming a via hole that exposes the device under test in the first interlayer insulating film (b1);
    A step (b2) of forming the first via by embedding a conductive material in the formed via hole;
    Forming a wiring groove in a region including the first via in the first interlayer insulating film (b3);
    And a step (b4) of forming the first wiring by burying a conductive material in the formed wiring groove.
  4. 　請求項１又は２において、
    　前記工程（ｂ）は、
    　前記第１の層間絶縁膜に前記被測定素子を露出するビアホール及び該ビアホールを含む領域に配線溝を形成する工程（ｂ５）と、
    　形成された前記ビアホール及び配線溝に導電性材料を埋め込むことにより前記第１のビア及び第１の配線を形成する工程（ｂ６）とを含む半導体装置の製造方法。     In claim 1 or 2,
    The step (b)
    Forming a via hole exposing the device under test in the first interlayer insulating film and a wiring groove in a region including the via hole (b5);
    Forming the first via and the first wiring by embedding a conductive material in the formed via hole and wiring trench.
  5. 　請求項１において、
    　前記工程（ｅ）よりも後に、
    　前記第１の層間絶縁膜の上に、前記第１の配線と接続されるようにチップ接続用電極を形成する工程（ｆ）と、
    　保持基板の上に前記半導体基板を保持すると共に、前記チップ接続用電極を介して前記半導体基板と前記保持基板とを電気的に接続する工程（ｇ）とをさらに備えている半導体装置の製造方法。     In claim 1,
    After the step (e),
    Forming a chip connection electrode on the first interlayer insulating film so as to be connected to the first wiring;
    A method of manufacturing a semiconductor device, further comprising a step (g) of holding the semiconductor substrate on a holding substrate and electrically connecting the semiconductor substrate and the holding substrate via the chip connection electrode. .
  6. 　請求項５において、
    　前記保持基板は、プリント基板であり、
    　前記工程（ｇ）において、前記半導体基板の前記チップ接続用電極を前記プリント基板の主面と対向させることにより、前記チップ接続用電極を前記プリント基板と接続する半導体装置の製造方法。     In claim 5,
    The holding substrate is a printed circuit board;
    A method of manufacturing a semiconductor device, wherein in the step (g), the chip connection electrode is connected to the printed circuit board by causing the chip connection electrode of the semiconductor substrate to face the main surface of the printed circuit board.
  7. 　請求項５において、
    　前記保持基板は、少なくとも貫通電極を有し、
    　前記工程（ｇ）において、前記半導体基板の前記チップ接続用電極を前記保持基板の主面と対向させることにより、前記チップ接続用電極を前記保持基板と接続し、
    　前記工程（ｇ）よりも後に、前記保持基板における前記半導体基板と反対側の面をプリント基板の主面と対向させることにより、前記保持基板を前記プリント基板と電気的に接続する工程（ｈ）をさらに備えている半導体装置の製造方法。     In claim 5,
    The holding substrate has at least a through electrode,
    In the step (g), the chip connecting electrode is connected to the holding substrate by making the chip connecting electrode of the semiconductor substrate face the main surface of the holding substrate,
    After the step (g), the step of electrically connecting the holding substrate to the printed circuit board by causing the surface of the holding substrate opposite to the semiconductor substrate to face the main surface of the printed circuit board (h) A method for manufacturing a semiconductor device, further comprising:
  8. 　被測定素子が形成された半導体基板の上に、第１の層間絶縁膜を形成する工程（ａ）と、
    　前記第１の層間絶縁膜に、前記被測定素子と電気的に接続される第１のビアと、該第１のビアと電気的に接続される第１の配線とを形成する工程（ｂ）と、
    　前記第１の層間絶縁膜の上に、前記第１の配線と接続されるようにチップ接続用電極を形成する工程（ｃ）と、
    　前記第１の層間絶縁膜の上に、有機導電性膜からなる検査用パッド電極を前記第１の配線と接続されるように形成する工程（ｄ）と、
    　前記検査用パッド電極にプローブ針を接触させた状態で、前記被測定素子の電気的特性を測定する工程（ｅ）と、
    　前記工程（ｅ）よりも後に、前記検査用パッド電極を除去する工程（ｆ）と、
    　前記工程（ａ）から工程（ｆ）までを実施された第１チップと、前記工程（ａ）から工程（ｆ）までを実施された第２チップとを準備し、前記第１チップ及び第２チップを互いに対向させることにより、前記第１チップ及び第２チップにおける前記チップ接続用電極同士を接続し、前記第１のチップ及び第２チップからなる積層チップ構造を形成する工程（ｇ）とを備えている半導体装置の製造方法。     A step (a) of forming a first interlayer insulating film on the semiconductor substrate on which the device under measurement is formed;
    Forming a first via electrically connected to the device under test and a first wiring electrically connected to the first via in the first interlayer insulating film (b) When,
    Forming a chip connecting electrode on the first interlayer insulating film so as to be connected to the first wiring (c);
    Forming a test pad electrode made of an organic conductive film on the first interlayer insulating film so as to be connected to the first wiring;
    A step (e) of measuring electrical characteristics of the device under test in a state where a probe needle is in contact with the pad electrode for inspection;
    A step (f) of removing the inspection pad electrode after the step (e);
    A first chip that has been performed from step (a) to step (f) and a second chip that has been performed from step (a) to step (f) are prepared, and the first chip and the second chip are prepared. A step (g) of connecting the chip connecting electrodes in the first chip and the second chip by making the chips face each other to form a laminated chip structure composed of the first chip and the second chip; A method of manufacturing a semiconductor device.
  9. 　請求項１～８のうちのいずれか１項において、
    　前記有機導電性膜は、チオフェン系有機導電性材料を含む半導体装置の製造方法。     In any one of claims 1 to 8,
    The method for manufacturing a semiconductor device, wherein the organic conductive film includes a thiophene-based organic conductive material.
  10. 　請求項９において、
    　前記チオフェン系有機導電性材料は、ポリ３，４－エチレンジオキシチオフェンを含む半導体装置の製造方法。     In claim 9,
    The method for manufacturing a semiconductor device, wherein the thiophene-based organic conductive material includes poly 3,4-ethylenedioxythiophene.
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