WO2012011207A1 - Procédé de fabrication d'un dispositif semi-conducteur comprenant une étape de retrait d'une électrode pastille pour inspection - Google Patents

Procédé de fabrication d'un dispositif semi-conducteur comprenant une étape de retrait d'une électrode pastille pour inspection Download PDF

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Publication number
WO2012011207A1
WO2012011207A1 PCT/JP2011/001515 JP2011001515W WO2012011207A1 WO 2012011207 A1 WO2012011207 A1 WO 2012011207A1 JP 2011001515 W JP2011001515 W JP 2011001515W WO 2012011207 A1 WO2012011207 A1 WO 2012011207A1
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chip
insulating film
interlayer insulating
wiring
forming
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PCT/JP2011/001515
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English (en)
Japanese (ja)
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藤井政了
安井孝俊
平井健裕
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L2224/039—Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0392—Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step
    • H01L2224/03921—Methods of manufacturing bonding areas involving a specific sequence of method steps specifically adapted to include a probing step by repairing the bonding area damaged by the probing step
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    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that enables probe inspection of an element to be measured during manufacture.
  • a first interlayer insulating film 2 made of a plurality of layers is formed on a semiconductor substrate 1 made of silicon on which a device under test (not shown) such as a transistor is formed.
  • the first metal wiring layer 4, the first contact plug 3, and the second metal wiring layer 5 that are electrically connected to the element to be measured are sequentially formed on each interlayer insulating film so as to be electrically connected to each other. To do.
  • a first metal pad 6 connected to the second metal wiring layer 5 is selectively formed on the first interlayer insulating film 2.
  • the probe 7 is brought into contact with the formed first metal pad 6, and the electrical characteristics of the element to be measured are measured.
  • a second layer composed of a plurality of layers is formed on the first interlayer insulating film 2 including the first metal pad 6.
  • the interlayer insulating film 11 is formed, and the second contact plug 10 and the third metal wiring layer 8 electrically connected to the second metal wiring layer 5 are sequentially electrically connected to each interlayer insulating film.
  • a second metal pad 9 connected to the third metal wiring layer 8 is formed on the second interlayer insulating film 11.
  • the probe 7 is brought into contact with the second metal pad 9 to measure various electrical characteristics of the finished product.
  • the probe 7 is brought into contact with the first metal pad 6 to measure the electrical characteristics of the element to be measured. At this time, a part of the surface of the first metal pad 6 is peeled off by contact with the probe 7, and as a result, particles that are metal powder are generated.
  • the process proceeds to the next process with the first metal pad 6 left, so the first metal pad 6 occupies.
  • the same metal wiring layer cannot be formed in the region. That is, the metal wiring layer that is the same layer as the first metal pad 6 needs to be formed avoiding the first metal pad 6, resulting in an increase in chip area. For this reason, there arises a problem that the number of chips taken per wafer is reduced and the manufacturing cost per chip is increased.
  • the first interlayer insulating film 2 formed at the end of the first metal pad 6 is left.
  • the wiring is formed in the upper layer due to the difference in level, a problem of manufacturing defects due to insufficient processing accuracy in the lithography process also occurs.
  • a step is formed in the vicinity of the first metal pad 6 on the surface of the resist film, and the focus during exposure may not be achieved.
  • the present invention can remove particles generated from a pad without damaging a semiconductor device even if probe inspection of an element to be measured is performed in the middle of manufacturing, and also increases the chip area and the chip. It aims to be able to prevent the decrease in the number of harvests.
  • a method for manufacturing a semiconductor device is configured such that an inspection pad electrode formed on an interlayer insulating film being manufactured is used and then the inspection pad electrode is removed.
  • the first method for manufacturing a semiconductor device includes a step (a) of forming a first interlayer insulating film on a semiconductor substrate on which an element to be measured is formed, and a first interlayer Forming a first via electrically connected to the device to be measured and a first wiring electrically connected to the first via in the insulating film; and a first interlayer A step (c) of forming an inspection pad electrode made of an organic conductive film on the insulating film so as to be connected to the first wiring, and a probe needle in contact with the inspection pad electrode A step (d) of measuring the electrical characteristics of the measuring element and a step (e) of removing the inspection pad electrode after the step (d) are provided.
  • the electrical characteristics of the element to be measured are measured in a state where the probe needle is in contact with the inspection pad electrode made of an organic conductive film, and then the inspection pad electrode is removed. . For this reason, even if probe inspection of the element under measurement is performed during manufacturing, the pad electrode for inspection can be easily and reliably removed without damaging the semiconductor device, and particles generated from the pad can be removed. In addition, since the same layer wiring as the pad can be arranged in the pad formation region, an increase in the chip area can be prevented.
  • the first semiconductor device manufacturing method includes a step (f) of forming a second interlayer insulating film on the first interlayer insulating film so as to cover the first wiring after the step (e). And (g) forming a second via electrically connected to the first wiring and a second wiring electrically connected to the second via in the second interlayer insulating film. And may be further provided.
  • the step (b) includes a step (b1) of forming a via hole exposing the device under test in the first interlayer insulating film, and embedding a conductive material in the formed via hole.
  • a step (b2) of forming a via hole exposing the device under test in the first interlayer insulating film, and embedding a conductive material in the formed via hole.
  • the step (b) is formed by a step (b5) of forming a via hole exposing the element to be measured in the first interlayer insulating film and a wiring groove in a region including the via hole. And a step (b6) of forming a first via and a first wiring by embedding a conductive material in the via hole and the wiring groove.
  • the manufacturing method of the first semiconductor device includes a step (f) of forming a chip connection electrode on the first interlayer insulating film so as to be connected to the first wiring after the step (e).
  • the method may further comprise the step (g) of holding the semiconductor substrate on the holding substrate and electrically connecting the semiconductor substrate and the holding substrate via the chip connection electrode.
  • the holding substrate is a printed board
  • the chip connecting electrode may be connected to the printed board by making the chip connecting electrode of the semiconductor substrate face the main surface of the printed board. Good.
  • the holding substrate has at least a through electrode
  • the chip connecting electrode is made to face the main surface of the holding substrate by causing the chip connecting electrode of the semiconductor substrate to face the holding substrate.
  • the step (h) of electrically connecting the holding substrate to the printed circuit board by causing the surface of the holding substrate opposite to the semiconductor substrate to face the main surface of the printed circuit board.
  • the second semiconductor device manufacturing method includes a step (a) of forming a first interlayer insulating film on a semiconductor substrate on which an element to be measured is formed, and a first interlayer insulating film, A step (b) of forming a first via electrically connected to the device to be measured and a first wiring electrically connected to the first via; and on the first interlayer insulating film (C) forming a chip connection electrode so as to be connected to the first wiring; and an inspection pad electrode made of an organic conductive film is formed on the first wiring on the first interlayer insulating film. More than the step (d), the step (e) of measuring the electrical characteristics of the device under test with the probe needle in contact with the test pad electrode, and the step (e).
  • the first chip that has been subjected to the step (f) of removing the pad electrode for inspection and the steps (a) to (f) The second chip that has been subjected to the steps (a) to (f) is prepared, and the first chip and the second chip are made to face each other, so that the chip connecting electrodes in the first chip and the second chip are connected to each other. And a step (g) of forming a laminated chip structure including the first chip and the second chip.
  • the organic conductive film may include a thiophene-based organic conductive material.
  • poly3,4-ethylenedioxythiophene can be used as the thiophene organic conductive material.
  • the inspection pad electrode can be easily and reliably removed without damaging the semiconductor device.
  • particles generated from the pad can be removed, and wiring in the same layer as the pad can be arranged in the pad formation region, so that an increase in chip area and a reduction in the number of chips can be prevented.
  • FIG. 1 is a cross-sectional view showing a process for forming a device under test, which is a method for manufacturing a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a plan view showing a device under test, which is a method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 3A to FIG. 3F are cross-sectional views in order of steps showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4A to FIG. 4I are cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to a modification of the first embodiment of the present invention.
  • FIG. 5G are cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 6A is a plan view showing a conventional semiconductor device.
  • FIG. 6B is a plan view showing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 7 is a cross-sectional view showing one step of a method for manufacturing a semiconductor device according to a modification of the second embodiment of the present invention.
  • FIG. 8 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device according to the third embodiment of the present invention.
  • FIG. 9 is a plan view showing one step in the method of manufacturing a semiconductor device according to the third embodiment of the present invention.
  • FIG. 10A to FIG. 10D are cross-sectional views in order of steps showing a method of manufacturing a semiconductor device including probe inspection during manufacturing according to a conventional example.
  • a transistor as a device to be measured is formed on a semiconductor substrate 100 made of silicon.
  • the element isolation film 200 is selectively formed on the semiconductor substrate 100 to form an active region.
  • the gate insulating film 201 and the gate electrode 202 are formed on the active region, and the sidewalls 203 are formed on the side surfaces of the gate insulating film 201 and the gate electrode 202.
  • predetermined impurity ions are implanted into the active region to form source / drain regions 204 and 205, respectively.
  • a first interlayer insulating film 101 made of, for example, silicon oxide (SiO 2 ) or silicon oxycarbide (SiOC) is formed on the semiconductor substrate 100 so as to cover the transistor by chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • contact plugs 206 made of, for example, tungsten (W), which are electrically connected to the source / drain regions 204 and 205, are formed in the first interlayer insulating film 101 by CVD and chemical mechanical polishing (CMP), respectively.
  • CMP chemical mechanical polishing
  • a first metal wiring 102 made of, for example, copper (Cu) connected to the contact plug 206 is selectively formed on the first interlayer insulating film 101 by plating and CMP.
  • Fig. 2 shows the planar configuration of the transistor.
  • the gate electrode 202 is connected to the gate pad 208.
  • Three sets of source / drain regions 204 and 205 are formed in parallel and connected to the drain pad 209 and the source pad 210, respectively.
  • a second interlayer insulating film 101 A is formed on the first interlayer insulating film 101 so as to cover the first metal wiring 102.
  • a via plug 103 made of, for example, tungsten, copper, or aluminum (Al), which is electrically connected to the first metal wiring 102, is formed in the second interlayer insulating film 101A.
  • the transistor and the contact plug 206 are omitted to simplify the drawing.
  • an organic conductive film 104 is formed on the second interlayer insulating film 101A with the via plug 103 exposed on the upper surface.
  • the organic conductive film 104 is formed by, for example, dissolving a thiophene-based organic conductive material made of poly3,4-ethylenedioxythiophene in an organic solvent such as 1-butanol, followed by spin coating, followed by 100 ° C. It is formed by baking to a certain extent.
  • a resist pattern 105 that determines a formation region of a test pad is formed on the organic conductive film 104 by lithography.
  • the film thicknesses of the organic conductive film 104 and the resist pattern 105 are each about 1 ⁇ m.
  • the organic conductive film 104 is inspected by etching the organic conductive film 104 using the resist pattern 105 as a mask, for example, by selective dry etching using oxygen gas.
  • a pad electrode 104A is formed.
  • the size of the inspection pad electrode 104A is set to 30 ⁇ m or more on one side or the diameter so as to ensure a sufficient size for probing.
  • the specific resistance of the thiophene-based organic conductive material is as small as about 1000 ⁇ cm, which is sufficient for measuring the basic characteristics of the formed transistor.
  • the inspection pad electrode 104A is formed by the lithography method and the etching method. Instead, the inspection pad electrode 104A is formed by an offset printing method, an inkjet printing method, or the like. It can also be used. Further, if a photosensitive organic conductive film is used as the organic conductive film 104, the organic conductive film can be directly patterned.
  • thiophene organic conductive material a thiophene organic conductive material other than poly3,4-ethylenedioxythiophene can be used. Furthermore, even if carbon black or carbon fiber, which is a conductive material, is mixed with, for example, an amine-based non-photosensitive polymer and then patterned with a resist, an effect equivalent to that of a thiophene-based organic conductive material can be obtained. Can do.
  • the resist pattern 105 is also reduced by etching and eventually disappears. This is because there is almost no difference in film thickness and etching rate between the resist pattern 105 and the organic conductive material film 104. That is, because the patterning accuracy of the inspection pad electrode 104A is not required to be high, the etching selectivity between the organic conductive film 104 and the resist pattern 105 does not need to be so high. For this reason, it is not necessary to provide a process for removing the resist for patterning.
  • the film thickness of the resist pattern 105 when the film thickness of the resist pattern 105 is excessive, the resist remains on the organic conductive film 104, or conversely, the film thickness of the resist pattern 105 is insufficient and the organic conductive film 104 itself becomes
  • the surface of the organic conductive film 104 may be etched to form a surface oxide layer having a thickness of about 10 nm.
  • the probe needle breaks through the remaining resist pattern or surface oxide layer and comes into contact with the organic conductive film 104 (inspection pad electrode 104A) during the probe inspection in the next process. It does not interfere with probe inspection.
  • the probe needle 107 or the like is brought into contact with the inspection pad electrode 104A, and the probe inspection of the element to be measured is performed during the manufacturing process.
  • the probe inspection only those wafers whose semiconductor devices (chips) exhibiting abnormal electrical characteristics do not exceed a predetermined ratio or quantity are advanced to the next process, and defective wafers exceeding the predetermined ratio or quantity are subjected to this probe inspection.
  • the set value can be arbitrarily set.
  • the wafer treatment after being removed from the manufacturing process is usually discarded, but if it can be reused, the processing corresponding to that can be performed.
  • the transistor shown in FIG. 2 can be evaluated if the probe inspection during the manufacturing process is after the formation of at least one layer of the first metal wiring 102. That is, inspection of transistor characteristics such as threshold voltage and leakage current, parasitic resistance characteristics, contact characteristics, and junction characteristics can be performed. If the obtained characteristics are different from the desired characteristics as a result of the inspection, the corresponding chip is excluded from the inspection target chip at the time of the final probe inspection performed after the manufacturing process as a wafer, or the probe inspection is completed during the manufacturing process. Thus, the corresponding wafer is determined to be an abnormal wafer, and measures such as not proceeding to the next process are performed. In this way, it is possible to reduce the manufacturing material cost of the semiconductor device and the like, reduce the inspection cost, and improve the average yield per wafer after the completion of the semiconductor device. Furthermore, the production efficiency of the entire line can be improved, and the production quantity can be increased.
  • transistor characteristics such as threshold voltage and leakage current, parasitic resistance characteristics, contact characteristics, and junction characteristics can be performed. If the obtained characteristics are different from the
  • the basic circuit characteristics such as the SRAM circuit, the inverter circuit, and the analog circuit can be inspected. Subsequent processing of defective chips or processing of defective wafers is as described above.
  • determining the layout of the upper metal wiring based on this probe inspection. For example, when the signal processing (propagation) speed of a certain circuit is faster than other circuits as a result of probe inspection, a wiring delay circuit is added in the upper layer in the middle of the signal transmission element to other circuits. By omitting the delay circuit in the upper layer, the electrical characteristics of the entire chip can be corrected, and as a result, defects due to clock skew can be relieved and the yield can be maximized. it can.
  • the inspection pad electrode 104A made of an organic conductive material used in the probe inspection is removed by, for example, ashing using oxygen gas or etching using an organic solvent such as 1-butanol.
  • a second metal wiring 108 is formed on the second interlayer insulating film 101A to obtain a final product in a wafer state.
  • the second metal wiring 108 may be formed in a third interlayer insulating film formed on the second interlayer insulating film 101A.
  • the probe inspection is performed when the upper second metal wiring is formed in order to remove the inspection pad electrode after performing the probe inspection.
  • the area occupied by the inspection pad electrode can be effectively utilized. That is, since the increase in the chip area can be suppressed by removing the inspection pad electrode, the number of chips collected per wafer can be increased, and as a result, the semiconductor device can be manufactured at a lower cost.
  • the pad electrode for inspection can be selectively selected without damaging the underlying device or wiring layer that is the element to be measured. Can be removed.
  • the element to be measured is a transistor here, the transistor is only an example, and may be an active element and a passive element that generally constitute a semiconductor device.
  • This modification is different from the first embodiment in the formation method of the metal wiring. That is, in the first embodiment, the metal wiring is formed by using a so-called single damascene method in which the via plug and the metal wiring are separately formed. However, in this modification, the via plug and the metal wiring are formed at the same time. The metal wiring is formed using a so-called dual damascene method.
  • the same reference numerals are given to the same constituent materials as those shown in the first embodiment, and the description thereof is omitted.
  • the first metal wiring 102 is covered on the first interlayer insulating film 101 in the semiconductor substrate 100 on which the transistor shown in FIGS. 1 and 2 is formed.
  • a second interlayer insulating film 101A is formed.
  • the second metal wiring 110 is formed in the second interlayer insulating film 101A by burying, for example, tungsten, copper, or aluminum in the lower via portion connected to the first metal wiring 102 and the upper groove portion. To do.
  • a dielectric film 111 made of, for example, silicon oxide is formed so as to cover the second interlayer insulating film 101A including the second metal wiring 110.
  • an opening for exposing a part of the second metal wiring 110 is formed in the dielectric film 111 by lithography and dry etching, and the dielectric film 111 is formed. Then, a mask film 111a is formed.
  • the organic conductive film 104 is formed on the mask film 111a including the opening.
  • the organic conductive film 104 is spin-coated by dissolving a thiophene-based organic conductive material made of poly3,4-ethylenedioxythiophene in an organic solvent such as 1-butanol, as in the first embodiment. After that, it is formed by baking at about 100 ° C.
  • a resist pattern 105 is formed on the organic conductive film 104 to determine the formation area of the inspection pad by lithography.
  • the organic conductive film 104 is etched from the organic conductive film 104 by etching using the resist pattern 105 as a mask by selective dry etching using oxygen gas.
  • a pad electrode 104A is formed.
  • the probe needle 107 or the like is brought into contact with the inspection pad electrode 104A, and the probe inspection of the element to be measured is performed during the manufacturing process.
  • the inspection pad electrode 104A which is the organic conductive film 104 used in the probe inspection, is removed by, for example, ashing using oxygen gas or etching using an organic solvent such as 1-butanol.
  • a third interlayer insulating film 112 is formed on the mask film 111a including the second metal wiring 110, and then the second damascene method is used.
  • a third metal wiring 113 is formed in the third interlayer insulating film 112. Further, although not shown in the drawing, the third and subsequent metal wirings are formed by a dual damascene method to obtain a desired semiconductor device.
  • the probe pad electrode is removed after the probe inspection, and thereafter When the wiring layer is formed, particles generated during probe inspection can be removed. Further, since the inspection pad electrode is removed, the region occupied by the inspection pad electrode can be used effectively, and an increase in the chip area can be suppressed. Further, by using an organic conductive material for the inspection pad electrode, the inspection pad electrode can be selectively removed after the probe inspection without damaging the underlying device or wiring layer.
  • the case where probe inspection is performed on an element to be measured for example, a transistor, in the process of manufacturing one chip has been described.
  • the second embodiment when a chip is mounted on a printed board.
  • probe inspection of the element to be measured is performed during the manufacturing process. Specifically, in the second embodiment, after the uppermost metal wiring is formed, the probe inspection of the element to be measured is performed.
  • the via plug 103 and the second metal wiring 108 are selectively formed in the second interlayer insulating film 101A.
  • a third interlayer insulating film 101B is formed on the second interlayer insulating film 101A including the second metal wiring 108.
  • the via plug 103 and the third metal wiring 120 are sequentially formed in the third interlayer insulating film 101B.
  • a protective film 121 made of, for example, polybenzoxazole (PBO) for preventing moisture absorption from the chip surface is formed on the third interlayer insulating film 101B including the third metal wiring 120 which is the uppermost wiring.
  • a connection hole 121a that exposes the third metal wiring 120 is formed in the protective film 121 by lithography and dry etching.
  • a thiophene-based organic conductive material made of poly3,4-ethylenedioxythiophene is 1-butanol or the like.
  • the organic conductive film 104 is formed by dissolving in an organic solvent and spin coating, followed by baking at about 100 ° C.
  • a resist pattern 105 is formed by lithography on the region including the connection hole 121a in the organic conductive film 104 so as to cover the formation region of the inspection pad electrode.
  • the film thicknesses of the organic conductive film 104 and the resist pattern 105 are each about 1 ⁇ m.
  • the step of forming the organic conductive film 104 is not limited to the above-described procedure.
  • the wafer is diced and separated into chips, and a chip connection electrode described later is deposited, that is, the chip connection. It may be formed on the electrode. Further, it may be before the protective film 121 is formed.
  • the organic conductive film 104 is etched from the organic conductive film 104 by using, for example, selective dry etching using oxygen to mask the resist pattern 105 as a mask.
  • the electrode 104A is formed.
  • the resist pattern 105 is also reduced and eventually disappears.
  • the probe needle 107 or the like is brought into contact with the inspection pad electrode 104A, and the probe inspection of the element to be measured is performed during the manufacturing process.
  • the process proceeds to the next step. If the electrical characteristics of the device under test indicate abnormal characteristics, either exclude the chip from the target chip for probe inspection after the end of the manufacturing process, or determine that the wafer is an abnormal wafer and proceed to the next process. Take measures such as not moving. If it does in this way, while being able to reduce the manufacturing material cost including the assembly process which is a post process, or to improve the average yield after the assembly, it becomes possible to increase the production efficiency and the production quantity of the entire production line. .
  • test pad electrode 104A which is an organic conductive film used in the probe test, by, for example, ashing using oxygen gas or etching using an organic solvent such as 1-butanol.
  • a chip connection electrode 122 as a base metal layer is formed on the third metal wiring 120 by a vacuum deposition method. Thereafter, solder balls 123 are provided on the chip connection electrodes 122.
  • a solder ball is placed between the chip in the state shown in FIG. 5F between the chip connection electrode 122 and the electrode formed on the upper surface of the printed circuit board 130 as the holding substrate.
  • Mounting is performed by a so-called flip-chip method in which 123 is held in an intervening state.
  • a through electrode 131 made of silicon is formed inside the printed circuit board 130 so as to penetrate in the front and back direction of the printed circuit board 130, and solder balls 123 are also provided on the electrode exposed from the back surface. .
  • FIG. 6A is a conventional semiconductor device for comparison, and shows a planar configuration when the probe inspection is performed in a completed state of the chip 140.
  • the completed chip 140 has a normal pad forming area to which solder balls 123 each having a diameter of about 20 ⁇ m to 400 ⁇ m can be connected to ensure electrical continuity between the chips when connecting to other chips and the like. Is required.
  • the test pad electrode 104A made of an organic conductive material is formed on the third metal wiring 120 itself, and FIG. Probe inspection is performed in the step shown in FIG. 5B, and in the step shown in FIG. 5E, the inspection pad electrode 104A used as the pad electrode in the probe inspection is removed. Therefore, as shown in the plan configuration of FIG. 6B, in the second embodiment, it is not necessary to provide the pad electrode for inspection 141 for performing the probe inspection as in the prior art on the peripheral portion of the chip 140. Therefore, a region for routing the metal wiring 142 that electrically connects the normal pad electrode and the inspection pad electrode 141 is also unnecessary. For this reason, since the area of the chip 140 itself can be greatly reduced, a reduction in the number of chips can be prevented, and as a result, a semiconductor device can be manufactured at a lower cost.
  • This modified example is different from the second embodiment in the chip mounting form after the probe inspection is completed. That is, in the second embodiment, the chip is directly mounted on the printed circuit board 130. However, in this modified example, after the chip is mounted on the wiring board (interposer) 132 that is the holding board, the wiring board is further mounted. 132 is mounted on the printed circuit board 130.
  • the chip in the state shown in FIG. 5F is flip-chip mounted on the wiring substrate 132 on which the through electrode 133 made of, for example, silicon is formed with the solder balls 123 interposed.
  • the through electrode 133 made of, for example, silicon
  • a memory circuit, a logic circuit, or the like may be formed on the wiring board 132 in addition to the through electrode 133.
  • the wiring substrate 132 holding the chip is flip-chip mounted on the printed circuit board 130 with the solder balls 123 interposed therebetween, thereby completing a mounted product.
  • the inspection pad electrode for performing the conventional probe inspection is removed in order to remove the inspection pad electrode used as the pad electrode during the probe inspection. Need not be provided at the peripheral edge of the chip. Therefore, a region for routing the metal wiring that electrically connects the normal pad electrode and the inspection pad electrode becomes unnecessary. As a result, the area of the chip itself can be greatly reduced, so that a reduction in the number of chips can be prevented, and a semiconductor device can be manufactured at a lower cost.
  • the third embodiment is a method of manufacturing a semiconductor device formed by stacking a first chip 100a and a second chip 100b, which are semiconductor device chips, respectively.
  • the semiconductor device according to the third embodiment is configured, for example, by bonding a first chip 100a and a second chip 100b to each other via solder balls 123 and the like.
  • a plurality of metal wirings 120b formed on the surface of the metal wiring layer 114b as chip connection electrodes via solder balls 123, electrical signals between the two chips 100a and 100b can be exchanged.
  • the back surface of the second chip 100b is bonded to a lead frame 213 made of metal.
  • a bonding wire 212 made of gold or the like is wire-bonded to the bonding pad 211 provided on the surface of the second chip 100b.
  • the bonding pad 211 for wire bonding has a square shape with a side length of at least 50 ⁇ m, and the metal wirings 120a and 120b for exchanging electrical signals between the chips 100a and 100b are , Both are circular or square with a side length of about 10 ⁇ m.
  • the first chip 100a and the second chip 100b are formed by forming test pads made of an organic conductive material on the chips 100a and 100b before bonding to each other.
  • the inspection pad is removed after the inspection using the probe pad and the probe needle is carried out to determine the quality of each chip 100a, 100b.
  • solder balls 123 are respectively formed on the metal wirings 120b of the second chip 100b, and the metal wirings 120a of the first chip 100a and the metal wirings 120b of the second chip 100b are aligned and crimped together. To do.
  • the defective chips are excluded in advance.
  • FIG. 9 schematically shows, for example, a state when the first chip 100a is inspected.
  • the test pad 104a made of an organic material having conductivity according to the present invention includes, for example, a scribe region 301a, a region where no chip-to-chip metal wiring 120a is provided on the chip surface, or a chip surface. Is protected by an insulating film, it is formed over a region on the metal wiring 120a for chip-to-chip connection that is not used for inspection.
  • the size of the inspection pad is about 50 ⁇ m, and the minimum pitch of the pads is 60 ⁇ m.
  • the inspection method is the same as that described in the first embodiment, and repeated description thereof is omitted here.
  • each metal wiring 120a, 120b has a size of 10 ⁇ m or less, it is made of an organic material having conductivity around it.
  • the test pad 104a it is possible to determine the quality of each chip 100a, 100b. That is, as a result of individually inspecting each of the chips 100a and 100b, chips determined as non-defective products can be bonded together.
  • the surface of each metal wiring 120a, 120b is not in direct contact with the probe needle, damage to the wiring surface and particles are not generated, and a stable connection between chips can be achieved with a solder ball 123 or the like. realizable. As a result, the probability that the semiconductor device after bonding is defective can be extremely reduced, and the manufacturing cost can be greatly reduced.
  • the method for manufacturing a semiconductor device according to the present invention can remove particles generated from a pad without damaging the semiconductor device even if probe inspection of the element to be measured is performed in the middle of manufacturing, and also increases the chip area, and thus It is possible to prevent a reduction in the number of chips collected, and is particularly useful for a method for manufacturing a semiconductor device including in-line probe inspection of a semiconductor device.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Selon l'invention, un premier film isolant intercalaire (101) est déposé sur un substrat semi-conducteur (100) sur lequel est formé un élément à mesurer. Ensuite, une fiche de contact (206) reliée électriquement à l'élément à mesurer et une première ligne de câblage (102) reliée électriquement à la fiche de contact (206) sont formées dans le premier film isolant intercalaire (101). Une électrode pastille pour inspection (104A) composée d'un film conducteur organique est alors formée sur le premier film isolant intercalaire (101) de manière à être reliée à la première ligne de câblage (102). Ensuite, les caractéristiques électriques de l'élément à mesurer sont mesurées, tout en maintenant une aiguille sonde (107) en contact avec l'électrode pastille pour inspection (104A). Puis, l'électrode pastille pour inspection (104A) est retirée.
PCT/JP2011/001515 2010-07-21 2011-03-15 Procédé de fabrication d'un dispositif semi-conducteur comprenant une étape de retrait d'une électrode pastille pour inspection WO2012011207A1 (fr)

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JP2010-163708 2010-07-21

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014146780A (ja) * 2013-01-28 2014-08-14 Win Semiconductors Corp 半導体集積回路
EP4227693A4 (fr) * 2020-12-29 2024-03-20 Origin Quantum Computing Tech Hefei Co Ltd Structure de test de puce quantique et procédé de fabrication associé, et procédé de test de puce quantique et procédé de fabrication

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62193137A (ja) * 1986-02-19 1987-08-25 Hitachi Ltd 半導体装置の製造方法
JPH02181457A (ja) * 1989-01-06 1990-07-16 Fuji Electric Co Ltd バンプ電極を備える集積回路装置の試験方法
JPH02199849A (ja) * 1989-01-27 1990-08-08 Nec Corp 集積回路装置
JP2003332449A (ja) * 2002-05-15 2003-11-21 Nec Electronics Corp 半導体装置の製造方法
JP2005116606A (ja) * 2003-10-03 2005-04-28 Seiko Epson Corp 電子デバイスの検査方法
JP2005317867A (ja) * 2004-04-30 2005-11-10 Sony Corp 半導体装置の製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62193137A (ja) * 1986-02-19 1987-08-25 Hitachi Ltd 半導体装置の製造方法
JPH02181457A (ja) * 1989-01-06 1990-07-16 Fuji Electric Co Ltd バンプ電極を備える集積回路装置の試験方法
JPH02199849A (ja) * 1989-01-27 1990-08-08 Nec Corp 集積回路装置
JP2003332449A (ja) * 2002-05-15 2003-11-21 Nec Electronics Corp 半導体装置の製造方法
JP2005116606A (ja) * 2003-10-03 2005-04-28 Seiko Epson Corp 電子デバイスの検査方法
JP2005317867A (ja) * 2004-04-30 2005-11-10 Sony Corp 半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014146780A (ja) * 2013-01-28 2014-08-14 Win Semiconductors Corp 半導体集積回路
EP4227693A4 (fr) * 2020-12-29 2024-03-20 Origin Quantum Computing Tech Hefei Co Ltd Structure de test de puce quantique et procédé de fabrication associé, et procédé de test de puce quantique et procédé de fabrication

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