JP6012688B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP6012688B2 JP6012688B2 JP2014217034A JP2014217034A JP6012688B2 JP 6012688 B2 JP6012688 B2 JP 6012688B2 JP 2014217034 A JP2014217034 A JP 2014217034A JP 2014217034 A JP2014217034 A JP 2014217034A JP 6012688 B2 JP6012688 B2 JP 6012688B2
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Description
まず、本実施の形態における半導体装置の構成について図面を参照して説明する。図2は本実施の形態における半導体装置の平面を示す模式図であり、図3は図2に示す半導体装置の断面の要部を示す模式図であり、図4は図2に示す半導体装置の平面の要部を示す模式図である。また、図4ではその一部を除去した状態で示している。
前記実施の形態では、めっき法によって形成される導電膜(めっき膜)で、再配線を構成した場合について説明したが、本実施の形態では、めっき膜でバンプ電極を構成した場合について説明する。なお、他の内容については前記実施の形態1と同様である。
前記実施の形態1では、再配線の一部上にはんだ印刷技術を用いたバンプ電極を形成した場合について説明したが、本実施の形態では、再配線の一部上にめっき法を用いたパッドを形成する場合について説明する。なお、他の内容については前記実施の形態1と同様である。
前記実施の形態1〜3では、プローブ領域のパッド上では、めっき法によって導電膜(めっき膜)を形成しない場合について説明したが、本実施の形態では、接続領域を拡大してプローブ領域のパッド上にもめっき膜を形成する場合について説明する。なお、他の内容については前記実施の形態1〜3と同様である。
前記実施の形態2では、パッド上にめっき法によって単層の導電膜(めっき膜)を形成した場合について説明したが、本実施の形態では、めっき法を繰り返して多層の導電膜を形成する場合について説明する。なお、他の内容については前記実施の形態2と同様である。
前記実施の形態1では、プロービングされるプローブ領域と、パッドと再配線とが接続される接続領域とを区画して、それぞれの領域を十分確保し、プロービング性の制限を緩和するようにしている。本実施の形態では、プローブ領域と接続領域との区画をより明確とした場合について説明する。なお、他の内容については前記実施の形態1と同様である。
前記実施の形態1では、パッドの平面形状を長方形状とした場合について説明したが、本実施の形態では、凸形状とした場合について説明する。なお、他の内容については前記実施の形態1と同様である。
前記実施の形態1では、パッド上に形成される再配線接続用の開口部において、その平面形状が正方形状の場合について説明したが、本実施の形態では、長方形状の開口部についても説明する。なお、他の内容については前記実施の形態1と同様である。
前記実施の形態2では、パッドの平面領域内に収まるようにバンプ電極を設ける場合について説明したが、本実施の形態では、パッドの平面領域内を越えてバンプ電極を設ける場合について説明する。なお、他の内容については前記実施の形態1と同様である。
前記実施の形態1では、はんだから構成されるバンプ電極をパッドから離れた位置のめっき膜(再配線)の一部上に設けた場合について説明したが、本実施の形態では、パッド上にめっき膜を介してはんだから構成されるバンプ電極を設ける場合について説明する。なお、他の内容については前記実施の形態1と同様である。
本実施の形態では、フリップチップ技術、およびワイヤボンディング技術を用いて半導体チップを積層して小型・高密度のSiP(System in Package)を構成する場合について説明する。
1W 半導体ウエハ
2 パッド(電極)
2A ダミーパッド
3 パッシベーション膜(第1絶縁膜)
4 プローブ針
5 パッシベーション膜(第2絶縁膜)
6 シード膜(配線層、導電膜、めっき層)
7 再配線(配線層、導電膜、めっき膜)
8 パッシベーション膜(第3絶縁膜)
9 バンプ電極
10A プローブ領域(第1領域)
10B 接続領域(第2領域)
11、12、12A、13、14、15 開口部
16 マスク
17 バンプ電極
18 パッシベーション膜
19 シード膜(配線層、導電膜、めっき層)
20 ボール
21、22 開口部
23、24 マスク
25 開口部
26、26a、26b パッド
27 マスク
28 開口部
29 導電膜
30 マスク
31 開口部
32 絶縁基板
33、33a、33b ワイヤ(導電性部材)
34 レジン
35 ボール電極
36 接着材
50 デバイス形成領域
51 スクライブ領域
52 基板
53 電極
54 アンダーフィル樹脂
55 基板
56 電極
57 ワイヤ
100 プローブ痕(外傷)
101 凸部
102 鬆
Claims (7)
- 主面、および前記主面上に形成されたパッドを有する半導体チップと、
前記半導体チップの前記主面上に形成された第1絶縁層と、
前記第1絶縁層上に形成された配線と、
前記配線の一部に設けられ、かつ、前記配線を介して前記パッドと電気的に接続されたバンプ電極と、
を含み、
前記バンプ電極は、平面視において、前記半導体チップの中央部に配置されており、
前記パッドは、平面視において、前記中央部の周囲に位置する前記半導体チップの外周部に配置されており、
前記パッドの表面のうちの第1領域には、プローブ痕が形成されており、
前記第1絶縁層は、開口部を有しており、
前記パッドの前記表面のうちの第2領域は、前記第1絶縁層の開口部から露出しており、
前記第1領域は、平面視において、前記第2領域よりも前記半導体チップの中央部側に位置しており、
前記配線は、前記第1領域ではなく、前記第2領域において、前記パッドと接続され、
前記パッドと前記バンプ電極を互いに、かつ、電気的に接続する前記配線は、前記プローブ痕と重ならないように、前記第2領域から前記半導体チップの前記中央部まで引き出されている、半導体装置。 - 請求項1記載の半導体装置において、
前記パッドの前記表面のうちの前記第1領域は、前記第1絶縁層で覆われている、半導体装置。 - 請求項1記載の半導体装置において、
前記主面上には、第2絶縁層が形成されており、
前記第2絶縁層は、開口部を有しており、
前記パッドの前記表面は、前記第2絶縁層の開口部から露出しており、
前記第1絶縁層は、前記第2絶縁層上に形成されている、半導体装置。 - 請求項1記載の半導体装置において、
前記第1絶縁層上には、第3絶縁層が形成されており、
前記第3絶縁層は、開口部を有しており、
前記配線の前記一部は、前記第3絶縁層の開口部から露出している、半導体装置。 - 請求項4記載の半導体装置において、
前記第3絶縁層の開口部内には、前記バンプ電極が配置されている、半導体装置。 - 請求項1記載の半導体装置において、
前記配線は、シード層を介して前記パッドと接続されている、半導体装置。 - 請求項6記載の半導体装置において、
前記シード層は、前記第1絶縁層上に延在しており、
前記シード層は、前記第1領域ではなく、前記第2領域において、前記パッドと接続されており、
前記配線は、前記シード層を介して前記第1絶縁層上に形成されている、半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2014217034A JP6012688B2 (ja) | 2014-10-24 | 2014-10-24 | 半導体装置 |
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JP2014217034A JP6012688B2 (ja) | 2014-10-24 | 2014-10-24 | 半導体装置 |
Related Parent Applications (1)
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JP2013130933A Division JP2013219385A (ja) | 2013-06-21 | 2013-06-21 | 半導体装置 |
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