TWI429042B - 半導體元件及其製法 - Google Patents

半導體元件及其製法 Download PDF

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Publication number
TWI429042B
TWI429042B TW99123753A TW99123753A TWI429042B TW I429042 B TWI429042 B TW I429042B TW 99123753 A TW99123753 A TW 99123753A TW 99123753 A TW99123753 A TW 99123753A TW I429042 B TWI429042 B TW I429042B
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Taiwan
Prior art keywords
layer
bonding pad
protective layer
stepped
stress buffer
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TW99123753A
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English (en)
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TW201128751A (en
Inventor
Tzu Yu Wang
Tzu Wei Chiu
Shin Puu Jeng
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Taiwan Semiconductor Mfg
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Publication of TW201128751A publication Critical patent/TW201128751A/zh
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Publication of TWI429042B publication Critical patent/TWI429042B/zh

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Description

半導體元件及其製法
本發明係有關於半導體元件及其製法，且特別是有關於一種應力緩衝結構(stress buffer structure)應用於半導體元件之接合結構(mounting structure)及其製法。
近年來，隨著積體電路(integrated circuits,ICs)朝向微小化之趨勢，因此，需要發展高輸入/輸出(high I/O)密度的元件，亦即，需要發展小尺寸的接合墊(bonding pads)。這些接合墊通常形成於晶片的主動表面上，且這些接合墊會定義出晶片的電路電性連接到外部元件所需要的區域。由於各種潛在的(potential)問題(例如短路、結合強度不一致或不適當)，使得接合線(bonding wires)的使用逐漸地不普及。因此，開始引進覆晶技術(flip chip technique)。根據此技術，焊料凸塊(solder bumps)會形成於晶片的接合墊上，且藉由迴焊(reflow)此焊料凸塊，使晶片直接黏著到基材上。最後的產物通常稱為球柵陣列(ball grid array,BGA)或覆晶球柵陣列(flip chip ball grid array,FCBGA)晶片或封裝。
為了增進焊料凸塊與接合墊之間的黏著性，設置一凸塊底層金屬(under bump metallurgy,UBM)結構介於焊料凸塊與接合墊之間。凸塊底層金屬(UBM)結構亦可具有其他功能，例如，作為阻障層(barrier layer)，以避免焊料材料擴散至接合墊或甚至是進入晶片的半導體材料中。一般凸塊底層金屬(UBM)結構包括各自具有不同功能的數層金屬層。
由於凸塊底層金屬(UBM)結構與焊料凸塊的多層材料層集中在每一個接合墊附近，因此，應力亦會集中於這些材料所在的區域。如果沒有預防性的測量，這些應力會逐漸增大，而對直接位於接合墊底下或附近之晶片的層間介電層(inter-level dielectric layers,ILD)造成傷害。對於脆性較高(brittle)，或者於某些應用中多孔性的(porous) low-k介電(低介電常數介電材料)層，應力的影響更大。這些低介電常數介電層容易產生裂縫(cracks)及/或於應力的作用下造成脫層(delaminate)。
本發明提供一種半導體元件，包括：一半導體基材；一接合墊(bonding pad)位於該半導體基材之上；一應力緩衝結構(stress buffer structure)部分地覆蓋該接合墊並暴露一部分之接合墊，其中該應力緩衝結構包括一階梯狀側壁(stepwise wall)，該階梯狀側壁從該暴露之接合墊逐漸地向上延伸；以及一凸塊底層金屬(under-bump metallurgy,UBM)層位於該暴露之接合墊上與該階梯狀側壁之上，其中該凸塊底層金屬之形狀與該階梯狀側壁之形狀一致。
本發明亦提供一種半導體元件，包括：一接合墊；一第一保護層覆蓋該接合墊之周圍部份(peripheral portion)，而暴露該接合墊之中間部分；一階梯狀應力緩衝層，從該第一保護層之上表面向下延伸，沿著該第一保護層之側壁延伸至該接合墊之中間部分；一凸塊底層金屬(under-bump metallurgy,UBM)層位於該接合墊中間之暴露部分、位於階梯狀應力緩衝層之上，其中該凸塊底層金屬(under-bump metallurgy,UBM)層之形狀與該階梯狀應力緩衝層之形狀一致；以及一焊料凸塊位於該凸塊底層金屬(under-bump metallurgy,UBM)層之上。
本發明另提供一種半導體元件之製法，其中該製法包括：形成一接合墊於該半導體元件之主動表面上；形成具有階梯狀側壁之應力緩衝層於該接合墊之周圍部份，而暴露該接合墊之中間部分；形成凸塊底層金屬(under-bump metallurgy,UBM)層位於該接合墊中間之暴露部分，與位於該應力緩衝層之階梯狀側壁上，使得凸塊底層金屬(under-bump metallurgy,UBM)層之形狀與該階梯狀側壁之形狀一致；以及形成一焊料凸塊於該凸塊底層金屬(under-bump metallurgy,UBM)層之上。
本發明又提供一種半導體元件之製法，包括以下步驟：形成一接合墊於該半導體元件之主動表面上；形成至少一保護層於該主動表面或接合墊上，以圍繞該接合墊；形成一應力緩衝層於該至少一保護層與接合墊之上，而暴露該接合墊之中間部分；圖案化至少(i)該應力緩衝層或(ii)該至少一保護層，使其具有階梯狀形狀以定義該應力緩衝層之階梯狀側壁；形成一凸塊底層金屬(under-bump metallurgy,UBM)層於該接合墊之暴露的中間部分，與位於該階梯狀應力緩衝層之上，使得該凸塊底層金屬(under-bump metallurgy,UBM)層之形狀與該階梯狀側壁之形狀一致；以及一焊料凸塊形成於凸塊底層金屬(under-bump metallurgy,UBM)層之上。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
應注意的是，下文所述之一層位於另一層或基材之上，其可以是直接接觸該層或該基材，或者是中間仍存在著別層。
第1圖顯示習知之焊料凸塊結構100之剖面圖。焊料凸塊結構100形成於半導體元件之晶圓或晶片102之主動表面101之上，且包括第一保護層106、接合墊108、第二保護層110、聚亞醯胺層(polyimide,PI)112、凸塊底層金屬(UBM)結構114與焊料凸塊116，並依此順序由下而上形成於晶圓或晶片102之上。晶片102包括位於接合墊108之下，電性連接至接合墊108的最上層金屬層(top-level metal)104。最上層金屬層(top-level metal)104是晶片102中內連線結構的一部分。晶片102之內連線結構尚包括，位於最上層金屬層104之下及/或附近的一或多個介電層(圖中未顯示)，同上所述，這些介電層通常由低介電常數或極低介電常數材料所組成，這些低介電常數材料是脆性高的(brittle)且容易產生裂縫(cracks)或脫層(delamination)。
由於焊料凸塊結構100通常會在凸塊底層金屬(UBM)結構114之下方邊緣與上方邊緣120,122產生高度應力集中。應力大小係取決於凸塊底層金屬(UBM)結構114之側壁1149的傾斜角度。特別當側壁1149處於(例如，相對於主動表面101為40°)銳角(acute)角度時，應力大部分會集中於下方邊緣120。當側壁1149之傾斜角度增加至90°時，應力會集中偏移至上方邊緣122。然而，不論處於任何斜角，高應力仍會傳送至位於邊緣120,122底下之內連線結構的介電層中，因此，提高介電層產生裂縫(cracks)或脫層(delamination)的可能性。
第2A圖顯示第1圖焊料凸塊結構100之簡化圖或部分圖。第2B-2C圖類似於第2A圖，顯示本發明之各種焊料凸塊結構240,250之實施例。
第2B圖中的焊料凸塊結構形成於半導體元件之半導體晶圓或晶片(圖中未顯示)之主動表面201上。焊料凸塊結構240包括接合墊208、應力緩衝結構212、凸塊底層金屬(UBM)結構214與焊料凸塊216(部分顯示)，並依此順序由下而上依序形成。於接合墊208之下，晶片包括由多層導電與介電層依序疊加形成之內連線結構。為了簡化說明，只有內連線結構之最上層導電層顯示於圖中，例如最上層金屬層204。內連線結構尚包括，位於最上層金屬層204之下及/或附近的一或多個介電層(圖中未顯示)，於一些實施例中，該些介電層通常由低介電常數(low-k)或極低介電常數(extreme low-k)材料所組成。當晶片被反轉(flipped over)與設置於載板(例如基材或導線架(lead frame)(圖中未顯示))之上，與焊料凸塊216被迴焊(reflow)時，焊料凸塊結構240用以定義出晶片之黏著結構(mounting structure)。於一些實施例中，因為提供多個焊料凸塊結構240，所以晶片包括多個接合墊208。
應力緩衝結構(stress buffer structure)212與第1圖與第2A圖中之焊料凸塊結構100的聚亞醯胺(PI)層112不同。特別的是，亞醯胺(PI)層112具有一側壁1125，此側壁1125係角度一致地(monotonously)從接合墊108開始延伸向上，亦即，從接合墊108開始以一固定的斜率向上延伸。如此一來，形成於亞醯胺(PI)層112上之凸塊底層金屬(UBM)結構114與亞醯胺(PI)層112之形狀一致，且亦具有角度一致地(monotonously)延伸之側壁1149。此種焊料凸塊結構100，同上所述，容易造成底下各層(例如，晶片之低介電常數(low-k)介電層或超低介電常數(extremely low-k)介電層)的應力集中。
相反地，於第2B圖中的應力緩衝結構(stress buffer structure)212並不具有角度一致地(monotonously)延伸之側壁1149。取而代之的是應力緩衝結構212從接合墊208開始以階梯狀(stepwise manner)向上延伸。高於接合墊208之上的側壁2125至少包括兩個階梯，分別命名為下層階梯2121與上層階梯2122，其各自具有高度b與a，如第2B圖中所示。既然應力緩衝結構212之側壁2125是階梯狀，則形成於應力緩衝結構212之上且順應其形狀之凸塊底層金屬(UBM)結構214亦具有階梯狀側壁2149。下文會加以詳述，凸塊底層金屬(UBM)結構214與應力緩衝結構212之階梯狀構造，會造成底下各層(例如低介電常數(low-k)介電層或超低介電常數(extremely low-k)介電層)之應力分佈較為均勻。比起焊料凸塊結構100，此階梯狀構造尚可降低應力的最大及/或平均值。
於第2C圖中的焊料凸塊結構250類似於焊料凸塊結構240，差別只在介於階梯之間(例如下層階梯2121與上層階梯2122)的高度不同。第2B圖中的高度比例為約1：1，亦即，下層階梯2121之高度與上層階梯2122之高度大約相同。於第2C圖中的高度比例為約2：1，亦即上層階梯2122之高度為下層階梯2121之高度的兩倍。
假設焊料凸塊結構100,240與250之所有特性皆相同(亦即，材料或厚度等)，差別只在亞醯胺(PI)層112/應力緩衝結構212與對應的凸塊底層金屬(UBM)結構之特定形狀與特定高度不同(請參見第2B-2C圖)，應力產生之電腦模擬(computer simulation)結果顯示於第3A-3B圖中。
第3A圖中顯示底下各層之低介電常數(low-k)材料或超低介電常數(extremely low-k,ELK)材料之應力分佈圖，例如位於焊料凸塊結構100,240與250中最上層金屬層104,204底下的各層。在第2A圖中的焊料凸塊結構100的應力分佈最不平均(uneven)，其位於下方邊緣120(第1圖中)的位置具有非常高的訊號峰值(最大應力值)。第2B圖中的焊料凸塊結構240的應力分佈比第2A圖的焊料凸塊結構100均勻，其具有較低的訊號峰值。第2C圖中的焊料凸塊結構250的應力分佈比第2B圖的焊料凸塊結構240更為均勻，其具有最低的訊號峰。如此一來，最大的應力值依序從焊料凸塊結構100、焊料凸塊結構240下降至焊料凸塊結構250。因此，比起焊料凸塊結構100，應力集中的問題在焊料凸塊結構240、焊料凸塊結構250中較不嚴重。
此外，平均應力值亦可改善。第3B圖中顯示底下各層之低介電常數(low-k)材料或超低介電常數(extremely low-k,ELK)材料之平均應力分佈圖，例如於最上層金屬層104、204底下的各層，與位於凸塊底層金屬(UBM)結構(例如凸塊底層金屬結構114、214)之上的各層。由第3B圖中可得知，橫越凸塊底層金屬(UBM)結構之寬度，且位於底下之介電層與凸塊底層金屬(UBM)結構兩者之平均應力值係依序從焊料凸塊結構100、焊料凸塊結構240下降至焊料凸塊結構250。因此，位於底下之介電層材料，其平均應力值下降超過25%(從63.4下降至47.1)；凸塊底層金屬(UBM)結構中之平均應力值下降超過20%(從183.3下降至147.1)。
因此，凸塊底層金屬(UBM)結構與應力緩衝結構之階梯狀構造會造成較均勻的應力分佈，且降低晶片底下介電材料與凸塊底層金屬(UBM)結構自身的最大/平均應力值。於各種未顯示之實施例中，藉由改變階梯之數目(例如，形成大於兩個以上的階梯)及/或高度及/或於各個階梯構造之高度比，於凸塊底層金屬(UBM)結構中的應力值與分佈可以像晶片底下介電材料一樣，皆被最佳化成所需之數值。進行應力最佳化的調整時，可以單一條件各自調整或多個條件一起調整，例如調整應力緩衝結構之厚度(於某些實施例中亦稱為聚亞醯胺(PI)層厚度)、及/或於應力緩衝結構中開口之尺寸(於某些實施例中亦稱為”PI層開口”)、及/或開口之側壁的斜角。
應力緩衝結構212包括一或多層材料層。簡而言之，於第2B-2C圖中僅顯示一層應力緩衝層。這些應力緩衝層是由應力緩衝材料所組成，且由應力緩衝結構212定義出階梯狀側壁2125，因此，亦對應地定義出凸塊底層金屬(UBM)結構214之階梯狀側壁2149。於某些實施例中，應力緩衝材料為高分子，其中高分子包括聚醯亞胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、以環氧樹脂為主的高分子、酚(phenol)為主的高分子或苯並環丁烯(benzocyclobutene,BCB)。
於一些實施例中，提供類似於焊料凸塊結構100之第二保護層110之保護層(並未顯示於圖中)，此保護層位於應力緩衝結構212之下，用以調整應力緩衝結構212之高度，因此不需要大量的應力緩衝層材料。於其他實施例中，由一或多種應力緩衝材料形成之多層結構係由下而上依序形成，用以組成應力緩衝結構212，這些材料可組成應力緩衝結構212或與保護層一起組成應力緩衝結構212。
依據本發明之實施例，第4A-4H圖顯示半導體元件400(第4H圖)製作接合結構之各個製程階段的剖面圖。
於第4A圖中，提供一半導體基材402。於一些實施例中，半導體基材402為晶圓。於其他實施例中，半導體基材402為具有內部電路與主動表面401之晶片。半導體基材402包括最上層導電層，例如最上層金屬層404。半導體基材402尚包括位於最上層金屬層104之下及/或附近的一或多個介電層(圖中未顯示)，於某些實施例中，該些介電層由脆性高的(brittle)且容易產生裂縫(cracks)或脫層(delamination)之低介電常數或極低介電常數材料所組成。
第一保護層406形成於主動表面401上，以部分覆蓋最上層金屬層404。未被第一保護層406覆蓋之一部分最上層金屬層404是暴露的，在此亦稱為第一保護層開口。於一些實施例中，保護層406包括氧化層或氮化層，例如氧化矽或氮化矽。於其他實施例中，第一保護層包括聚亞醯胺(polyimide)。第一保護層406之形成方法包括沉積(例如藉由化學氣相沉積法(chemical vapor deposition,CVD))保護材料於主動表面401上，接著蝕刻一部分的保護材料以形成第一保護層開口。
導電材料接著沉積到第一保護層開口中，與位於第一保護層406上表面之上並圍繞第一保護層開口，以形成接合墊408。於一些實施例中，接合墊408侷限於(confined within)第一保護層開口中，不設置於第一保護層406上表面之上。接合墊408之導電材料包括鋁或銅，且其沉積後用以電性連接半導體基材或晶片402之內部電路。
如第4A圖所示，保護材料層4101沉積於接合墊408與第一保護層406之上。於此特別實施例中，保護材料層4101之上表面之形狀與底下接合墊408之形狀相同。於其他實施例中，於後續製程步驟之前，對保護材料層4101之上表面進行平坦化。保護材料層4101之材料與第一保護層406之材料相同或類似。
請參見第4B圖，具有一開口D1之罩幕411用於部分地移除保護材料層4101之暴露部分。舉例而言，罩幕411包括沉積一光阻，接著，對位於保護材料層4101上表面之上的光阻進行光微影圖案化(photo-lithographically patterned)製程。之後，移除暴露之保護材料層4101(例如，藉由第一蝕刻製程)。
第4C圖顯示進行第一蝕刻製程之後且罩幕411被移除之後的剖面圖。特別的是，第二保護層開口4159形成於保護材料層4101之中。曾經被圖案化之保護材料層4101在此處將被稱為保護材料層4102。於一些實施例中，請參見第4C圖，對保護材料層4101之蝕刻停止於接合墊408暴露之前。如此一來，可得到如下所述之至少三階之階梯狀結構。於其他實施例中，對保護材料層4101之蝕刻停止於直到接合墊408暴露為止。如此一來，可得到如下所述之至少兩階之階梯狀結構。
請參見第4D圖，另一罩幕413具有大於開口D1之開口D2，此開口D2用於(例如，藉由第二蝕刻製程)移除保護材料層4102之暴露部分。舉例而言，罩幕413之形成類似於罩幕411。
第4E圖顯示進行第二蝕刻製程之後且罩幕413被移除之後的剖面圖。特別的是，第二保護層開口4159被放大且標示為4160。經過兩次圖案化之保護材料層4101已經變成第二保護層410。如第4E圖所示，第二保護層410具有階梯狀之側壁4107。對保護材料層4102之蝕刻停止於直到接合墊408暴露為止。
請參見第4F圖，藉由例如旋轉塗佈法沉積應力緩衝材料層4121於第二保護層410之上，與沉積於第二保護層開口4160之中與接合墊408之暴露部分上。應力緩衝材料層4121之側壁4125具有兩層上層階梯，其中上層階梯之形狀同於第二保護層410之階梯狀側壁4107。應力緩衝材料層4121之側壁4125尚包括一較下層階梯，其中下層階梯之形狀同於接合墊408之凸起部分4083。
請參見第4G圖，移除位於第二保護層開口4160底部之部分應力緩衝材料層4121以暴露一部分之接合墊408，利用例如已知之圖案化方法，包括微影製程與蝕刻製程。因此，圖案化後之應力緩衝材料層4121現在變成具有三層階梯狀結構之應力緩衝結構412。
請參見第4H圖，凸塊底層金屬(UBM)結構414沉積於應力緩衝結構412之上，其順應應力緩衝結構412之形狀而形成且電性接觸接合墊408暴露的部分。凸塊底層金屬(UBM)結構414包括一或多層金屬，其中金屬包括鉻(Cr)、鈦(Ti)、鎳(Ni)、鎢(W)、鉑(Pt)、銅(Cu)、鈀(Pd)、金(Au)、銀(Ag)或上述之合金。凸塊底層金屬(UBM)結構414之形成依序藉由(例如化學氣相沉積法(CVD)、電鍍或濺鍍)沉積成分層(亦即金屬層)於接合墊408之上，接著進行蝕刻製程(例如乾式蝕刻或濕式蝕刻)移除不想要的部分。焊料凸塊416形成於凸塊底層金屬(UBM)結構414之上，以完成半導體元件400。
依據本發明之實施例，第5A-5D圖顯示半導體元件500(第5D圖)製作接合結構之各個製程階段的剖面圖。
於第5A圖中，提供類似於半導體基材402之半導體基材502。半導體基材502包括最上層導電層，例如類似於最上層金屬層404之最上層金屬層504。第一保護層506、接合墊508與保護材料層5101類似於第一保護層406、接合墊408與保護材料層4101，各自地形成於半導體基材502之上，且形成之方法類似於第4A圖所述之方法。
第5A圖與第4A圖之差別在於，第一保護層506被圖案化大於一次(例如兩次)，而於第4A圖中，第一保護層406只被圖案化一次。結果造成於第一保護層506中之第一保護層開口具有如第5A圖所示之階梯狀側壁。形成階梯狀第一保護層開口之製程步驟類似於第4A-4E圖所示之方法(例如藉由具有不同尺寸罩幕進行兩次蝕刻製程)。然而，亦可以使用其他方法。
第5A圖與第4A圖另一點差別在於，形成於第一保護層506之上的接合墊508之形狀與第一保護層506之形狀相同，同樣具有階梯狀形狀。特別的是，接合墊508具有下層階梯5081與上層階梯5082各自對應到第一保護層506之下層階梯5061與上層階梯5062。於一些實施例中(圖中未顯示)，接合墊508被侷限於(confined within)第一保護層506之上層階梯5062所定義的邊界(boundary)中，因此其具有類似於第4A圖之形狀。
請參見第5B圖，類似於罩幕411之罩幕511具有開口D3用於移除保護材料層5101之暴露部分，移除之方法類似於第4B圖所述之方法。
第5C圖顯示進行第5B圖之蝕刻製程之後且罩幕511被移除之後的剖面圖。特別的是，第二保護層開口5159形成於曾經被圖案化之保護材料層5101中(在此處將被稱為保護材料層510)。對保護材料層5101之蝕刻停止於接合墊508暴露之前或之後。接合墊508之上層階梯5082之上表面被埋入第二保護層510中，且因此形成如下所述至少有兩層階梯之形狀。
請參見第5D圖，沉積應力緩衝材料層並圖案化之，以定義應力緩衝結構512，形成之方法類似於第4F-4G圖所述之方法。應力緩衝結構512之側壁5125具有對應到第二保護層510上表面之上層階梯5127與具有對應到接合墊508下層階梯5081之下層階梯5128。
凸塊底層金屬(UBM)結構514沉積於應力緩衝結構512之上，其順應應力緩衝結構512之形狀而形成且電性接觸接合墊508暴露的中間部分，此形成方法類似於第4H圖所述之方法。焊料凸塊(未顯示於第5D圖中)形成於凸塊底層金屬(UBM)結構514之上，以完成半導體元件500。
依據本發明之實施例，第6A-6B圖顯示半導體元件600(第6B圖)製作接合結構之各個製程階段的剖面圖。
第6A圖延續第5C圖之步驟，其中罩幕613具有大於開口D3之開口D4，此開口D4用於蝕刻第二保護層510，以獲得應力緩衝結構612(第6B圖)。因此，於第5C圖中的第二保護層開口5159變寬，因此造成接合墊508之上層階梯5082之上表面暴露，且定義出如第6B圖所示之最終階梯形狀。
特別的是，於第6B圖中，應力緩衝材料層612之側壁6125具有對應於第二保護層610上表面之上層階梯6127、對應於接合墊508下層階梯5081的下層階梯6128與對應於接合墊508上層階梯5082上表面之中間階梯6129。
凸塊底層金屬(UBM)結構614沉積於應力緩衝結構612之上，其順應應力緩衝結構612之形狀而形成且電性接觸接合墊508暴露的中間部分，此形成方法類似於本發明上述揭露之方法。焊料凸塊(未顯示於第6B圖中)形成於凸塊底層金屬(UBM)結構614之上，以完成半導體元件600。
於一些實施例中，罩幕613可以被取代罩幕511(而非結合兩者)，以蝕刻如第5B圖所示之保護材料層5101，以獲得類似於半導體元件600之半導體元件。
依據本發明之實施例，第7A-7C圖顯示半導體元件700(第7C圖)製作接合結構之各個製程階段的剖面圖。
第7A圖顯示半導體元件經過第4A-4C圖與4F-4H圖製程步驟之後的狀態。特別的是，於第7A圖中的半導體基材702類似於半導體基材402。半導體基材702包括最上層導電層，例如類似於最上層金屬層402之最上層金屬層704。第一保護層706、接合墊708與保護材料層(圖中未顯示)類似於第一保護層406、接合墊408與保護材料層4101，各自地形成於半導體基材702之上，且形成之方法類似於第4A圖所述之方法。
利用類似於第4B圖所述之罩幕(mask)圖案化保護材料層。
保護材料層之圖案化步驟會進行到直到接合墊708的中間部分暴露為止，並不像第4C圖之製程。因此，會得到第二保護層710。
如第4F圖所述，應力緩衝材料層(圖中未顯示)沉積於圖案化第二保護層710之上。且如第4G圖所述，對應力緩衝材料層進行圖案化，以獲得如第7A圖所示之圖案化應力緩衝材料層7121。
類似於罩幕411之罩幕711具有一開口(並未標示)寬於形成於第二保護層710中的第二保護層開口7159，罩幕711之作用在於，移除圍繞於第二保護層開口7159之圖案化應力緩衝材料層7121的暴露部分，以獲得如第7B圖所示之應力緩衝結構712。
第7B圖顯示進行第7A圖之蝕刻製程之後且罩幕711被移除之後的剖面圖。特別的是，移除部份的圖案化應力緩衝材料層7121會得到具有階梯狀側壁7125之應力緩衝結構712。值得一提的是，應力緩衝材料層712之側壁7125具有對應到圖案化應力緩衝材料層7121上表面之上層階梯7127(於第二次蝕刻製程之前)，與對應到圍繞第二保護層開口7159之應力緩衝材料層7121上表面之下層階梯7128(於第二次蝕刻製程之後)。因此，可獲得兩層階梯之形狀。
請參見第7C圖，凸塊底層金屬(UBM)結構714沉積於應力緩衝結構712之上，其順應應力緩衝結構712之形狀而形成且電性接觸接合墊708暴露的中間部分，此形成方法類似於第4H圖所述之方法。焊料凸塊(未顯示於第7C圖中)形成於凸塊底層金屬(UBM)結構714之上，以完成半導體元件700。
依據本發明之實施例，第8A-8C圖顯示半導體元件800(第8C圖)製作接合結構之各個製程階段的剖面圖第8A圖類似於第7A圖，差別在於不需要使用罩幕711。因此，於第8A圖中的半導體基材802類似於半導體基材702。半導體基材802包括最上層導電層，例如類似於最上層金屬層704之最上層金屬層804。第一保護層806、接合墊808與第二保護材料層810與圖案化應力緩衝材料層8121類似於第一保護層706、接合墊708與第二保護層710與圖案化應力緩衝材料層7121，各自地形成於半導體基材802之上，且形成之方法同前所述。此外，亦形成類似於第二保護層開口7159之第二保護層開口8159。
不同於第7A圖中立即使用罩幕對第8A圖之結構進行蝕刻，取而代之的是於第8B圖，填充第二應力緩衝材料層8122到第二保護層開口8159中，且沉積一所需厚度到圖案化應力緩衝材料層8121之上。於一些實施例中，使用旋轉塗佈製程(spin-coating process)形成第二應力緩衝材料層8122。使用具有所需開口(圖中未顯示)之罩幕811，此罩幕811用於蝕刻形成於第二保護層開口8159中的第二應力緩衝材料層8122之暴露部分，以及蝕刻位於圖案化應力緩衝材料層8121之上的部分。提高對應力緩衝材料層8121與第二應力緩衝材料層8122之蝕刻選擇性(etch selectivity)，使得第二應力緩衝材料層8122之暴露部分被移除，且不會嚴重影響到形成於罩幕811開口中的圖案化應力緩衝材料層8121之厚度。
第8C圖顯示進行第8B圖之蝕刻製程之後且罩幕811被移除之後的剖面圖。之後，會得到具有階梯狀側壁8125且結合第二應力緩衝材料層8122與圖案化應力緩衝材料層8121之應力緩衝結構812。應力緩衝材料層812之側壁8125具有對應到第二應力緩衝材料層8122上表面之上層階梯8127，與對應到圖案化應力緩衝材料層8121上表面之下層階梯8128(於第二次蝕刻製程之後)。因此，可獲得兩層階梯之形狀。可藉由調整第二應力緩衝材料層8122於第二保護層開口8159中之深度(第8A圖)決定階梯形狀中各層階梯的高度比(height ratio)。
凸塊底層金屬(UBM)結構814沉積於應力緩衝結構812之上，其順應應力緩衝結構812之形狀而形成且電性接觸接合墊808暴露的中間部分，此形成方法類似於第4H圖所述之方法。焊料凸塊(未顯示於第8C圖中)形成於凸塊底層金屬(UBM)結構814之上，以完成半導體元件800。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100．．．焊料凸塊結構
101．．．主動表面
102．．．晶圓或晶片
104．．．最上層金屬層
106．．．第一保護層
108．．．接合墊
110．．．第二保護層
112．．．聚亞醯胺層(PI)
114．．．凸塊底層金屬(UBM)結構
116．．．焊料凸塊
120．．．凸塊底層金屬(UBM)結構114之下方邊緣
122．．．凸塊底層金屬(UBM)結構114之上方邊緣
201．．．主動表面
204．．．最上層金屬層
208．．．接合墊
212．．．應力緩衝結構
214．．．凸塊底層金屬(UBM)結構
216、240、250．．．焊料凸塊
400、500、600、700、800．．．半導體元件
401．．．主動表面
402、502、702、802．．．半導體基材
404、504、704、804．．．最上層金屬層
406、506、706、806．．．第一保護層
408、508、708、808．．．接合墊
410、510、710、810．．．第二保護層
411、511、711、811．．．罩幕
412、512、612、712、812．．．應力緩衝結構
413、613．．．罩幕
414、514、614、714、814．．．凸塊底層金屬(UBM)結構
416．．．焊料凸塊
1125．．．側壁
1149、2149．．．側壁
b．．．下層階梯之高度
a．．．上層階梯之高度
2125、4125、5125、6125、7125、8125．．．側壁
4083．．．接合墊之凸起部分
4101、4102、5101．．．保護材料層
4107．．．階梯狀之側壁
4121、7121、8121．．．應力緩衝材料層
8122．．．第二應力緩衝材料層
4159、5159、7159、8159．．．第二保護層開口
4160．．．放大後之第二保護層開口
2121、5061、5081、5128、6128、7128、8128．．．下層階梯
2122、5062、5082、5127、6127、7127、8127．．．上層階梯
6129．．．中間階梯
D1、D2、D3、D4．．．開口
第1圖為一剖面圖，用以說明習知之半導體元件之焊料凸塊結構。
第2A~2C圖為一系列剖面圖，用以說明本發明一較佳實施例的流程。
第3A~3B圖為一系列圖式，用以說明第2A-2C圖之接合結構的應力分佈與應力值。
第4A~4H圖為一系列剖面圖，用以說明本發明另一較佳實施例的流程。
第5A~5D圖為一系列剖面圖，用以說明本發明又一較佳實施例的流程。
第6A~6B圖為一系列剖面圖，用以說明本發明一較佳實施例的流程。
第7A~7C圖為一系列剖面圖，用以說明本發明另一較佳實施例的流程。
第8A~8C圖為一系列剖面圖，用以說明本發明又一較佳實施例的流程。
400．．．半導體元件
402．．．半導體基材
404．．．最上層金屬層
406．．．第一保護層
408．．．接合墊
410．．．第二保護層
412．．．應力緩衝結構
414．．．凸塊底層金屬(UBM)結構
416．．．焊料凸塊

Claims (10)

  1. 一種半導體元件，包括：一半導體基材；一接合墊(bonding pad)位於該半導體基材之上；一應力緩衝結構(stress buffer structure)部分地覆蓋該接合墊並暴露一部分之接合墊，其中該應力緩衝結構包括一階梯狀側壁(stepwise wall)，該階梯狀側壁從該暴露之接合墊逐漸地向上延伸；以及一凸塊底層金屬(under-bump metallurgy,UBM)層位於該暴露之接合墊上與該階梯狀側壁之上，其中該凸塊底層金屬之形狀與該階梯狀側壁之形狀一致；其中該階梯狀側壁包含一上層階梯與一下層階梯，且該上層階梯之高度大於或等於該下層階梯之高度。
  2. 如申請專利範圍第1項所述之半導體元件，其中該應力緩衝結構(stress buffer structure)包括：一保護層；以及一應力緩衝高分子層(stress buffer polymer layer)位於該保護層之上，且定義(defining)出整個該階梯狀側壁，其中該應力緩衝高分子層包括聚醯亞胺(polyimide)、聚苯噁唑(polybenzoxazole,PBO)、以環氧樹脂為主的高分子、酚(phenol)為主的高分子或苯並環丁烯(benzocyclobutene,BCB)。
  3. 如申請專利範圍第1項所述之半導體元件，其中該應力緩衝結構(stress buffer structure)包括：一保護層，其中該保護層包括一第一階梯狀側壁； 以及一應力緩衝高分子層位於該保護層之上，且包括與該階梯狀側壁之形狀一致的一第二階梯狀側壁。
  4. 如申請專利範圍第3項所述之半導體元件，其中該接合墊包括一第三階梯狀側壁，且該第一與第二階梯狀側壁之形狀與該第三階梯狀側壁之形狀一致。
  5. 如申請專利範圍第1項所述之半導體元件，其中該上層階梯之高度大體上等於該下層階梯之高度。
  6. 如申請專利範圍第1項所述之半導體元件，其中該上層階梯之高度大於該下層階梯之高度。
  7. 一種半導體元件之製法，其中該製法包括：形成一接合墊於該半導體元件之主動表面上；形成具有階梯狀側壁之應力緩衝層於該接合墊之周圍部份，而暴露該接合墊之中間部分；形成凸塊底層金屬(under-bump metallurgy,UBM)層位於該接合墊中間之暴露部分，與位於該應力緩衝層之階梯狀側壁上，使得凸塊底層金屬(under-bump metallurgy,UBM)層之形狀與該階梯狀側壁之形狀一致；以及形成一焊料凸塊於該凸塊底層金屬(under-bump metallurgy,UBM)層之上；其中該階梯狀側壁包含一上層階梯與一下層階梯，且該上層階梯之高度大於或等於該下層階梯之高度。
  8. 如申請專利範圍第7項所述之半導體元件之製法，於形成該應力緩衝層之前，尚包括： 形成一上層保護層於該主動表面上與該接合墊上；以及當應力緩衝層形成於該上層保護層之上時，圖案化該上層保護層，使該上層保護層具有一階梯狀形狀，其中該階梯狀形狀至少部分地定義出該應力緩衝層之階梯狀側壁。
  9. 如申請專利範圍第7項所述之半導體元件之製法，尚包括：當應力緩衝層形成於該接合墊之上時，圖案化該接合墊，使得該接合墊具有一階梯狀形狀，其中該階梯狀形狀至少部分地定義出該應力緩衝層之階梯狀側壁。
  10. 如申請專利範圍第7項所述之半導體元件之製法，於形成該接合墊之前，尚包括：形成一下層保護層於該主動表面上；以及當接合墊形成於該下層保護層之上時，圖案化該下層保護層，使該下層保護層具有一階梯狀形狀，其中該階梯狀形狀定義出對應於該接合墊之一階梯形狀；當應力緩衝層形成於該接合墊之上時，其中接合墊之階梯狀形狀至少部分地定義出該應力緩衝層之階梯狀側壁。
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