CN109273433B - 封装结构及其制造方法 - Google Patents
封装结构及其制造方法 Download PDFInfo
- Publication number
- CN109273433B CN109273433B CN201710771489.6A CN201710771489A CN109273433B CN 109273433 B CN109273433 B CN 109273433B CN 201710771489 A CN201710771489 A CN 201710771489A CN 109273433 B CN109273433 B CN 109273433B
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- interlayer
- molding compound
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- die
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Abstract
本发明实施例是有关于一种封装结构及其制造方法。一种封装结构包括至少一个管芯、天线元件以及至少一个层间穿孔。所述天线元件位于所述至少一个管芯上。所述至少一个层间穿孔位于所述天线元件与所述至少一个管芯之间,其中所述天线元件经由所述至少一个层间穿孔电连接到所述至少一个管芯。
Description
技术领域
本发明实施例是有关于一种封装结构及其制造方法。
背景技术
通常可以在整片半导体晶片上制造半导体装置和集成电路。在晶片层级工艺中,针对晶片中的管芯进行加工处理,并且可以将管芯与其他的半导体元件(例如,天线)一起封装。目前各方正努力开发适用于晶片级封装的不同技术。
发明内容
本发明实施例提供一种封装结构包括至少一个管芯、天线元件以及至少一个层间穿孔。所述天线元件位于所述至少一个管芯上。所述至少一个层间穿孔位于所述天线元件与所述至少一个管芯之间,其中所述天线元件经由所述至少一个层间穿孔电连接到所述至少一个管芯。
附图说明
结合附图阅读以下详细说明,会最好地理解本发明实施例的各个方面。应注意,根据本行业中的标准惯例,各种特征并非按比例绘制。事实上,为论述清晰起见,可任意增大或减小各种特征的尺寸。
图1A至图1H是根据一些本发明实施例的封装结构的制造方法中的各阶段的示意性剖视图。
图2A至图2N是根据一些本发明实施例的封装结构的制造方法中的各阶段的示意性剖视图。
图3是说明图2B所绘示层间穿孔壁与第二重布线层之间的相对位置的示意性俯视图。
图4是说明图2M所绘示层间穿孔壁与第二金属图案之间的相对位置的示意性俯视图。
图5是说明根据一些本发明实施例的层间穿孔壁与第二金属图案之间的相对位置的示意性俯视图。
图6是说明根据一些本发明实施例的接地平面部分的示意性俯视图。
[符号的说明]
10、20:封装结构;
112、212:载体;
114、214:剥离层;
116:介电层;
120:层间穿孔;
130、230、230a、230b:模制化合物;
140:第一重布线层;
142、242:聚合物介电层;
144、244:金属层;
150:球下金属(UBM)图案;
152:连接垫;
160:导电元件;
170:管芯;
170a:有源表面;
170b:垫;
170c:钝化层;
170d:导电柱;
170e:保护层;
180:顶盖层;
180a:顶盖层的表面/第一侧;
180b:顶盖层的表面/第二侧;
181:粘合剂层;
182:第一金属图案;
184:第二金属图案;
220:层间穿孔壁;
220a:层间穿孔壁的内侧壁;
240:第二重布线层;
242a:开口;
244a:金属层的表面;
AC:空气腔;
ATN:天线元件;
DA:管芯贴合膜;
GP:接地平面部分;
OP、Opc:预定重叠区域;
Orp:开口;
PF:聚合物膜;
S:空间;
X:第二方向;
Y:第一方向。
具体实施方式
以下公开内容提供用于实作所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件、值、操作、材料、排列等的具体实例以简化本公开内容。当然,这些仅为实例且不旨在进行限制。预期存在其他组件、值、操作、材料、排列等。例如,以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例,且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外,本公开内容可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的,而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外,为易于说明,本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向)且本文中所用的空间相对性描述语可同样相应地进行解释。
另外,为易于说明,本文中可能使用例如“第一(first)”、“第二(second)”、“第三(third)”等用语来阐述与图中所示者相似或不同的一个或多个元件或特征,且可根据呈现次序或本说明的上下文来可互换地使用所述用语。
还可包括其他特征及工艺。举例来说,可包括测试结构以帮助进行三维(3D)封装或三维集成电路(3DIC)装置的验证测试。测试结构可包括例如形成于重布线层中或衬底上的测试垫,所述测试垫使得能够测试3D封装或3DIC、使用探针(probe)及/或探针卡(probecard)等。可对中间结构及最终结构执行验证测试。另外,本文中所公开的结构及方法可结合包含对已知良好管芯的中间验证的测试方法一起使用,以提高产量(yield)及降低成本。
图1A至图1H是根据一些本发明实施例的封装结构的制造方法中的各阶段的示意性剖视图。图6是说明在根据一些本发明实施例的封装结构中,重布线层的接地平面部分的示意性俯视图。在示例性实施例中,所述制造方法是晶片级封装工艺的一部分。举例来说,在图1A至图1H中,示出一个管芯来表示晶片的多个管芯,且示出封装结构10来表示通过所述制造方法所获得的封装结构。在其他实施例中,示出两个芯片或管芯来表示晶片的多个芯片或管芯,且示出一个或多个封装结构来表示通过所述(半导体)制造方法所获得的多个(半导体)封装结构,本发明实施例并不仅限于此。
参照图1A,在一些实施例中,提供载体112,且载体112可以是玻璃载体或任意适于所述封装结构的制造方法的载体。在一些实施例中,载体112涂布有剥离层114。剥离层114的材料可以是能够使载体112与位于其上的各层轻易脱离的任意材料。接下来,通过在载体112之上形成介电材料层(图中未示出)在载体112上形成介电层116。介电层116可通过例如旋转涂布、叠层、沉积等适当的制作技术来形成。在一些实施例中,介电层116是聚合物层;所述聚合物层可包含聚酰亚胺、聚苯并恶唑(PBO)、苯并环丁烯(BCB)、味之素增层膜(Ajinomoto Buildup Film,ABF)、阻焊膜(Solder Resist film,SR)等。
如图1A所示,在载体112上形成天线元件ATN。在一些实施例中,天线元件ATN可通过以下方式形成:在载体112之上形成金属化材料层(图中未示出),并图案化所述金属化材料层以形成经图案化的金属性层(称为天线元件ATN)。在一些实施例中,天线元件ATN的材料可包括铝、钛、铜、镍、钨、及/或其合金,天线元件ATN可通过例如沉积或电镀等适当的制作技术形成,且可通过例如光刻及蚀刻等适当的图案化工艺进行图案化。
参照图1B,在一些实施例中,在载体112上形成至少一个层间穿孔(throughinterlayer via,TIV)120,且层间穿孔120与天线元件ATN接触且电连接。此处仅示出了一个层间穿孔,但层间穿孔的数目不受本文中所作说明的限制。在一些实施例中,层间穿孔120是贯穿集成扇出型穿孔(through integrated fan-out via,InFO via)。在某些实施例中,层间穿孔120物理地接触天线元件ATN并排列成靠近天线元件ATN的边缘。在一些实施例中,层间穿孔120是通过光刻工艺、镀覆工艺、光刻胶剥除工艺、或任意其他适当的方法来形成。在一个实施例中,层间穿孔120可通过以下方式形成:形成具有开口的掩模图案(图中未示出),所述开口暴露出天线元件ATN的一部分,并通过电镀或沉积形成填充所述开口的金属材料,以在天线元件ATN的被暴露出的部分上形成层间穿孔120,且然后移除掩模图案。然而,本发明实施例并不仅限于此。在一个实施例中,层间穿孔120的材料可包括金属材料,例如铜或铜合金等。如图1B所示,仅示出了一个层间穿孔120;然而,本发明实施例并不仅限于此。在另一实施例中,可基于需求选择层间穿孔的数目。
参照图1C,在一些实施例中,使天线元件ATN及层间穿孔120与模制化合物130接触并模制天线元件ATN及层间穿孔120在模制化合物130中。在一些实施例中,模制化合物130覆盖层间穿孔120、天线元件ATN、以及介电层116。在一些实施例中,模制化合物130覆盖层间穿孔120的顶表面及侧壁以及天线元件ATN的顶表面及侧壁,其中层间穿孔120的顶表面及天线元件ATN的顶表面与载体112相对。在一些实施例中,模制化合物130的材料具有低介电常数(low permittivity(Dk))性质以及低损耗正切(low loss tangent(Df))性质。根据高速应用(high speed applications)的频率范围,可基于封装结构的所需电性性质来选择模制化合物130的适当材料。
参照图1D,在一些实施例中,对模制化合物130及层间穿孔120进行平坦化,直到暴露出层间穿孔120。在某些实施例中,如图1D所示,在平坦化之后,层间穿孔120与模制化合物130变得实质上齐平。在一个实施例中,层间穿孔120的顶表面与模制化合物130的顶表面共面。在一些实施例中,通过研磨工艺(grinding process)或化学机械抛光(chemicalmechanical polishing,CMP)工艺对模制化合物130及层间穿孔120进行平坦化。在研磨工艺之后,可视情况执行清洁步骤,例如以清洁并移除从研磨步骤产生的残余物。然而,本发明实施例并不仅限于此,且可通过任意其他适当的方法来执行所述平坦化步骤。
参照图1E,在一些实施例中,在层间穿孔120、模制化合物130以及天线元件ATN上形成第一重布线层140。在一些实施例中,第一重布线层140物理地连接到层间穿孔120,并经由层间穿孔120电连接到天线元件ATN。除由第一重布线层140提供的布线功能以外,第一重布线层140的位于天线元件ATN之上并在垂直投影上与天线元件ATN重叠的一部分是接地平面部分(groundplane portion)GP,所述接地平面部分GP发挥天线元件ATN的接地板(groundplate)的作用。在一些实施例中,当天线元件ATN与接地平面部分GP之间存在特定距离(其与波长相关)时,接地平面部分GP充当天线辐射的反射器并确保天线的高增益/效率(high gain/efficiency)。由于此种构造的存在,因此可通过调整层间穿孔120的高度来控制天线元件ATN与接地平面部分GP之间的距离,从而使得随后形成的导电元件能够具有小的节距(fine pitch)且在设计印刷电路板(其经由随后形成的导电元件连接到封装结构10)时能够具有更好的灵活性。有鉴于此,此种构造可进一步减小封装结构10的高度。此外,在本公开内容中,除模制化合物130以外,在天线元件ATN与接地平面部分GP之间不存在由金属或金属性材料制成的额外的半导体元件(例如,无源组件/器件或有源组件/器件)或其他由金属或金属性材料制成的元件,从而确保天线应用的可靠性。形成第一重布线层140包括交替地依序形成一个或多个聚合物介电层142及一个或多个金属层144。在某些实施例中,如图1E所示,金属层144夹置在聚合物介电层142之间,但金属层144的顶表面被聚合物介电层142的最顶层暴露出,且金属层144的最底层被聚合物介电层142的最底层暴露出,以连接层间穿孔120。在一些实施例中,金属层144的材料包括铝、钛、铜、镍、钨及/或其合金,且金属层144可通过电镀或沉积来形成。在一些实施例中,聚合物介电层142的材料包括聚酰亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(BCB)、聚苯并恶唑(PBO)、或任意其他适当的聚合物系介电材料。
在一些实施例中,可在被暴露出的金属层144的最顶层的顶表面上设置多个球下金属(under-ball metallurgy,UBM)图案150用于与导电元件(例如,导电球)电连接,且/或可在被暴露出的金属层144的最顶层的顶表面上设置至少一个连接垫152用于与至少一个半导体元件(例如,无源组件/器件或有源组件/器件)电连接。如图1E所示,举例来说,形成多个球下金属图案150及多个连接垫152。在一些实施例中,举例来说,球下金属图案150及连接垫152的材料可包括铜、镍、钛、钨、或其合金等,且可通过电镀工艺来形成。在一个实施例中,球下金属图案150的材料可与连接垫152的材料相同。在另一实施例中,球下金属图案150的材料可与连接垫152的材料不同。在一个实施例中,在封装结构中可仅存在球下金属图案150;然而,在另一实施例中,可仅存在连接垫152。球下金属图案150及连接垫152的数目在本发明实施例中并无限制。
参照图1F,在形成第一重布线层140之后,在第一重布线层140上形成多个导电元件160。如图1F所示,在球下金属图案150上设置导电元件160。在一些实施例中,可通过植球工艺(ball placementprocess)或回流工艺(reflowprocess)在球下金属图案150上设置导电元件160。在一些实施例中,导电元件160是例如焊料球(solderball)或球栅阵列(ballgrid array,BGA)球。在一些实施例中,导电元件160经由球下金属图案150连接到第一重布线层140。如图1F所示,部分的导电元件160经由第一重布线层140、层间穿孔120以及部分的球下金属图案150电连接到天线元件ATN。
参照图1G,在第一重布线层140上提供并设置至少一个管芯170。如图1G所示,管芯170设置在连接垫152上,并经由连接垫152连接到第一重布线层140。在一些实施例中,管芯170可通过回流工艺设置在连接垫152上。在一些实施例中,导电元件160及管芯170形成在第一重布线层140的表面上,其中第一重布线层140位于模制化合物130与导电元件160之间且位于模制化合物130与管芯170之间。在一些实施例中,如图1G所示,管芯170包括:有源表面170a;多个垫170b,分布在有源表面170a上;钝化层170c,覆盖有源表面170a及垫170b的一部分;多个导电柱170d;以及保护层170e。垫170b局部地被钝化层170c暴露出,导电柱170d设置在垫170b上并电连接到垫170b,且保护层170e覆盖钝化层170c并暴露出导电柱170d。如图1G所示,管芯170经由导电柱170d及连接垫152电连接到第一重布线层140;管芯170经由导电柱170d、连接垫152、第一重布线层140以及一些球下金属图案150电连接到部分的导电元件160;且管芯170经由导电柱170d、连接垫152、第一重布线层140以及层间穿孔120电连接到天线元件ATN。在本发明实施例中,管芯170上覆天线元件ATN;也就是说,在第一重布线层140上的垂直投影中,管芯170的定位位置与天线元件ATN的定位位置重叠,此使得能够减小封装结构10的布局面积。此外,管芯170不模制在模制化合物130中,因此实现良好的散热。举例来说,导电柱170d是铜柱、铜合金柱、或其他适当的金属柱。在一些实施例中,保护层170e可以是聚苯并恶唑(PBO)层、聚酰亚胺(PI)层或其他适当的聚合物。在一些替代实施例中,保护层170e可由例如以下无机材料制成:氧化硅、氮化硅、氮氧化硅、或任意适当的介电材料。在一些实施例中,可在管芯170与连接垫152之间设置底部填充材料(图中未示出),以增强封装的可靠性。
如图1G所示,出于说明目的仅呈现了一个管芯,然而应注意,可提供一个或多个管芯。本文中所述的管芯可被称为芯片或集成电路(integrated circuit,IC)。在一些实施例中,管芯170包括至少一个无线及射频(radio frequency,RF)芯片。在一些实施例中,管芯170可进一步包括相同类型或不同类型的额外芯片。在替代实施例中,提供多于一个管芯170,且管芯170除包括至少一个无线及射频芯片以外还可包括选自以下的相同类型或不同类型的芯片:数位芯片(digital chip)、模拟芯片(analog chip)或混合信号芯片(mixedsignal chip)、应用专用集成电路(application-specific integrated circuit,ASIC)芯片、传感器芯片(sensor chip)、存储器芯片、逻辑芯片、或电压调节器芯片(voltageregulator chip)。
参照图1H,在一些实施例中,将载体112翻转(上下倒置),然后从介电层116剥离载体112以形成封装结构10。在一些实施例中,介电层116因剥离层114的存在而容易从载体112分开。在一些实施例中,通过剥离工艺,从介电层116分离载体112,并移除载体112及剥离层114。在一些实施例中,保留在天线元件ATN及模制化合物130上的介电层116充当保护层。作为另外一种选择,在一些实施例中,可随后移除介电层116并暴露出天线元件ATN的表面。在一些实施例中,执行分割工艺(dicing process)以将具有多个封装结构10的晶片切割成各个单独的封装结构10。在一个实施例中,所述分割工艺是包括机械刀片锯切(mechanical blade sawing)或激光切割(laser cutting)的晶片分割工艺(waferdicingprocess)。
如图1H所示,在一些实施例中,封装结构10包括至少一个层间穿孔120、模制化合物130、第一重布线层140、天线元件ATN、导电元件160以及至少一个管芯170。封装结构10进一步包括球下金属图案150及连接垫152。在一些实施例中,导电元件160及管芯170分别经由球下金属图案150及连接垫152而位于第一重布线层140上并连接到第一重布线层140。在一些实施例中,导电元件160及管芯170位于第一重布线层140的同一侧上,且不模制在模制化合物130中(位于模制化合物130外部),得以实现良好的散热。如图1H所示,连接到第一重布线层140的表面的层间穿孔120模制在模制化合物130中,且位于与导电元件160及管芯170相对的第一重布线层140的另一侧处。在一些实施例中,第一重布线层140位于导电元件160与模制化合物130之间,且位于管芯170与模制化合物130之间。在一些实施例中,第一重布线层140位于导电元件160与天线元件ATN及层间穿孔120之间并位于管芯170与天线元件ATN之间。在一些实施例中,天线元件ATN位于层间穿孔120上并物理地连接到层间穿孔120,且天线元件ATN经由层间穿孔120电连接到第一重布线层140。如图1H所示,层间穿孔120位于天线元件ATN与第一重布线层140之间并与天线元件ATN及第一重布线层140接触,以使得天线元件ATN与第一重布线层140电连接。详细来说,天线元件ATN及层间穿孔120与模制化合物130接触并模制在模制化合物130中,其中天线元件ATN的顶表面及层间穿孔120的底表面不被模制化合物130覆盖。在某些实施例中,天线元件ATN位于第一重布线层140及管芯170之上,其中管芯170的定位位置与天线元件ATN的定位位置对应并重叠(例如,在第一重布线层140的垂直投影中,天线元件ATN与管芯170重叠)。
由于天线元件ATN的构造及第一重布线层140的布局,因此第一重布线层140不仅提供布线功能,而且充当天线元件ATN的接地板。参照图1H及图6,接地平面部分GP包括:用于将连接导电元件160的布线及垫与其余金属层144隔离的开口Orp以及对应于管芯170的无源组件的位置的开口Opc。在一些实施例中,天线元件ATN的位置与第一重布线层140的接地平面部分GP的位置对应且重叠。由于管芯170位于模制化合物130外部、且在天线元件ATN与接地平面部分GP之间不存在额外的半导体元件(例如,无源组件/器件或有源组件/器件),因此管芯的散热更好、封装结构的可靠性更好、且天线的阵列增益及效率增强。此外,可通过调整层间穿孔120的高度来控制天线元件ATN与接地平面部分GP之间的距离,从而使得随后形成的导电元件能够具有小的节距及更好的灵活性。再者,由于在垂直投影中,管芯170的定位位置与天线元件ATN的定位位置重叠,因此实现封装结构10的紧凑的布局面积。在一些实施例中,部分的导电元件160经由部分的球下金属图案150、第一重布线层140、连接垫152以及导电柱170d电连接到管芯170。在一些实施例中,部分的导电元件160经由部分的球下金属图案150、第一重布线层140以及层间穿孔120电连接到天线元件ATN。
图2A至图2N是根据一些本发明实施例的封装结构的制造方法中的各阶段的示意性剖视图。图3是说明图2B所绘示层间穿孔壁与第二重布线层之间的相对位置的示意性俯视图。图4是说明图2M所绘示层间穿孔壁与第二金属图案之间的相对位置的示意性俯视图。与先前所述的元件相似或实质上相同的元件将使用相同的参考编号,下文中将不再对相同元件予以赘述。在一个示例性实施例中,举例来说,在图2A至图2N中,示出一个管芯来表示晶片的多个管芯,且示出封装结构20来表示通过所述制造方法所获得的封装结构。在其他实施例中,示出两个芯片或管芯来表示晶片的多个芯片或管芯,且示出一个或多个封装结构来表示通过所述(半导体)制造方法所获得的多个(半导体)封装结构,本发明实施例并不仅限于此。
参照图2A,在一些实施例中,提供载体212,且载体212可以是玻璃载体或任意适于所述封装结构的制造方法的载体。在一些实施例中,载体212涂布有剥离层214。剥离层214的材料可以是能够使载体212与位于其上的各层轻易脱离的任意材料。接下来,在载体212上形成第二重布线层240。形成第二重布线层240包括交替地依序形成一个或多个聚合物介电层242及一个或多个金属层244。第二重布线层240的材料及形成方法与图1E所述形成第一重布线层140的工艺相同或类似,下文中将不再予以赘述。如图2A所示,第二重布线层240包括一个聚合物介电层242及一个金属层244,且金属层244的顶表面(未标记)被暴露出。
参照图2B,在一些实施例中,在载体212上形成层间穿孔壁(throughinterlayervia wall)220,且层间穿孔壁220物理地连接到金属层244。在一些实施例中,层间穿孔壁220是贯穿集成扇出型穿孔,且层间穿孔壁220的形状具有以下形式:中空矩形框架(如图3所示)、中空圆形框架(图中未示出)、中空方形框架(图中未示出)、或中空多边形框架(图中未示出)等。在某些实施例中,层间穿孔壁220沿金属层244的边缘设置。在一些实施例中,层间穿孔壁220是通过光刻工艺、镀覆工艺、光刻胶剥除工艺、或任意其他适当的方法来形成。在一个实施例中,层间穿孔壁220可通过以下方式来形成:形成具有开口且覆盖于金属层244及聚合物介电层242上的掩模图案(图中未示出),所述开口暴露出金属层244的一部分,并通过电镀或沉积形成填充所述开口的金属材料以形成层间穿孔壁220,且然后移除掩模图案。然而,本发明实施例并不仅限于此。在一个实施例中,层间穿孔壁220的材料可包括金属材料,例如铜或铜合金等。
参照图2C,在一些实施例中,局部地模制第二重布线层240及层间穿孔壁220在模制化合物230a中。在一些实施例中,模制化合物230a至少填充两个封装结构20的层间穿孔壁220之间的间隙以及层间穿孔壁220与金属层244之间的间隙,并覆盖层间穿孔壁220的外侧壁(与内侧壁220a相对)、聚合物介电层242的被金属层244暴露出的一部分以及金属层244的一部分。在一些实施例中,模制化合物230a不形成在层间穿孔壁220的内侧壁220a上及不形成在被层间穿孔壁220环绕的第二重布线层240的表面(例如,金属层244的表面244a,参见图3)上。在一些实施例中,模制化合物230a例如可包含聚合物(例如,环氧树脂、酚醛树脂、含硅树脂、或其他适当的树脂)、具有低介电常数(Dk)性质及低损耗正切(Df)性质的介电材料、或其他适当的材料。根据高速应用的频率范围,可基于封装结构的所需电性性质来选择模制化合物230a的适当材料。在一些实施例中,形成模制化合物230a可包括:在层间穿孔壁220的顶部放置掩模(图中未示出),其中层间穿孔壁220的内侧壁220a及第二重布线层240的金属层244的表面244a被掩模覆盖;然后在被掩模暴露出的层间穿孔壁220及第二重布线层240上形成模制化合物230a;最后,移除掩模。在本公开内容中,形成模制化合物230a并不仅限于此,且可应用其他适当的形成方法。在某些实施例中,如图2C所示,层间穿孔壁220与模制化合物230a变得实质上齐平。在一个实施例中,如图2C所示,层间穿孔壁220的顶表面及模制化合物230a的顶表面共面。在一些实施例中,可进一步应用研磨工艺或化学机械抛光(CMP)工艺来平坦化模制化合物230a及层间穿孔壁220,因此模制化合物230a与层间穿孔壁220齐平。在研磨工艺之后,可视情况执行清洁步骤,例如以清洁并移除从研磨步骤产生的残余物。然而,本发明实施例并不仅限于此,且可通过任意其他适当的方法来执行所述研磨步骤。
参照图2D,在一些实施例中,将载体212翻转(上下倒置),且然后从第二重布线层240剥离载体212。在一些实施例中,第二重布线层240因剥离层214的存在而容易从载体212分开,且第二重布线层240的聚合物介电层242被暴露出。在一些实施例中,通过剥离工艺,从第二重布线层240分离载体212,并移除载体212及剥离层214。
参照图2E,在一些实施例中,将第二重布线层240放置在载体112上。在一些实施例中,载体112涂布有剥离层114。剥离层114的材料可以是能够使载体112与位于其上的各层轻易脱离的任意材料。如图2D所示,从载体212剥离的第二重布线层240通过使层间穿孔壁220及载体112与剥离层114接触而设置在载体112上。接下来,参见图2E,对被暴露出的第二重布线层240的聚合物介电层242进行图案化以形成暴露出金属层244的一部分的开口242a。在一些实施例中,对第二重布线层240的聚合物介电层242进行图案化可通过激光钻孔来执行。
参照图2F,在一些实施例中,在载体112上形成一个或多个层间穿孔120,且层间穿孔120物理地连接到第二重布线层240的金属层244。如图2F所示,层间穿孔120形成在第二重布线层240上,且经由被开口242a暴露出的金属层244电连接到层间穿孔壁220。层间穿孔120的材料及形成方法与图1B所述层间穿孔120的工艺相同或类似,因此下文将不再予以赘述。
如图2F所示,在第二重布线层240上提供并设置至少一个管芯170。在一些实施例中,在管芯170的背面(未标记)与第二重布线层240的聚合物介电层242之间设置管芯贴合膜DA,以使得管芯170稳固地粘合到第二重布线层240的聚合物介电层242。在一些实施例中,如图2F所示,管芯170包括:有源表面170a(与管芯170的背面相对);多个垫170b,分布在有源表面170a上;钝化层170c,覆盖有源表面170a及垫170b的一部分;多个导电柱170d;以及保护层170e。垫170b局部地被钝化层170c暴露出,导电柱170d设置在垫170b上并电连接到垫170b,且保护层170e覆盖钝化层170c并暴露出导电柱170d。图2F所示的管芯170的类型及管芯170的组件的材料与图1G所述管芯170相同或类似,因此下文中不再对其予以赘述。
参照图2G,在一些实施例中,模制层间穿孔120及管芯170在模制化合物230b中。在一些实施例中,模制化合物230b至少填充层间穿孔120之间的间隙以及层间穿孔120与管芯170之间的间隙,并覆盖层间穿孔120的侧壁及顶表面、管芯170的侧壁及顶表面、以及被层间穿孔120及管芯170暴露出的聚合物介电层242的表面。在一些实施例中,模制化合物230b例如可包含聚合物(例如,环氧树脂、酚醛树脂、含硅树脂、或其他适当的树脂)、具有低介电常数(Dk)性质及低损耗正切(Df)性质的介电材料、或其他适当的材料。根据高速应用的频率范围,可基于封装结构的所需电性性质来选择模制化合物230b的适当材料。在本公开内容中,模制化合物230a与模制化合物230b一起被称为模制化合物230;也就是说,模制化合物230包括模制化合物230a及模制化合物230b。在一个实施例中,模制化合物230a的材料与模制化合物230b的材料可相同,然而,本发明实施例并不仅限于此。在一个实施例中,模制化合物230a的材料与模制化合物230b的材料可不同。
参照图2H,在一些实施例中,对模制化合物230b及层间穿孔120进行平坦化,直到暴露出层间穿孔120的顶表面以及管芯170的导电柱170d及保护层170e的顶表面。在某些实施例中,如图2H所示,在平坦化之后,管芯170的导电柱170d及保护层170e变得与层间穿孔120及模制化合物230b实质上齐平。在一个实施例中,层间穿孔120的顶表面、导电柱170d的顶表面、保护层170e的顶表面、以及模制化合物230b的顶表面共面。在一些实施例中,通过研磨工艺或化学机械抛光(CMP)工艺对模制化合物230b及层间穿孔120进行平坦化。在研磨工艺之后,可视情况执行清洁步骤,例如以清洁并移除从研磨步骤产生的残余物。然而,本发明实施例并不仅限于此,且可通过任意其他适当的方法来执行所述平坦化步骤。
参照图2I,在一些实施例中,在载体112上形成第一重布线层140。在一些实施例中,第一重布线层140形成在层间穿孔120、管芯170以及模制化合物230(包括模制化合物230a及模制化合物230b)上,并物理地连接到管芯170及层间穿孔120。如图2I所示,第一重布线层140经由层间穿孔120电连接到第二重布线层240,第一重布线层140经由垫170b及导电柱170d电连接到管芯170,且第一重布线层140经由层间穿孔120及第二重布线层240电连接到第二层间穿孔壁。在一些实施例中,第一重布线层140包括交替排列的一个或多个聚合物介电层142及一个或多个金属层144。本文已在图1E中阐述了第一重布线层140的材料及形成方法,因此不再对其予以赘述。如图2I所示,管芯170设置在第一重布线层140与第二重布线层240之间。
接下来,在一些实施例中,可在被聚合物介电层142的最顶层暴露出的金属层144的最顶层的顶表面的一些部分上设置多个球下金属(UBM)图案150,以用于与导电元件(例如,导电球)电连接。如图2I所示,例如形成多个球下金属图案150。在一些实施例中,举例来说,球下金属图案150的材料可包括铜、镍、钛、钨、或其合金等,且可通过电镀工艺来形成。在本发明实施例中对球下金属图案150的数目并无限制。
参照图2J,在一些实施例中,在形成第一重布线层140之后,在第一重布线层140上形成多个导电元件160,且所述多个导电元件160经由球下金属图案150电连接到第一重布线层140。在一些实施例中,第一重布线层140位于模制化合物230与导电元件160之间、导电元件160与管芯170之间、以及导电元件160与层间穿孔120之间。如图2J所示,导电元件160物理地连接到球下金属图案150。在一些实施例中,可通过植球工艺或回流工艺在球下金属图案150上设置导电元件160。在一些实施例中,导电元件160是例如焊料球或球栅阵列(BGA)球。在一些实施例中,导电元件160经由球下金属图案150电连接到第一重布线层140。在一些实施例中,部分的导电元件160经由部分的球下金属图案150、第一重布线层140以及管芯170的导电柱170d电连接到管芯170。在一些实施例中,部分的导电元件160经由部分的球下金属图案150、第一重布线层140以及层间穿孔120电连接到第二重布线层240。
参照图2K,在一些实施例中,将载体112翻转(上下倒置),且然后从模制化合物230及层间穿孔壁220剥离载体112。模制化合物230及层间穿孔壁220因剥离层114的存在而容易从载体112分开,且层间穿孔壁220的内侧壁220a、被层间穿孔壁220环绕的金属层244的表面244a、以及模制化合物230的表面被暴露出。在一些实施例中,通过剥离工艺,从层间穿孔壁220以及模制化合物230分离载体112,并移除载体112及剥离层114。
参照图2L,在一些实施例中,将导电元件160安装到聚合物膜PF中,其中导电元件160完全嵌入聚合物膜PF中。在一些实施例中,聚合物膜PF的材料可包括具有足以使得导电元件160能够嵌入其中的弹性的聚合物膜。在一些实施例中,聚合物膜PF可以是石蜡膜(parafilm)或由其他适当的软性聚合物材料等制成的膜。接下来,如图2L所示,在一些实施例中,提供设置有第一金属图案182的顶盖层180,并将所述顶盖层180设置在从载体112剥离的模制化合物230及层间穿孔壁220上。在一些实施例中,顶盖层180的材料可包括具有低介电常数(Dk)性质及低损耗正切(Df)性质的介电材料、或其他适当的材料;例如熔融二氧化硅(其具有Dk~3.80且Df<0.001)。在某些实施例中,顶盖层180通过粘合剂设置在层间穿孔壁220及模制化合物230上。在一些实施例中,如图2L及图4所示,在层间穿孔壁220及模制化合物230上设置顶盖层180例如包括:将第一金属图案182的至少一部分经由导电粘合剂材料(图中未示出)连接到对应于预定重叠区域OP的层间穿孔壁220的一部分,因此使得第一金属图案182电连接到层间穿孔壁220;以及将顶盖层180的被第一金属图案182暴露出的表面180a经由粘合剂层181连接到层间穿孔壁220及模制化合物230。在本公开内容中,粘合剂层181的材料可以是任意适当的非导电粘合剂或胶水。
在替代实施例中,如图2L及图5所示,将第一金属图案182的一部分经由导电粘合剂材料(图中未示出)连接到对应于预定重叠区域OP的层间穿孔壁220的一部分,其中连接到第一金属图案182的对应于预定重叠区域OP的层间穿孔壁220的所述部分通过间隙与其余的层间穿孔壁220分隔开,且第一金属图案182及连接到第一金属图案182的对应于预定重叠区域OP的层间穿孔壁220的所述部分经由第二重布线层240的金属层244电连接到其余的层间穿孔壁220;且被第一金属图案182暴露出的顶盖层180的表面180a经由粘合剂层181连接到其余的层间穿孔壁220及模制化合物230。在一些实施例中,在层间穿孔壁220及模制化合物230上设置顶盖层180之前,可执行图案化工艺以在层间穿孔壁220中形成间隙,如图5所示。举例来说,所述图案化工艺可包括光刻及蚀刻。
如图2L所示,与顶盖层180相对的第一金属图案182的表面、顶盖层180的第一侧180a、第二重布线层240的金属层244的表面244a以及层间穿孔壁220的内侧壁220a一起界定空的空间S(即,空气腔AC),其中空气具有低介电常数(Dk)性质及低损耗正切(Df)性质。在一些实施例中,第一金属图案182及部分连接到第一金属图案182的层间穿孔壁220一起形成天线元件ATN,其中不仅第一重布线层140提供布线功能而且第二重布线层240的位于天线元件ATN之下并与天线元件ATN重叠的一部分充当天线元件ATN的接地平面部分GP。由于此种构造的存在,因此可通过调整层间穿孔壁220的高度来控制天线元件ATN与接地平面部分GP之间的距离,从而使得随后形成的导电元件能够具有小的节距且在设计印刷电路板(其经由随后形成的导电元件连接到封装结构20)时能够具有更好的灵活性。在本公开内容中,当天线元件ATN与接地平面部分GP之间存在某一距离(其与波长相关)时,接地平面部分GP充当天线辐射的反射器,确保天线的高增益/效率。由于顶盖层180及层间穿孔壁220的存在,因此天线元件ATN能够沿第一方向Y具有高增益辐射(high-gain rediation)并避免沿第二方向X的表面波/边缘辐射(surface wave/edge radiation)。此外,在本公开内容中,在天线元件ATN与接地平面部分GP之间不存在额外的半导体元件(例如,无源组件/器件或有源组件/器件)、或由金属材料及/或高介电常数介电材料制成的其他元件,从而确保天线应用的可靠性。如图2L所示,天线元件ATN上覆管芯170;也就是说,在第一重布线层140上的垂直投影中,管芯170的定位位置与天线元件ATN的定位位置重叠,相比于传统的天线元件和接地板的并排配置,此种配置能够减小封装结构20的布局面积。如图2L所示,天线元件ATN局部地接触模制化合物230a。
参照图2M,在一些实施例中,在将顶盖层180设置在层间穿孔壁220及模制化合物230上之后,在顶盖层180的第二侧180b上形成第二金属图案184,其中第二侧180b与设置有第一金属图案182(或者是说,天线元件ATN)的第一侧180a相对。在一些实施例中,第二金属图案184设置在层间穿孔壁220之上,其中第二金属图案184被形成为金属环形结构,且第二金属图案184的形状对应于层间穿孔壁220的形状(参见图4),并且顶盖层180位于第一金属图案182(即天线元件ATN)与第二金属图案184之间。天线元件ATN沿第二方向X的表面波/边缘辐射因第二金属图案184的存在而减小,使得表面波能够被反射,并因此减少天线系统中的不需要(unwanted)的边缘辐射。在一些实施例中,第二金属图案184是通过光刻工艺、沉积工艺、光刻胶剥除工艺、或任意其他适当的方法来形成。在一个实施例中,第二金属图案184可通过以下方式来形成:形成具有开口且覆盖于顶盖层180的第二侧180b的掩模图案(图中未示出),所述开口暴露出顶盖层180的一部分,并通过沉积形成填充所述开口的金属材料以形成第二金属图案184,且然后移除掩模图案,但本发明实施例并不仅限于此。在一个实施例中,第二金属图案184的材料可包括金属材料,例如铜或铜合金等。然而,本发明实施例并不仅限于此;在替代实施例中,第二金属图案184例如可在将顶盖层180设置在层间穿孔壁220及模制化合物230上之前先形成在顶盖层180上。
参照图2N,在一些实施例中,从聚合物膜PF释放导电元件160以形成封装结构20,并暴露出第一重布线层140及导电元件160。在一些实施例中,执行分割工艺以将具有多个封装结构20的晶片切割成各个单独的封装结构20。在一个实施例中,所述分割工艺为包括机械刀片锯切或激光切割的晶片分割工艺。
参照图2N,在一些实施例中,封装结构20包括层间穿孔120、第一重布线层140、导电元件160、至少一个管芯170、顶盖层180、第一金属图案182、第二金属图案184、层间穿孔壁220、模制化合物230(包括模制化合物230a及模制化合物230b)、第二重布线层240以及天线元件ATN。封装结构20进一步包括球下金属图案150。在一些实施例中,管芯170及位于管芯170旁边的层间穿孔120位于第一重布线层140上并物理地连接到第一重布线层140,且模制在模制化合物230(例如,模制化合物230b)中。导电元件160设置在与管芯170及层间穿孔120相对的第一重布线层140的表面上,且第一重布线层140位于导电元件160与模制化合物230之间。如图2N所示,第二重布线层240位于模制化合物230(例如,模制化合物230a)、层间穿孔120、管芯170以及第一重布线层140上,且第二重布线层240经由层间穿孔120电连接到第一重布线层140,并经由层间穿孔壁220电连接到第一金属图案182。层间穿孔120及管芯170位于第一重布线层140与第二重布线层240之间。
在一些实施例中,层间穿孔壁220位于第二重布线层240上并物理地连接到第二重布线层240,其中层间穿孔壁220及第二重布线层240局部地模制在模制化合物230的模制化合物230a中,且层间穿孔壁220的内侧壁220a及第二重布线层240的表面244a既不被模制化合物230(例如,模制化合物230a)覆盖也不与所述模制化合物230接触。如图2N所示,层间穿孔壁220经由第二重布线层240电连接到层间穿孔120,并经由第二重布线层240及层间穿孔120电连接到第一重布线层140。在一些实施例中,顶盖层180位于模制化合物230(例如,模制化合物230a)上并位于第一金属图案182与第二金属图案184之间,其中位于顶盖层180的表面180a上的第一金属图案182电连接到层间穿孔壁220的一部分,且位于顶盖层180的表面180b上的第二金属图案184位于层间穿孔壁220之上并于第一重布线层140上的垂直投影与层间穿孔壁220重叠。如图2N所示,第一金属图案182位于模制化合物230及层间穿孔壁220上,顶盖层180位于第一金属图案182上并覆盖第一金属图案182,且第二金属图案184位于顶盖层180上,其中顶盖层180夹置在第一金属图案182与第二金属图案184之间。在一些实施例中,模制化合物230位于顶盖层180与第一重布线层140之间。
在一些实施例中,如图2N所示,第一金属图案182与部分连接到第一金属图案182的层间穿孔壁220一起形成天线元件ATN,其中不仅第一重布线层140提供布线功能而且第二重布线层240的位于天线元件ATN之下的一部分充当天线元件ATN的接地平面部分GP。由于此种构造的存在,因此可通过调整层间穿孔壁220的高度来控制天线元件ATN与接地平面部分GP之间的距离,从而使得随后形成的导电元件能够具有小的节距且在设计印刷电路板(其经由随后形成的导电元件连接到封装结构20)时能够具有更好的灵活性。当天线元件ATN与接地平面部分部分GP之间存在某一距离(其与波长相关)时,接地平面部分GP充当天线辐射的反射器,并确保天线的高增益/效率。由于位于顶盖层180与层间穿孔壁220之间存在有空气腔AC(所述腔内的空气具有Dk=1、Df~0),因此天线元件ATN能够沿第一方向Y具有高增益辐射并避免沿第二方向X的表面波/边缘辐射。此外,在本公开内容中,在天线元件ATN与接地平面部分GP之间不存在额外的半导体元件(例如,无源组件/器件或有源组件/器件)、或由金属材料及/或高介电常数介电材料制成的其他元件,从而确保天线应用的可靠性。在一些实施例中,天线元件ATN位于顶盖层180与第二重布线层240之间。在一些实施例中,部分的导电元件160经由部分的球下金属图案150、第一重布线层140以及导电柱170d电连接到管芯170。在一些实施例中,部分的导电元件160经由部分的球下金属图案150、第一重布线层140以及层间穿孔120电连接到第二重布线层240。在一些实施例中,部分的导电元件160经由部分的球下金属图案150、第一重布线层140、层间穿孔120、第二重布线层240以及层间穿孔壁220电连接到天线元件ATN。
在一些实施例中,天线元件ATN局部地接触模制化合物230(例如,模制化合物230a),其中朝向第二重布线层240的天线元件ATN的面侧、朝向天线元件ATN的第二重布线层240的面侧、以及未被模制化合物230(模制化合物230a或模制化合物230b)覆盖的层间穿孔壁220的内侧壁220a一起用于界定空气腔AC的空间S。如图2N所示,空气腔AC位于天线元件ATN、第二重布线层240以及层间穿孔壁220之间。在某些实施例中,天线元件ATN经由层间穿孔壁220电连接到第二重布线层240,且上覆管芯170。也就是说,在第一重布线层140上的垂直投影中,管芯170的定位位置与天线元件ATN的定位位置重叠,相比于传统的天线元件和接地板的并排配置,此种配置能够产生较小的布局面积的封装结构20。在一些实施例中,位于层间穿孔壁220之上的第二金属图案184的形状对应层间穿孔壁220的形状(如图4所示)。由于第二金属图案184的存在,因此减小了天线元件ATN沿第二方向X的表面波/边缘辐射。
根据一些实施例,一种封装结构包括模制化合物、天线元件、至少一个管芯、以及重布线层。所述天线元件模制在所述模制化合物中。所述至少一个管芯位于所述模制化合物上。所述重布线层位于所述至少一个管芯与所述模制化合物之间,其中所述重布线层包括接地平面部分,且在垂直投影中,所述天线元件的位置与所述接地平面部分的位置重叠。
根据一些实施例,所述封装结构进一步包括包封在所述模制化合物中的至少一个层间穿孔,其中所述至少一个层间穿孔连接到所述天线元件且所述天线元件经由所述重布线层及所述至少一个层间穿孔电连接到所述至少一个管芯。
根据一些实施例,在所述封装结构中,在所述垂直投影中,所述天线元件的所述位置与所述至少一个管芯的位置重叠。
根据一些实施例,所述封装结构进一步包括连接到所述重布线层的多个导电元件,其中所述重布线层位于所述多个导电元件与所述天线元件之间,且所述至少一个管芯与所述多个导电元件位于所述重布线层的表面上。
根据一些实施例,所述封装结构进一步包括保护层,所述保护层位于所述模制化合物上且覆盖所述天线元件。
根据一些实施例,一种封装结构包括至少一个管芯、天线元件、以及层间穿孔壁。所述天线元件位于所述至少一个管芯上方。所述层间穿孔壁位于所述天线元件与所述至少一个管芯之间,其中所述层间穿孔壁连接到所述天线元件,空气腔位于所述天线元件与所述至少一个管芯之间且被所述层间穿孔壁环绕,且所述天线元件电连接到所述至少一个管芯。
根据一些实施例,所述封装结构进一步包括连接到所述至少一个管芯的第一重布线层、位于所述至少一个管芯上的第二重布线层以及连接到所述第一重布线层及所述第二重布线层且排列在所述至少一个管芯旁边的至少两个层间穿孔,其中所述至少一个管芯位于所述第一重布线层与所述第二重布线层之间,且所述天线元件经由所述层间穿孔壁、所述第二重布线层、所述至少两个层间穿孔及所述第一重布线层电连接到所述至少一个管芯。
根据一些实施例,所述封装结构进一步包括模制化合物,其中所述天线元件、所述层间穿孔壁、所述至少一个管芯、所述第二重布线层及所述至少两个层间穿孔被模制在所述模制化合物中,其中所述层间穿孔壁的内侧壁、被所述层间穿孔壁的所述内侧壁环绕且面朝所述至少一个管芯的所述天线元件的表面、以及被所述层间穿孔壁的所述内侧壁环绕且面朝所述天线元件的所述第二重布线层的表面不含所述模制化合物。
根据一些实施例,所述封装结构进一步包括多个导电元件,连接到所述第一重布线层,其中所述第一重布线层位于所述多个导电元件与所述至少一个管芯之间。
根据一些实施例,所述封装结构进一步包括位于所述天线元件上的顶盖层以及设置在与所述天线元件相对的所述顶盖层的表面上的金属环形结构,其中所述天线元件位于所述顶盖层与所述层间穿孔壁之间。
根据一些实施例,一种制造封装结构的方法设置有以下步骤:在第一载体上形成第一重布线层;在所述第一载体上形成至少一个层间穿孔,其中所述至少一个层间穿孔电连接到所述第一重布线层;将所述至少一个层间穿孔包封在模制化合物中;在所述第一载体上设置至少一个管芯,其中所述至少一个管芯电连接到所述第一重布线层;形成天线元件,其中所述天线元件至少局部地接触所述模制化合物且电连接到所述第一重布线层,且在所述第一重布线层上的垂直投影中,所述天线元件与所述至少一个管芯重叠;以及将多个导电元件设置在所述第一重布线层上,其中所述第一重布线层位于所述模制化合物与所述多个导电元件之间。
根据一些实施例,在所述制造封装结构的方法中,所述天线元件是在所述第一载体上形成所述第一重布线层、所述至少一个层间穿孔及所述至少一个管芯之前形成在所述第一载体上。
根据一些实施例,在所述制造封装结构的方法中,在所述天线元件上形成所述至少一个层间穿孔之后,将所述天线元件及所述至少一个层间穿孔包封在所述模制化合物中,且接着在所述至少一个层间穿孔上形成所述第一重布线层,其中所述至少一个管芯及所述多个导电元件设置在与所述模制化合物相对的所述第一重布线层的表面上且不被模制在所述模制化合物中。
根据一些实施例,在所述制造封装结构的方法中,在所述第一载体上设置所述至少一个管芯以及在形成所述至少一个层间穿孔、所述第一重布线层及所述天线元件之前,所述制造封装结构的方法进一步包括在第二载体上形成第二重布线层;在所述第二重布线层上形成层间穿孔壁,其中所述层间穿孔壁电连接到所述第二重布线层;将所述第二重布线层及所述层间穿孔壁包封在所述模制化合物中;以及从所述第二重布线层剥离所述第二载体并通过使所述层间穿孔壁与所述第一载体接触将所述第二重布线层设置在所述第一载体上。
根据一些实施例,在所述制造封装结构的方法中,包封所述第二重布线层及所述层间穿孔壁包括局部地包封所述第二重布线层及所述层间穿孔壁,其中所述层间穿孔壁的内侧壁及被所述层间穿孔壁的所述内侧壁环绕的所述第二重布线层的侧不被所述模制化合物覆盖。
根据一些实施例,在所述制造封装结构的方法中,设置所述至少一个管芯包括:在所述至少一个层间穿孔形成在所述第二重布线层上之后,将所述至少一个管芯设置在与所述层间穿孔壁相对的所述第二重布线层的侧上,其中所述至少一个管芯形成在设置有所述至少一个层间穿孔的所述第二重布线层的所述侧上,且将所述至少一个层间穿孔包封在所述模制化合物中包括将所述至少一个管芯及所述至少一个层间穿孔包封在所述模制化合物中。
根据一些实施例,在所述制造封装结构的方法中,形成所述第一重布线层包括在包封所述至少一个层间穿孔之后,在所述模制化合物上形成所述第一重布线层,其中所述第一重布线层经由所述至少一个层间穿孔电连接到所述第二重布线层,且所述至少一个管芯位于所述第一重布线层与所述第二重布线层之间。
根据一些实施例,在所述制造封装结构的方法中,在将多个导电元件设置在所述第一重布线层上之后,所述制造封装结构的方法进一步包括从所述层间穿孔壁及所述模制化合物剥离所述第一载体;以及将所述多个导电元件安装在聚合物膜中,其中所述多个导电元件嵌入所述聚合物膜中。
根据一些实施例,在所述制造封装结构的方法中,在将所述多个导电元件安装在所述聚合物膜中之后,所述制造封装结构的方法进一步包括提供顶盖层,所述顶盖层具有设置有第一金属图案的第一侧;以及将所述顶盖层通过所述第一侧设置在所述层间穿孔壁及所述模制化合物上,且其中所述顶盖层的所述第一侧、所述层间穿孔壁的内侧壁、以及朝向所述顶盖层的所述第一侧且被由不被所述模制化合物覆盖的所述层间穿孔壁的所述内侧壁环绕的所述第二重布线层的侧构成空气腔的容纳空间,其中形成天线元件包括将所述第一金属图案连接到所述层间穿孔壁的一部分,以使所述第一金属图案及所述层间穿孔壁的连接到所述第一金属图案的所述一部分一同形成所述天线元件。
根据一些实施例,在所述制造封装结构的方法中,所述制造封装结构的方法进一步包括在与设置有所述天线元件的所述第一侧相对的所述顶盖层的第二侧上形成第二金属图案,其中所述第二金属图案设置在所述层间穿孔壁之上,所述第二金属图案的形状对应于所述层间穿孔壁的形状,且所述顶盖层位于所述天线元件与所述第二金属图案之间。
以上概述了若干实施例的特征,以使所属领域中的技术人员可更好地理解本发明实施例的各个方面。所属领域中的技术人员应知,其可容易地使用本发明实施例作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到,这些等效构造并不背离本发明实施例的精神及范围,而且他们可在不背离本发明实施例的精神及范围的条件下对其作出各种改变、代替以及变更。
Claims (21)
1.一种封装结构,其特征在于,包括:
至少一个管芯;
天线元件,位于所述至少一个管芯上方;以及
层间穿孔壁,位于所述天线元件与所述至少一个管芯之间,其中所述层间穿孔壁连接到所述天线元件,空气腔位于所述天线元件与所述至少一个管芯之间且被所述层间穿孔壁环绕,且所述天线元件电连接到所述至少一个管芯。
2.根据权利要求1所述的封装结构,其特征在于,进一步包括:
第一重布线层,连接到所述至少一个管芯;
第二重布线层,位于所述至少一个管芯上,其中所述至少一个管芯位于所述第一重布线层与所述第二重布线层之间;以及
至少两个层间穿孔,连接到所述第一重布线层及所述第二重布线层且排列在所述至少一个管芯旁边,
其中所述天线元件经由所述层间穿孔壁、所述第二重布线层、所述至少两个层间穿孔、及所述第一重布线层电连接到所述至少一个管芯。
3.根据权利要求2所述的封装结构,其特征在于,进一步包括模制化合物,其中所述天线元件、所述层间穿孔壁、所述至少一个管芯、所述第二重布线层及所述至少两个层间穿孔被模制在所述模制化合物中,其中所述层间穿孔壁的内侧壁、被所述层间穿孔壁的所述内侧壁环绕且面朝所述至少一个管芯的所述天线元件的表面、以及被所述层间穿孔壁的所述内侧壁环绕且面朝所述天线元件的所述第二重布线层的表面不含所述模制化合物。
4.根据权利要求2所述的封装结构,其特征在于,进一步包括:
多个导电元件,连接到所述第一重布线层,其中所述第一重布线层位于所述多个导电元件与所述至少一个管芯之间。
5.根据权利要求1所述的封装结构,其特征在于,进一步包括:
顶盖层,位于所述天线元件上,其中所述天线元件位于所述顶盖层与所述层间穿孔壁之间;以及
金属环形结构,设置在与所述天线元件相对的所述顶盖层的表面上,其中所述金属环形结构位于所述层间穿孔壁之上,且所述金属环形结构的形状对应于所述层间穿孔壁的形状。
6.一种封装结构,其特征在于,包括:
第一模制化合物及位于所述第一模制化合物上的第二模制化合物;
半导体管芯,模制在所述第一模制化合物中;以及
层间穿孔壁,位于所述半导体管芯上并电连接至所述半导体管芯,所述层间穿孔壁包括具有内表面与相对于所述内表面的外表面的环形形状,其中所述层间穿孔壁模制在所述第二模制化合物中,且空腔位于所述层间穿孔壁内并被所述内表面环绕。
7.根据权利要求6所述的封装结构,其特征在于,所述层间穿孔壁具有包括连续结构的所述环形形状。
8.根据权利要求6所述的封装结构,其特征在于,所述层间穿孔壁具有包括多个空隙的非连续结构的所述环形形状。
9.根据权利要求6所述的封装结构,其特征在于,所述层间穿孔壁的所述内表面不接触所述第二模制化合物,且所述层间穿孔壁的所述外表面被所述第二模制化合物包绕。
10.根据权利要求6所述的封装结构,其特征在于,进一步包括位于所述半导体管芯之上并与所述半导体管芯电连接的天线元件,其中所述天线元件包括第一部分、第二部分及连接所述第一部分与所述第二部分的第三部分,其中所述天线元件的所述第一部分位于所述空腔内且不接触所述第一模制化合物,所述天线元件的所述第二部分连接至所述层间穿孔壁且不接触所述第一模制化合物,所述天线元件的所述第三部分模制于所述第二模制化合物中且不接触所述第一模制化合物。
11.根据权利要求10所述的封装结构,其特征在于,进一步包括:
顶盖层,位于所述天线元件上,其中所述天线元件位于所述顶盖层与所述层间穿孔壁之间;以及
金属环形结构,设置在与所述天线元件相对的所述顶盖层的表面上,其中所述金属环形结构位于所述层间穿孔壁之上,且所述金属环形结构的形状对应于所述层间穿孔壁的所述环形形状。
12.根据权利要求6所述的封装结构,其特征在于,进一步包括:
第一重布线层,位于所述半导体管芯上;
多个层间穿孔,位于所述第一重布线层上且模制于所述第一模制化合物中;以及
第二重布线层,位于所述多个层间穿孔上以及在述第一模制化合物与述第二模制化合物之间,
其中所述半导体管芯位于所述第一重布线层与所述第二重布线层之间并与所述第一重布线层与所述第二重布线层电连接,所述多个层间穿孔经由所述第二重布线层电连接至所述半导体管芯,所述层间穿孔壁经由所述第二重布线层、所述多个层间穿孔及所述第一重布线层电连接至所述半导体管芯。
13.根据权利要求12所述的封装结构,其特征在于,进一步包括:
多个导电元件,连接到所述第一重布线层,其中所述多个导电元件经由所述第一重布线层电连接至所述半导体管芯,且所述第一重布线层位于所述多个导电元件与所述半导体管芯之间。
14.一种封装结构,其特征在于,包括:
第一重布线层,具有第一表面及与所述第一表面相对的第二表面;
至少一个管芯,位于所述第一重布线层的所述第二表面上;
层间穿孔壁,位于所述第一重布线层的所述第一表面上;
顶盖层,位于所述层间穿孔壁上,其中所述层间穿孔壁位于所述第一重布线层与所述顶盖层之间;
模制化合物,具有第一部分与位于所述第一部分之下的第二部分,其中所述至少一个管芯被包封在所述模制化合物的所述第二部分中,且所述层间穿孔壁被包封在所述模制化合物的所述第一部分中;
空腔,位于所述模制化合物的所述第一部分内,且被所述顶盖层、所述第一重布线层及所述层间穿孔壁环绕;以及
天线元件,至少部份地位于所述空腔中。
15.根据权利要求14所述的封装结构,其特征在于,所述空腔是不与所述模制化合物接触的空气腔。
16.根据权利要求14所述的封装结构,其特征在于,所述层间穿孔壁为闭环形状或包括多个空隙的环形形状。
17.根据权利要求14所述的封装结构,其特征在于,进一步包括:
第二重布线层,位于所述模制化合物的所述第二部分及所述至少一个管芯之上;
多个层间穿孔,位于所述至少一个管芯旁且贯穿所述模制化合物的所述第二部分,其中所述多个层间穿孔电连接到所述第一重布线层及所述第二重布线层;以及
多个导电元件,位于所述第二重布线层上,其中所述第二重布线层位于所述所述模制化合物的所述第二部分与所述多个导电元件之间。
18.根据权利要求14所述的封装结构,其特征在于,进一步包括:
金属环形结构,设置在所述顶盖层上,其中所述顶盖层夹置在所述天线元件与所述金属环形结构之间,且所述金属环形结构的形状对应于所述层间穿孔壁的所述环形形状。
19.一种制造封装结构的方法,其特征在于,包括:
形成第一重布线层;
在所述第一重布线层的第一表面上形成层间穿孔壁;
经由第一模制化合物部份地覆盖所述第一重布线层与所述层间穿孔壁;
于所述第一重布线层之上以及在所述层间穿孔壁与所述第一模制化合物上形成顶盖层,以形成被所述第一重布线层、所述层间穿孔壁与所述顶盖层环绕之空腔,所述顶盖层设置有位于其上的天线元件,其中所述天线元件是至少部份地位在所述空腔中;
在所述第一重布线层的第二表面上设置至少一个管芯,所述第一表面与所述第二表面相对;以及
侧向地包封所述至少一个管芯于第二模制化合物中。
20.根据权利要求19所述的方法,其特征在于,在侧向地包封所述至少一个管芯于所述第二模制化合物中之前,进一步包括:
形成多个层间穿孔于所述第一重布线层的所述第二表面上,
其中侧向地包封所述至少一个管芯于所述第二模制化合物中进一步包括侧向地包封所述多个层间穿孔于所述第二模制化合物中。
21.根据权利要求20所述的方法,其特征在于,在侧向地包封所述至少一个管芯于所述第二模制化合物中之后,进一步包括:
形成第二重布线层于所述第二模制化合物之上;以及
形成多个导电元件于所述第二重布线层上,所述第二重布线层位在所述至少一个管芯与所述多个导电元件之间。
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CN109273433A (zh) | 2019-01-25 |
TW201909375A (zh) | 2019-03-01 |
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US10186492B1 (en) | 2019-01-22 |
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