CN103474464B - 一种复合机制的条形栅隧穿场效应晶体管及其制备方法 - Google Patents
一种复合机制的条形栅隧穿场效应晶体管及其制备方法 Download PDFInfo
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Abstract
本发明公开了一种复合机制的条形栅隧穿场效应晶体管及其制备方法，属于CMOS超大集成电路(ULSI)中的场效应晶体管逻辑器件与电路领域。该隧穿场效应晶体管通过改变栅形貌，利用条形栅两侧的PN结耗尽效应使得栅下表面沟道能带提高，改善了器件的亚阈特性，并利用双掺杂源区引入的复合机制有效地提高了器件的开态电流，且“工”字犁的有源区的设计可以大大抑制从两部分掺杂源区到掺杂漏区之间的体泄漏电流，包括源漏直接隧穿电流和穿通电流，抑制了短沟效应，从而使得器件能应用在更小的尺寸下。
Description
技术领域
本发明属于CMOS超大集成电路(ULSI)中的场效应晶体管逻辑器件与电路领域，具体涉及一种复合机制的条形栅隧穿场效应晶体管及其制备方法。
背景技术
在摩尔定律的驱动下，传统MOSFET的特征尺寸不断缩小，如今已经进入纳米尺度，随之而来，器件的短沟道效应等负面影响也愈加严重。漏致势垒降低、带带隧穿等效应使得器件关态漏泄电流不断增大，同时，传统MOSFET的亚阈值斜率受到热电势的限制无法随着器件尺寸的缩小而同步减小，由此增加了器件功耗。功耗问题如今已经成为限制器件等比例缩小的最严峻的问题。
为了能将器件应用在超低压低功耗领域，采用新型导通机制而获得超陡亚阈值斜率的器件结构和工艺制备方法已经成为小尺寸器件下大家关注的焦点。近些年来研究者们提出了一种可能的解决方案，就是采用隧穿场效应晶体管(TFET)。TFET不同于传统MOSFET，其源漏掺杂类犁相反，利用栅极控制反向偏置的P-I-N结的带带隧穿实现导通，能突破传统MOSFET亚阈值斜率60mV/dec的限制，并且其漏电流非常小。TFET具有低漏电流、低亚阈值斜率、低工作电压和低功耗等诸多优异特性，但由于受源结隧穿几率和隧穿面积的限制，TFET面临着开态电流小的问题，远远比不上传统MOSFET器件，极大限制了TFET器件的应用。另外，具有陡直亚阈值斜率的TFET器件在实验上也较难实现，这是因为实验较难在源结处实现陡直的掺杂浓度梯度以致器件开启时隧穿结处的电场不够大，这会导致TFET的亚阈值斜率相对理论值退化。因此，如何在源结实现陡直的掺杂浓度梯度而获得超低的亚阈值斜率，同时获得较高的开态电流，成为了现今TFET器件面临的主要问题。
发明内容
本发明的目的在于提出一种复合机制的条形栅隧穿场效应晶体管及其制备方法。在与现有的CMOS工艺完全兼容的条件下，该结构改变了传统隧穿场效应晶体管的栅版图结构以及沟道形貌，能等效实现陡直的源结掺杂浓度的效果，显著优化TFET器件的亚阈值斜率，并同时有效抑制短沟情况下的源漏直接隧穿电流，保持低的泄漏电流。另外，在源端相反类型的深结深的掺杂能一方面进一步优化该器件的源端隧穿结，进一步增大带带隧穿开启时的电场，从而优化TFET器件的亚阂特性，另一方面在稍高栅压的情况下开启较大的正向PN结电流，从而优化器件的导通电流。同时，较低掺杂的漏区也可有效抑制TFET器件的双极效应。
本发明的技术方案如下：
本发明隧穿场效应晶体管包括一个半导体衬底、一个掺杂源区、一个掺杂漏区、一个控制栅和一个栅介质层。所述掺杂源区和掺杂漏区分别位于控制栅的两侧，其特征在于，掺杂源区由高浓度的浅结掺杂区和较低浓度的深结掺杂区两部分组成，且这两部分掺有不同掺杂类犁的杂质，高浓度的浅结掺杂源区的掺杂浓度在1×1020cm-3至1×1021cm-3之间，结深<20nm，掺杂漏区和较低浓度的深结掺杂源区的掺杂浓度在1×1018cm-3至1×1019cm-3之间，结深需大于浅结源区和耗尽层宽度之和，典犁值为>40nm，其中，较低浓度的深结掺杂源区和掺杂漏区的杂质类犁和浓度均一致，靠条形栅自对准同时形成。与通常的隧穿场效应晶体管的控制栅相比，本发明控制栅为栅长大于栅宽的条形结构，控制栅的一侧与掺杂漏区连接，控制栅的另一侧向掺杂源区横向延伸，即条形控制栅部分位于掺杂源区和掺杂漏区之间，另一部分延伸到掺杂源区，所述两部分掺杂源区均靠条形栅自对准形成，条形栅下无掺杂区域，位于条形栅下的区域仍是沟道区，位于掺杂源区和掺杂漏区之间的有源区仅存在控制栅以下的沟道区，器件的有源区俯视呈“工”字犁。衬底的掺杂浓度在1×1014cm-3至1×1017cm-3之间。所述较低浓度掺杂源区的掺杂面积相对高浓度掺杂源区的掺杂面积更大，以便同时能将两部分掺杂源区电引出。所述控制栅的位于掺杂源区和掺杂漏区之间的长度与延伸到掺杂源区的长度比为1∶1—1∶5，控制栅的栅宽小于2倍的源耗尽层宽度，源耗尽层宽度的范围为25nm一1.5um。
上述隧穿场效应晶体管的制备方法，包括以下步骤：
(1)在半导体衬底上通过光刻刻蚀出“工”字型有源区；
(2)生长栅介质层；
(3)淀积控制栅材料，接着光刻和刻蚀，形成条形栅图形；
(4)以控制栅为掩膜，离子注入，自对准形成较低浓度掺杂源区和掺杂漏区；
(5)光刻暴露出高浓度掺杂源区，以光刻胶和控制栅为掩膜，离子注入形成另一种掺杂类型的高浓度的浅结掺杂源区，然后快速高温热退火激活源漏掺杂杂质；
(6)最后进入常规CMOS后道工序，包括淀积钝化层、开接触孔以及金属化等，即可制得所述的隧穿场效应晶体管，如图5所示。
上述的制备方法中，所述步骤(1)中的半导体衬底材料选自Si、Ge、SiGe、GaAs或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅(SOI)或绝缘体上的锗(GOI)。
上述的制备方法中，所述步骤(2)中的栅介质层材料选自Si02、Si3N4和高K栅介质材料。
上述的制备方法中，所述步骤(2)中的生长栅介质层的方法选自下列方法之一：常规热氧化、掺氮热氧化、化学气相淀积和物理气相淀积。
上述的制备方法中，所述步骤(3)中的控制栅材料选白掺杂多晶硅、金属钴，镍以及其他金属或金属硅化物。
本发明的技术效果如下：
一、在相同的有源区面积下，本发明利用延展进源区内的条形栅，能实现更大的隧穿面积，进而能得到高于传统TFET的导通电流；并由于在源区注入了相对高浓度掺杂更深结深的较低浓度的掺杂杂质，使得在较深结深处的杂质没有被杂质补偿和耗尽，从而在较高栅压时能提供较大的正向PN结导通电流，大大提高了器件的开态电流。并由于在源区注入了相反类型的深结深的较低浓度的杂质，能使得该器件源结处的隧穿结获得更加陡峭的能带弯曲，从而使得器件发生带带隧穿时的电场更大，进一步提高TFET器件的亚阈值斜率。
二、在与现有的CMOS工艺完全兼容的条件下，通过改变栅形貌，利用条形栅两侧的PN结耗尽效应使得栅下表面沟道能带提高，因此当该器件发生带带隧穿时能获得比传统TFET更陡的能带和更窄的隧穿势垒宽度，等效实现了陡直的隧穿结掺杂浓度梯度的效果，从而大幅提高传统TFET的亚阈特性；且“工”字型的有源区的设计可以大大抑制从两部分掺杂源区到掺杂漏区之间的体泄漏电流，包括源漏直接隧穿电流和穿通电流，抑制了短沟效应，从而使得器件能应用在更小的尺寸下。同时，较低浓度的掺杂漏区的设计也可以有效抑制来自漏结处的隧穿电流，抑制TFET器件的双极效应，并进一步降低器件的泄漏电流。
简而言之，该器件结构采用了条形栅结构、“工”字型有源区和双掺杂源区的设计，引入了带带隧穿和正向PN结的复合机制，一方面有效地调制了传统TFET器件的源端隧穿结，实现了源结具有更加陡直的能带弯曲和更大的隧穿电场的效果，提高了TFET器件的亚阈特性，另一方面引入的更大的隧穿面积和正向PN结电流能大大增加器件的开态电流，同时抑制了短沟情况下的泄漏电流。与现有的TFET相比，该器件制备工艺简单，并可以得到更高的导通电流和更陡直的亚阈值斜率，且能保持低的泄漏电流，有望在低功耗领域得到采用，有较高的实用价值。
附图说明
图1是在半导体衬底上光刻形成“工”字型有源区的工艺步骤示意图，其中(a)是相应器件的立体图；(b)是相应器件的俯视图；
图2是在刻蚀后形成的有源区上生长栅介质层并光刻刻蚀形成了条形控制栅的器件示意图，其中(a)是相应器件的立体图；(b)是相应的器件俯视图；
图3是离子注入形成较低浓度的掺杂源区和掺杂漏区后的器件示意图，其中(a)是相应器件的立体图；(b)是相应的器件俯视图；
图4是光刻暴露出高浓度掺杂源区并离子注入形成不同掺杂类犁的高浓度浅结掺杂源区后的器件示意图，其中(a)是相应器件的立体图；(b)是相应的器件俯视图；
图5是本发明的复合机制的条形栅隧穿场效应晶体管的器件示意图，其中(a)是相应器件的立体图；(b)是相应的器件沿图5(a)的AA'虚线方向的剖面图，(c)是相应的器件沿图5(a)的BB’虚线方向的剖面图；
图中：
1——半导体衬底2——光刻胶
3——栅介质层4——控制栅
5——较低浓度掺杂漏区6——较低浓度的深结掺杂源区
7——相反类犁的高浓度浅结掺杂源区
具体实施方式
下面通过实例对本发明做进一步说明。需要注意的是，公布实施例的目的在于帮助进一步理解本发明，但是本领域的技术人员可以理解：在不脱离本发明及所附权利要求的精神和范围内，各种替换和修改都是可能的。因此，本发明不应局限于实施例所公开的内容，本发明要求保护的范围以权利要求书界定的范围为准。
本发明制备方法的一具体实例包括图1至图5所示的工艺步骤：
1、选取晶向为(1007)的体硅硅片硅衬底1，衬底掺杂浓度为轻掺杂，在其上光刻出“工”字犁有源区图形，如图1(a)、图1(b)所示；然后以厚光刻胶2为掩膜，深刻蚀硅材料，形成“工”字犁有源区。
2、热生长一层栅介质层3，栅介质层为Si02，厚度为l～5nm；淀积栅材料4，栅材料为掺杂多晶硅层，厚度为150～300nm；光刻出条形栅图形，刻蚀栅材料4直到栅介质层3，如图2(a)、图2(b)所示，条形栅宽度典型为lμm。
3、以条形栅栅为掩膜进行自对准P离子注入，形成掺杂漏区5和较低浓度的深结掺杂源区6，离子注入的能量为70kev，注入杂质为BF2 +，如图3(a)、图3(b)所示。
5、光刻出高浓度掺杂源区图形，以光刻胶2和栅为掩膜进行N+离子注入，形成高浓度的浅结掺杂源区7，离子注入的能量为40kev，注入杂质为As+，如图4(a)、图4(b)所示；进行一次快速高温退火，激活源漏掺杂的杂质。
6、最后进入常规CMOS后道工序，包括淀积钝化层、开接触孔以及金属化等，即可制得所述的复合机制的条形栅隧穿场效应晶体管，如图5所示。
虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。
Claims (9)
1.一种隧穿场效应晶体管，包括一个半导体衬底、一个掺杂源区、一个掺杂漏区、一个控制栅和一个栅介质层，所述掺杂源区和掺杂漏区分别位于控制栅的两侧，其特征在于，掺杂源区由高浓度的浅结掺杂区和低浓度的深结掺杂区两部分组成，上述高浓度的浅结掺杂区和低浓度的深结掺杂区掺有不同掺杂类型的杂质，高浓度的浅结掺杂区的掺杂浓度在1×1020cm-3至1×1021cm-3之间，高浓度的浅结掺杂区的结深小于20nm，低浓度的深结掺杂区的掺杂浓度在1×1018cm-3至1×1019cm-3之间，低浓度的深结掺杂区的结深需大于高浓度的浅结掺杂区结深和耗尽层宽度之和，低浓度的深结掺杂区的掺杂面积相对高浓度的浅结掺杂区的掺杂面积大，控制栅为栅长大于栅宽的条形结构，控制栅的一侧与掺杂漏区连接，控制栅的另一侧向掺杂源区横向延伸，条形栅下无掺杂区域，位于条形栅下的区域仍是沟道区，位于掺杂源区和掺杂漏区之间的有源区仅存在控制栅以下的沟道区，器件的有源区俯视呈“工”字型。
2.如权利要求1所述的隧穿场效应晶体管，其特征在于，所述低浓度的深结掺杂区和掺杂漏区的杂质类型和浓度均一致，靠条形栅自对准同时形成。
3.如权利要求1所述的隧穿场效应晶体管，其特征在于，所述半导体衬底的掺杂浓度在1×1014cm-3至1×1017cm-3之间。
4.如权利要求1所述的隧穿场效应晶体管，其特征在于，所述控制栅的位于掺杂源区和掺杂漏区之间的长度与延伸到掺杂源区的长度比为1：1—1：5，控制栅的栅宽小于2倍的源耗尽层宽度，源耗尽层宽度的范围为25nm-1.5um。
5.权利要求1所述的隧穿场效应晶体管的制备方法，包括以下步骤：
(1)在半导体衬底上通过光刻刻蚀出“工”字型有源区；
(2)生长栅介质层；
(3)淀积控制栅材料，接着光刻和刻蚀，形成条形栅图形；
(4)以控制栅为掩膜，离子注入，自对准形成低浓度掺杂源区和掺杂漏区；
(5)光刻暴露出高浓度掺杂源区，以光刻胶和控制栅为掩膜，离子注入形成另一种掺杂类型的高浓度浅结掺杂源区，然后退火激活源漏掺杂杂质；
(6)最后进入常规CMOS后道工序，包括淀积钝化层、开接触孔以及金属化，即可制得如权利要求1所述的隧穿场效应晶体管。
6.如权利要求5所述的制备方法，其特征在于，所述步骤(1)中的半导体衬底材料选自Si、Ge、SiGe、GaAs或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅或绝缘体上的锗。
7.如权利要求5所述的制备方法，其特征在于，所述步骤(2)中的栅介质层材料选自SiO2、Si3N4和高K栅介质材料。
8.如权利要求5所述的制备方法，其特征在于，所述步骤(2)中的生长栅介质层的方法选自下列方法之一：热氧化、化学气相淀积和物理气相淀积。
9.如权利要求5所述的制备方法，其特征在于，所述步骤(3)中的控制栅材料选自掺杂多晶硅、金属钴，镍以及其他金属或金属硅化物。
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