CN103560144B - 抑制隧穿晶体管泄漏电流的方法及相应的器件和制备方法 - Google Patents

抑制隧穿晶体管泄漏电流的方法及相应的器件和制备方法 Download PDF

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CN103560144B
CN103560144B CN201310571563.1A CN201310571563A CN103560144B CN 103560144 B CN103560144 B CN 103560144B CN 201310571563 A CN201310571563 A CN 201310571563A CN 103560144 B CN103560144 B CN 103560144B
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source region
insulating barrier
source
tunneling transistor
highly doped
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CN103560144A (zh
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黄如
黄芊芊
吴春蕾
王佳鑫
王超
王阳元
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Peking University
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Abstract

本发明公开了一种抑制隧穿晶体管泄漏电流的方法及相应的器件和制备方法，属于CMOS超大集成电路（ULSI）中的场效应晶体管逻辑器件与电路领域。本发明通过在源区和隧穿结下方的体区之间插入绝缘层，而在源区和沟道之间的隧穿结处不插入绝缘层，从而有效抑制了小尺寸TFET器件体内的源漏直接隧穿泄漏电流，并同时能有效改善亚阈值斜率。且相应的器件制备方法与现有的CMOS工艺完全兼容。

Description

抑制隧穿晶体管泄漏电流的方法及相应的器件和制备方法
技术领域
本发明属于CMOS超大集成电路（ULSI）中的场效应晶体管逻辑器件与电路领域，具体涉及一种抑制隧穿晶体管泄漏电流的方法及相应的器件和制备方法。
背景技术
在摩尔定律的驱动下，传统MOSFET的特征尺寸不断缩小，如今已经到进入纳米尺度，随之而来，器件的短沟道效应等负面影响也愈加严重。漏致势垒降低、带带隧穿等效应使得器件关态漏泄电流不断增大，同时，传统MOSFET的亚阈值斜率受到热电势的限制无法随着器件尺寸的缩小而同步减小，由此增加了器件功耗。功耗问题如今已经成为限制器件等比例缩小的最严峻的问题。
为了能将器件应用在超低压低功耗领域，采用新型导通机制而获得超陡亚阈值斜率的器件结构和工艺制备方法已经成为小尺寸器件下大家关注的焦点。近些年来研究者们提出了一种可能的解决方案，就是采用隧穿晶体管（TFET）。TFET不同于传统MOSFET，其源漏掺杂类型相反，利用栅极控制反向偏置的P-I-N结的带带隧穿实现导通，能突破传统MOSFET亚阈值斜率60mV/dec的限制，并且长沟情况下其漏电流非常小。TFET具有低漏电流、低亚阈值斜率、低工作电压和低功耗等诸多优异特性，但由于受源结隧穿几率和隧穿面积的限制，TFET面临着开态电流小的问题，极大限制了TFET器件的应用。另外一方面，对于小尺寸的TFET，当栅长小于约20nm，在体区来自源到漏的直接带带隧穿电流会急剧增大，使得TFET器件的泄漏电流和亚阈值斜率严重退化。采用超薄体SOI衬底的TFET可以一定程度上抑制这种短沟效应，但是由于薄硅膜下埋氧层的存在，散热问题将成为主要问题，自热效应严重，影响器件特性，同时薄硅膜的要求也增加的器件的工艺复杂度。
发明内容
本发明的目的在于提出一种抑制隧穿晶体管泄漏电流的方法及相应的器件和制备方法。该方法通过在源区和隧穿结下方的体区之间插入绝缘层，而在源区和沟道之间的隧穿结处不插入绝缘层，从而有效抑制了小尺寸TFET器件体内的源漏直接隧穿泄漏电流，并同时能有效改善亚阈值斜率。相应的器件制备方法与现有的CMOS工艺完全兼容。
本发明的技术方案如下：
本发明提供的隧穿晶体管包括一个高阻半导体衬底（1）、一个高掺杂源区（10）、一个低掺杂漏区（11），一个栅介质层（3）和一个控制栅（4）。所述高掺杂源区（10）和沟道之间构成隧穿晶体管的隧穿结，隧穿结的厚度h为5-10nm，隧穿结下方设有绝缘层（7），绝缘层（7）位于高掺杂源区（10）和高阻半导体衬底（1）之间，且厚度为50-500nm。所述掺杂源区和掺杂漏区分别位于控制栅的两侧，且掺杂类型相反，掺杂浓度不同。对于N型晶体管，源区为高掺杂P+源区，掺杂浓度为5×1019～1×1021cm-3，漏区为低掺杂N漏区，掺杂浓度为1×1018～1×1019cm-3。对于P型晶体管，源区为高掺杂N+源区，掺杂浓度为5×1019～1×1021cm-3，漏区为较低掺杂P漏区，掺杂浓度为1×1018～1×1019cm-3。所述高阻半导体衬底为轻掺杂，掺杂类型和源区掺杂一致，掺杂浓度小于1×1017cm-3。
上述隧穿晶体管的制备方法，包括以下步骤：
（1）在高阻半导体衬底上通过浅槽隔离定义有源区；
（2）生长栅介质层，淀积控制栅材料和硬掩膜层；
（3）光刻和刻蚀，形成控制栅图形，并利用侧墙工艺，形成器件的一层薄侧墙保护结构，薄侧墙的厚度决定了源结到控制栅边缘的距离，根据设计决定；
（4）光刻暴露出源区，以栅侧墙为保护层，各向异性刻蚀源区的硅，刻蚀深度为隧穿结的厚度h；然后淀积抗氧化材料，再一次光刻暴露出源区，各向异性刻蚀该抗氧化材料，形成单边抗氧化侧墙；
（5）以抗氧化侧墙为保护，进一步各向异性刻蚀源区的硅形成凹陷的硅槽结构；氧化暴露的硅，形成绝缘层；
（6）去掉抗氧化层，然后淀积源材料，过刻源材料层直到沟道表面；
（7）光刻暴露出源区，以光刻胶和控制栅为掩膜，离子注入形成高掺杂源区；然后光刻暴露出漏区，以光刻胶和控制栅为掩膜，离子注入形成另一种掺杂类型的低掺杂漏区，然后快速高温热退火激活源漏掺杂杂质；
（8）最后进入常规CMOS后道工序，包括淀积钝化层、开接触孔以及金属化，即可制得所述的隧穿场效应晶体管，如图8所示。
上述的制备方法中，所述步骤（1）中的半导体衬底材料选自Si、Ge、SiGe、GaAs或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅（SOI）或绝缘体上的锗（GOI）。
上述的制备方法中，所述步骤（2）中的栅介质层材料选自SiO2、Si3N4和高K栅介质材料。
上述的制备方法中，所述步骤（2）中的生长栅介质层的方法选自下列方法之一：常规热氧化、掺氮热氧化、化学气相淀积和物理气相淀积。
上述的制备方法中，所述步骤（2）中的控制栅材料选自掺杂多晶硅、金属钴，镍以及其他金属或金属硅化物。
上述的制备方法中，所述步骤（3）中的薄侧墙材料为SiO2等氧化物。
上述的制备方法中，所述步骤（4）中的抗氧化材料为Si3N4等不易被氧化的材料。
上述的制备方法中，所述步骤（6）中的源漏材料选自多晶硅、Ge、SiGe、GaAs或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体。
本发明抑制隧穿晶体管泄漏电流的方法具体为，在隧穿晶体管的的隧穿结处下方设有绝缘层，绝缘层位于源区和沟道下方的体区之间，利用绝缘层抑制隧穿晶体管的源漏直接隧穿的泄漏电流。
本发明的技术效果如下：
一、本发明的方法通过在隧穿结下方引入绝缘层，可以有效地降低小尺寸TFET器件的源到漏的直接带带隧穿几率，从而抑制隧穿晶体管的隧穿泄漏电流，获得较低的关态电流。且绝缘层的电场集边效应使得该器件发生带带隧穿时能获得比传统TFET更高的电场，从而提高TFET器件的亚阈特性。
二、利用本发明的方法制备的隧穿晶体管具有高掺杂源和较低掺杂漏，源区掺杂浓度为5×1019～1×1021cm-3，漏区掺杂浓度为1×1018～1×1019cm-3，且源和漏的掺杂类型相反，衬底为轻掺杂且掺杂类型和源区一致，掺杂浓度小于1×1017cm-3。该晶体管利用隧穿结处的带带隧穿机制导通，能突破MOSFET器件的亚阈值斜率的限制，获得比常规TFET器件和MOSFET器件更陡直的亚阈特性。低浓度的漏区掺杂也能有效降低漏结处的带带隧穿几率，抑制漏结处的隧穿电流，从而抑制器件的双极导通效应。另外，由于本发明的隧穿晶体管的半导体衬底为轻掺杂，且掺杂类型和源相同，因此是一种三端器件，衬底直接通过源结引出了，相比四端器件的MOSFET能获得更小的版图面积和更高的集成度。再有，相比常规SOITFET结构，本发明的隧穿晶体管能有效解决SOI结构的散热问题，抑制自热效应。
三、本发明的方法相应的隧穿晶体管的制备方法与现有的CMOS工艺完全兼容。隧穿结厚度由刻蚀工艺决定，相比SOITFET结构，能缓解对薄膜工艺的要求。且制备方法中，最后淀积源材料层可以方便地实现TFET异质结的设计，并且可以准确地控制TFET异质结所处的位置。异质结TFET相比同质结TFET有更陡的隧穿结，更小的隧穿势垒宽度，因此能实现更高的开态电流和更低的亚阈值斜率。
简而言之，本发明的方法能有效地抑制小尺寸下TFET的源漏直接隧穿泄漏电流，另一方面同时也能获得了更大的隧穿电场，提高了TFET器件的亚阈特性。利用该方法制备的隧穿晶体管还能抑制器件的双极导通效应，拥有更小的版图面积和更高的集成度，且制备工艺与现有的CMOS工艺完全兼容，有望在低功耗领域得到采用，有较高的实用价值。
附图说明
图1是在高阻半导体衬底上形成浅槽隔离的工艺步骤示意图；
图2是生长栅介质层并形成了控制栅和薄侧墙后的器件示意图；
图3是在源区刻蚀出h厚度的硅后并形成单边抗氧化侧墙的器件示意图；
图4是刻蚀出源区所在的凹槽并氧化出“L”形绝缘层后的器件示意图；
图5是淀积源材料后的器件示意图；
图6是光刻暴露出源区并离子注入形成高掺杂浓度源区后的器件示意图；
图7是光刻暴露出漏区并离子注入形成另一种掺杂类型的较低掺杂浓度的漏区后的器件示意图；
图8是完成淀积钝化层、开接触孔以及金属化的隧穿晶体管的示意图。
图中：
1——高阻半导体衬底2——有源区隔离层
3——栅介质层4——控制栅
5——栅硬掩膜层6——抗氧化侧墙
7——绝缘层8——源材料
9——光刻胶10——高掺杂源区
11——较低掺杂漏区12——钝化隔离层
13——金属层
具体实施方式
下面通过实例对本发明做进一步说明。需要注意的是，公布实施例的目的在于帮助进一步理解本发明，但是本领域的技术人员可以理解：在不脱离本发明及所附权利要求的精神和范围内，各种替换和修改都是可能的。因此，本发明不应局限于实施例所公开的内容，本发明要求保护的范围以权利要求书界定的范围为准。
本发明制备方法的一具体实例包括图1至图8所示的工艺步骤：
1、选取晶向为（100）的体硅硅片硅衬底1上采用浅槽隔离技术制作有源区隔离层2，衬底掺杂浓度为轻掺杂，如图1所示。
2、然后热生长一层栅介质层3，栅介质层为SiO2，厚度为1-5nm；淀积栅电极层4和栅硬掩膜层5，栅电极层为掺杂多晶硅层，厚度为150-300nm，硬掩膜层为SiO2，厚度为100-200nm；光刻出控制栅图形，刻蚀栅硬掩膜层5和栅电极层4直到栅介质层3；用LPCVD的方法淀积一层薄SiO2形成对栅结构的覆盖，厚度为30nm，之后，利用干法刻蚀可出带薄侧墙保护的栅结构，如图2所示。
3、光刻暴露出源区图形，以栅侧墙为保护层，各向异性刻蚀源区的硅，刻蚀深度为10nm，去除光刻胶；然后淀积Si3N4，厚度为50-100nm，再一次光刻暴露出源区，各向异性刻蚀该Si3N4，形成单边抗氧化侧墙6，去除光刻胶，如图3所示。
4、以Si3N4为保护，进一步各向异性刻蚀源区的硅形成凹陷的硅槽结构，刻蚀深度为20-100nm；然后氧化暴露出来的硅，形成SiO2层，即绝缘层7，该SiO2层的厚度为50-100nm，如图4所示。
5、LPCVD一层厚的多晶硅材料8，如图5所示。以栅区顶端的硬掩膜为停止层，化学机械抛光（CMP）多晶硅，过刻多晶硅直到沟道表面，形成多晶硅源结构。
6、光刻暴露出源区，以光刻胶9和栅区为掩膜进行P+离子注入，形成高掺杂源区10，离子注入的能量为40keV，注入杂质为BF2 +，如图6所示。
7、光刻暴露出漏区，以光刻胶9和栅区为掩膜进行N离子注入，形成较低浓度掺杂的漏区11，离子注入的能量为50keV，注入杂质为As+，如图7所示；进行一次快速高温退火，激活源漏掺杂的杂质。
8、最后进入常规CMOS后道工序，包括淀积钝化层12、开接触孔以及金属化形成金属层13，即可制得所述的隧穿晶体管，如图8所示。
虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (7)

1.一种隧穿晶体管，包括一个半导体衬底(1)、一个高掺杂源区(10)、一个低掺杂漏区(11)，一个栅介质层(3)和一个控制栅(4)，所述高掺杂源区(10)和沟道之间构成隧穿晶体管的隧穿结，隧穿结的厚度h为5-10nm，其特征在于，隧穿结下方设有绝缘层(7)，绝缘层(7)位于高掺杂源区(10)和半导体衬底(1)之间，绝缘层(7)的厚度为50-500nm，所述高掺杂源区(10)和低掺杂漏区(11)掺杂类型相反，对于N型晶体管，高掺杂P+源区的掺杂浓度为5×1019～1×1021cm-3，低掺杂N漏区的掺杂浓度为1×1018～1×1019cm-3；对于P型晶体管，高掺杂N+源区的掺杂浓度为5×1019～1×1021cm-3，低掺杂P漏区的掺杂浓度为1×1018～1×1019cm-3，所述半导体衬底(1)为轻掺杂，掺杂类型和高掺杂源区(10)掺杂一致，掺杂浓度小于1×1017cm-3。
2.一种抑制隧穿晶体管泄漏电流的方法，隧穿晶体管的源区和沟道的界面处为隧穿结，其特征在于，隧穿结下方设有绝缘层，绝缘层位于高掺杂源区和半导体衬底之间，绝缘层的厚度为50-500nm，利用该绝缘层抑制隧穿晶体管的源漏直接隧穿的泄漏电流。
3.制备如权利要求1所述的隧穿晶体管的方法，包括以下步骤：
(1)在半导体衬底上通过浅槽隔离定义有源区；
(2)生长栅介质层，淀积控制栅材料和硬掩膜层；
(3)光刻和刻蚀，形成控制栅图形，并利用侧墙工艺，形成器件的一层薄侧墙保护结构，薄侧墙的厚度决定了源结到控制栅边缘的距离；
(4)光刻暴露出源区，以栅侧墙为保护层，各向异性刻蚀源区的硅，刻蚀深度为隧穿结的厚度h；然后淀积抗氧化材料，再一次光刻暴露出源区，各向异性刻蚀该抗氧化材料，形成单边抗氧化侧墙；
(5)以抗氧化侧墙为保护，进一步各向异性刻蚀源区的硅形成凹陷的硅槽结构；氧化暴露的硅，形成绝缘层；
(6)去掉抗氧化层，然后淀积源材料，过刻源材料层直到沟道表面；
(7)光刻暴露出源区，以光刻胶和控制栅为掩膜，离子注入形成高掺杂源区；然后光刻暴露出漏区，以光刻胶和控制栅为掩膜，离子注入形成另一种掺杂类型的较低掺杂漏区，然后快速退火激活源漏掺杂杂质；
(8)最后进入CMOS后道工序，即可制得如权利要求1所述的隧穿晶体管。
4.如权利要求3所述的制备方法，其特征在于，所述步骤(1)中的半导体衬底材料为Si、Ge、SiGe、GaAs、绝缘体上的硅或绝缘体上的锗。
5.如权利要求3所述的制备方法，其特征在于，所述步骤(2)中的栅介质层材料为SiO2、Si3N4或高K栅介质材料。
6.如权利要求3所述的制备方法，其特征在于，所述步骤(2)中的控制栅材料为掺杂多晶硅、金属钴或镍。
7.如权利要求3所述的制备方法，其特征在于，所述步骤(6)中的源材料为多晶硅、Ge、SiGe或GaAs。
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