CN103594376B - 一种结调制型隧穿场效应晶体管及其制备方法 - Google Patents

一种结调制型隧穿场效应晶体管及其制备方法 Download PDF

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CN103594376B
CN103594376B CN201310552567.5A CN201310552567A CN103594376B CN 103594376 B CN103594376 B CN 103594376B CN 201310552567 A CN201310552567 A CN 201310552567A CN 103594376 B CN103594376 B CN 103594376B
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channel region
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CN103594376A (zh
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黄如
黄芊芊
吴春蕾
王佳鑫
詹瞻
王阳元
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Peking University
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Abstract

本发明公开了一种结调制型隧穿场效应晶体管及其制备方法，属于CMOS超大集成电路（ULSI）中的场效应晶体管逻辑器件与电路领域。该隧穿场效应晶体管利用垂直沟道区三面包围的高掺杂源区提供的PN结能有效耗尽沟道区，使得栅下表面沟道能带提高，当器件发生带隧穿时能获得比传统TFET更陡的能带和更窄的隧穿势垒宽度，等效实现了陡直的隧穿结掺杂浓度梯度的效果，从而大幅提高传统TFET的亚阈特性并同时提升器件的导通电流。本发明在与现有的CMOS工艺兼容的条件下，一方面有效地抑制了器件的双极导通效应，同时能抑制小尺寸下源结边角处的寄生隧穿电流，能等效实现陡直的源结掺杂浓度的效果。

Description

一种结调制型隧穿场效应晶体管及其制备方法
技术领域
本发明属于CMOS超大集成电路（ULSI）中的场效应晶体管逻辑器件与电路领域，具体涉及一种结调制型隧穿场效应晶体管及其制备方法。
背景技术
在摩尔定律的驱动下，传统MOSFET的特征尺寸不断缩小，如今已经到进入纳米尺度，随之而来，器件的短沟道效应等负面影响也愈加严重。漏致势垒降低、带带隧穿等效应使得器件关态漏泄电流不断增大，同时，传统MOSFET的亚阈值斜率受到热电势的限制无法随着器件尺寸的缩小而同步减小，由此增加了器件功耗。功耗问题如今已经成为限制器件等比例缩小的最严峻的问题。
为了能将器件应用在超低压低功耗领域，采用新型导通机制而获得超陡亚阈值斜率的器件结构和工艺制备方法已经成为小尺寸器件下大家关注的焦点。近些年来研究者们提出了一种可能的解决方案，就是采用隧穿场效应晶体管（TFET）。TFET不同于传统MOSFET，其源漏掺杂类型相反，利用栅极控制反向偏置的P-I-N结的带带隧穿实现导通，能突破传统MOSFET亚阈值斜率60mV/dec的限制，并且其漏电流非常小。TFET具有低漏电流、低亚阈值斜率、低工作电压和低功耗等诸多优异特性，但由于受源结隧穿几率和隧穿面积的限制，TFET面临着开态电流小的问题，远远比不上传统MOSFET器件，极大限制了TFET器件的应用。另外，具有陡直亚阈值斜率的TFET器件在实验上也较难实现，这是因为实验较难在源结处实现陡直的掺杂浓度梯度以致器件开启时隧穿结处的电场不够大，这会导致TFET的亚阈值斜率相对理论值退化。因此，如何在源结实现陡直的掺杂浓度梯度而获得超低的亚阈值斜率，也成为了TFET器件的另一个重要问题。
发明内容
本发明的目的在于提出一种结调制型隧穿场效应晶体管及其制备方法。在与现有的CMOS工艺兼容的条件下，该器件能等效实现陡直的源结掺杂浓度的效果，更加显著地优化TFET器件的亚阈值斜率，并同时提升器件的导通电流，且栅和漏之间存在栅未覆盖区，一方面有效地抑制了器件的双极导通效应，同时能抑制小尺寸下源结边角处的寄生隧穿电流。
本发明的技术方案如下：
本发明隧穿场效应晶体管包括一个半导体衬底（1）、一个垂直沟道区（2）、一个高掺杂源区（4）、一个低掺杂漏区（8）、一个栅介质层（5）和一个控制栅（6），以及与控制栅（6）相连的栅电极（9），与高掺杂源区（4）连接的源电极（10）和与低掺杂漏区（8）连接的漏电极（11），其特征在于，半导体衬底（1）的上方为垂直沟道区（2），垂直沟道区（2）呈长方体状；垂直沟道区（2）的下方一侧为栅介质层（5）和控制栅（6），其它侧面为高掺杂源区（4），低掺杂漏区（8）位于垂直沟道区（2）的顶端，低掺杂漏区（8）和控制栅（6）之间为隔离区（7），低掺杂漏区（8）和高掺杂源区（4）掺有不同掺杂类型的杂质，且低掺杂漏区（8）的掺杂浓度在5×1017cm-3至1×1019cm-3之间，高掺杂源区（4）的掺杂浓度在1×1019cm-3至1×1021cm-3之间。半导体衬底（1）的掺杂浓度在1×1014cm-3至1×1017cm-3之间。长方体状的垂直沟道区（2）的长和宽相等，且小于一倍的源耗尽层宽度，源耗尽层宽度的范围为25nm-1.5um，垂直沟道区（2）的高大于长和宽，垂直沟道区（2）的高度和长宽的比例为1.5:1-5:1。低掺杂漏区（8）和控制栅（6）之间的垂直距离为10nm-1μm。
上述隧穿场效应晶体管的制备方法，包括以下步骤：
（1）在半导体衬底上淀积硬掩膜层，并光刻刻蚀，定义垂直沟道区图形；在硬掩膜的保护下，深刻蚀形成垂直的沟道区；
（2）在硬掩膜的保护下，离子注入形成环绕垂直沟道区四面的高掺杂源区；光刻仅暴露出一面高掺杂源区，并刻蚀，刻蚀深度大于离子注入深度，使得只剩下三面包围的高掺杂源区；
（3）生长栅介质层，并淀积控制栅材料；
（4）接着淀积隔离层材料并回刻直至高掺杂源区上方的多晶硅，在隔离层的保护下腐蚀多晶硅，仅留下被隔离层覆盖的多晶硅层作为垂直控制栅；
（5）继续淀积隔离层，淀积厚度决定了漏和栅之间栅未覆盖区的长度；在隔离层的保护下，离子注入形成另一种掺杂类型的较低掺杂漏区，然后快速高温热退火激活掺杂杂质；
（6）最后进入常规CMOS后道工序，包括继续淀积隔离层、开接触孔以及金属化，即可制得所述的隧穿场效应晶体管，如图1所示。
上述的制备方法中，所述步骤（1）中的半导体衬底材料选自Si、Ge、SiGe、GaAs或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅（SOI）或绝缘体上的锗（GOI）。
上述的制备方法中，所述步骤（3）中的栅介质层材料选自SiO2、Si3N4和高K栅介质材料。
上述的制备方法中，所述步骤（3）中的生长栅介质层的方法选自下列方法之一：常规热氧化、掺氮热氧化、化学气相淀积和物理气相淀积。
上述的制备方法中，所述步骤（3）中的控制栅材料选自掺杂多晶硅、金属钴，镍以及其他金属或金属硅化物。
本发明的技术效果如下：
一、本发明隧穿场效应晶体管的垂直沟道区三面包围的高掺杂源区提供的PN结能有效耗尽沟道区，使得栅下表面沟道能带提高，因此当该器件发生带带隧穿时能获得比传统TFET更陡的能带和更窄的隧穿势垒宽度，等效实现了陡直的隧穿结掺杂浓度梯度的效果，从而大幅提高传统TFET的亚阈特性。同时相比平面条形栅的结耗尽型隧穿场效应晶体管，由于平面结构只能靠两边PN结耗尽，因此本发明的三面包围结构能更加有效调制隧穿结，获得更加陡直的亚阈特性。
二、在不增加有源区面积的前提下，本发明的垂直沟道区的设计能有效提高隧穿面积，隧穿面积由高掺杂源区和栅的交界面决定，如图1a中的虚线框出的区域所示。隧穿面积的增加有利于进一步提高器件的开态电流。
三、本发明采用了短栅的设计，即栅电极部分覆盖沟道区，在栅和漏之间存在一定间距的未覆盖区域。这种设计不仅可以有效抑制漏结处的隧穿，即常规TFET中的双极导通效应，还能有效降低栅电极对未覆盖区的影响，因此可以抑制小尺寸下寄生隧穿结的隧穿，寄生隧穿结发生的区域如图1a中B点所示位置。因此能降低器件开启时的亚阈值斜率。另外，漏区掺杂浓度较低也能进一步抑制双极导通效应。
四、该器件制备工艺简单，制备方法与传统的MOSFET工艺完全兼容。
简而言之，该器件结构采用垂直沟道区增加了器件的隧穿面积，利用高掺杂源区三面包围沟道区的设计有效调制了源端隧穿结，并且抑制了双极导通效应和小尺寸下的寄生隧穿结的隧穿，提高了TFET器件的开态电流和亚阈特性且制备方法简单。与现有的TFET相比，在同样的有源区尺寸下，该器件可以得到更高的导通电流和更陡直的亚阈值斜率,且能保持低的泄漏电流，有望在低功耗领域得到采用，有较高的实用价值。
附图说明
图1a是本发明的结调制型垂直隧穿场效应晶体管的剖面示意图，图1b是沿图1a中AA’方向的器件俯视图，其中箭头所示为隧穿方向；
图2a是刻蚀形成垂直沟道之后，在硬掩膜的保护下离子注入形成高掺杂漏区后的器件剖面图，图2b是相应的器件俯视图；
图3a是光刻仅暴露出垂直沟道区的一面，并刻蚀形成凹槽后的器件剖面图，图3b是相应的器件俯视图；
图4a是生长栅介质层，并淀积控制栅材料后的器件剖面图，图4b是相应的器件俯视图；
图5a是淀积隔离层并回刻，腐蚀未被保护的多晶硅后的器件剖面图，图5b是相应的器件俯视图；
图6a是继续淀积隔离层，并离子注入形成另一种掺杂类型的较低掺杂漏区后的器件剖面图，图6b是相应的器件俯视图；
图7是继续淀积隔离层、开接触孔以及形成金属引出后的结调制型垂直隧穿场效应晶体管剖面图；
图中：
1——半导体衬底2——垂直沟道区
3——硬掩膜层4——高掺杂源区
5——栅介质层6——控制栅
7——隔离层8——低掺杂漏区
9——栅电极10——源电极
11——漏电极
具体实施方式
下面通过实例对本发明做进一步说明。需要注意的是，公布实施例的目的在于帮助进一步理解本发明，但是本领域的技术人员可以理解：在不脱离本发明及所附权利要求的精神和范围内，各种替换和修改都是可能的。因此，本发明不应局限于实施例所公开的内容，本发明要求保护的范围以权利要求书界定的范围为准。
本发明制备方法的一具体实例包括图2至图7所示的工艺步骤：
1、在晶向为（100）的体硅硅片硅衬底1上淀积硬掩膜层3，硬掩膜层为Si3N4，厚度为300nm，衬底掺杂浓度为轻掺杂；然后光刻刻蚀，定义出垂直沟道区2所在的正方形图形，长宽均为50nm；在硬掩膜的保护下，深刻蚀硅材料形成垂直的沟道区2；
2、在硬掩膜的保护下，进行P+离子注入，形成环绕垂直沟道区四面的高掺杂源区4，离子注入的能量为40keV，注入杂质为BF2 +，如图2a、2b所示；
3、光刻仅暴露出环绕垂直沟道区一面的高掺杂源区，并刻蚀硅，刻蚀深度为500nm，使得只剩下三面包围的高掺杂源区，去除光刻胶，如图3a、3b所示；
4、热生长一层栅介质层5，栅介质层为SiO2，厚度为1～5nm；淀积栅材料，栅材料为掺杂多晶硅层，厚度为150～300nm，如图4a、4b所示。
5、淀积隔离层7，隔离层为SiO2，厚度为1μm，回刻，停止层为高掺杂源区上方的多晶硅；然后在隔离层7的保护下各项同性腐蚀多晶硅层，仅留下被隔离层覆盖的多晶硅层作为垂直控制栅6，如图5a、5b所示。
6、继续淀积SiO2，淀积厚度为50nm，然后进行N离子注入，形成另一种掺杂类型的低掺杂漏区8，离子注入的能量为50keV，注入杂质为As +，如图6a、6b所示；进行一次快速高温退火，激活源漏掺杂的杂质。
7、最后进入常规CMOS后道工序，包括淀积钝化层、开接触孔以及金属化，即可制得所述的结调制型垂直隧穿场效应晶体管，如图7所示。
虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (9)

1.一种隧穿场效应晶体管，包括一个半导体衬底(1)、一个垂直沟道区(2)、一个高掺杂源区(4)、一个低掺杂漏区(8)、一个栅介质层(5)和一个控制栅(6)，以及与控制栅(6)相连的栅电极(9)，与高掺杂源区(4)连接的源电极(10)和与低掺杂漏区(8)连接的漏电极(11)，其特征在于，半导体衬底(1)的上方为垂直沟道区(2)，垂直沟道区(2)呈长方体状；垂直沟道区(2)的下方一侧为栅介质层(5)和控制栅(6)，其它侧面为高掺杂源区(4)，低掺杂漏区(8)位于垂直沟道区(2)的顶端，低掺杂漏区(8)和控制栅(6)之间为隔离区(7)，低掺杂漏区(8)和高掺杂源区(4)掺有不同掺杂类型的杂质，且低掺杂漏区(8)的掺杂浓度在5×1017cm-3至1×1019cm-3之间，高掺杂源区(4)的掺杂浓度在1×1019cm-3至1×1021cm-3之间。
2.如权利要求1所述的隧穿场效应晶体管，其特征在于，半导体衬底(1)的掺杂浓度在1×1014cm-3至1×1017cm-3之间。
3.如权利要求1所述的隧穿场效应晶体管，其特征在于，垂直沟道区(2)的长和宽相等，且小于一倍的源耗尽层宽度，源耗尽层宽度的范围为25nm-1.5um，垂直沟道区(2)的高大于垂直沟道区(2)的长和宽，垂直沟道区(2)的高度和宽的比例为1.5:1-5:1。
4.如权利要求1所述的隧穿场效应晶体管，其特征在于，低掺杂漏区(8)和控制栅(6)之间的垂直距离为10nm-1μm。
5.一种制备权利要求1所述的隧穿场效应晶体管的方法，包括以下步骤：
(1)在半导体衬底上淀积硬掩膜层，并光刻刻蚀，定义垂直沟道区图形；在硬掩膜的保护下，深刻蚀形成垂直的沟道区；
(2)在硬掩膜的保护下，离子注入形成环绕垂直沟道区四面的高掺杂源区；光刻仅暴露出一面高掺杂源区，并刻蚀，刻蚀深度大于离子注入深度，使得只剩下三面包围的高掺杂源区；
(3)生长栅介质层，并淀积控制栅材料；
(4)淀积隔离层材料并回刻直至高掺杂源区上方的多晶硅，在隔离层的保护下腐蚀多晶硅，仅留下被隔离层覆盖的多晶硅层作为垂直控制栅；
(5)继续淀积隔离层，淀积厚度决定了漏和栅之间栅未覆盖区的长度；在隔离层的保护下，离子注入形成另一种掺杂类型的低掺杂漏区，然后快速热退火激活掺杂杂质；
(6)最后进入CMOS后道工序，包括继续淀积隔离层、开接触孔以及金属化，即可制得如权利要求1所述的隧穿场效应晶体管。
6.如权利要求5所述的制备方法，其特征在于，所述步骤(1)中的半导体衬底材料选自Si、Ge、SiGe、GaAs或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅或绝缘体上的锗。
7.如权利要求5所述的制备方法，其特征在于，所述步骤(3)中的栅介质层材料选自SiO2、Si3N4和高K栅介质材料中的一种。
8.如权利要求5所述的制备方法，其特征在于，所述步骤(3)中的生长栅介质层的方法选自下列方法之一：热氧化、化学气相淀积和物理气相淀积。
9.如权利要求5所述的制备方法，其特征在于，所述步骤(3)中的控制栅材料选自掺杂多晶硅、金属钴或镍。
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