WO2015066971A1 - 一种结调制型隧穿场效应晶体管及其制备方法 - Google Patents

一种结调制型隧穿场效应晶体管及其制备方法 Download PDF

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WO2015066971A1
WO2015066971A1 PCT/CN2014/070352 CN2014070352W WO2015066971A1 WO 2015066971 A1 WO2015066971 A1 WO 2015066971A1 CN 2014070352 W CN2014070352 W CN 2014070352W WO 2015066971 A1 WO2015066971 A1 WO 2015066971A1
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region
vertical channel
effect transistor
field effect
channel region
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PCT/CN2014/070352
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English (en)
French (fr)
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黄如
黄芊芊
吴春蕾
王佳鑫
詹瞻
王阳元
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北京大学
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Priority to US14/787,262 priority Critical patent/US20160079400A1/en
Publication of WO2015066971A1 publication Critical patent/WO2015066971A1/zh

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Definitions

  • TECHNICAL FIELD The present invention relates to field effect transistor logic devices and circuits in CMOS Very Large Integrated Circuits (ULSI), and more particularly to a junction modulation tunneling field effect transistor and a method of fabricating the same.
  • ULSI Very Large Integrated Circuits
  • TFETs tunneling field effect transistors
  • TFETs have many excellent characteristics such as low leakage current, low subthreshold slope, low operating voltage and low power consumption.
  • TFETs face the problem of small on-state current.
  • MOSFET devices the application of TFET devices is greatly limited.
  • TFET devices with steep subthreshold slopes are also experimentally difficult to implement because it is difficult to achieve a steep doping concentration gradient at the source junction so that the electric field at the tunnel junction is not large enough when the device is turned on. This causes the subthreshold slope of the TFET to degrade relative to the theoretical value.
  • An object of the present invention is to provide a junction modulation tunneling field effect transistor and a method of fabricating the same.
  • the device is equivalent to achieve a steep source junction doping concentration under conditions compatible with existing CMOS processes, significantly optimizing the subthreshold slope of the TFET device while simultaneously increasing the on current of the device, and There is a gate uncovered region between the gate and the drain, which effectively suppresses the bipolar conduction effect of the device and suppresses the parasitic tunneling current at the source junction angle of the small size.
  • the tunneling field effect transistor of the present invention comprises a semiconductor substrate (1), a vertical channel region (2), a highly doped source region (4), and a low doped drain region (8). a gate dielectric layer (5) and a control gate (6), and a gate electrode (9) connected to the control gate (6), a source electrode (10) connected to the highly doped source region (4), and a low-doped drain region (8) connected to the drain electrode (11), characterized in that the semiconductor substrate (1) is above the vertical channel region (2), and the vertical channel region (2) is in the shape of a rectangular parallelepiped;
  • the lower side of the track region (2) is the gate dielectric layer (5) and the control gate (6), the other side is the highly doped source region (4), and the low doped drain region (8) is located in the vertical channel region (2).
  • the low-doped drain region (8) and the control gate (6) are isolated regions (7), the low-doped drain region (8) and the highly doped source region (4) are doped with different doping types. impurity doping concentration, and a low-doped drain region (8) between 5xl0 17 cm_ 3 to lxl0 19 cm_ 3, the doping concentration of the high doped source region (4) at lxl0 19 cm_ 3 to lxl0 21 cm_ Between 3 The doping concentration of the semiconductor substrate (1) is between lxl0 14 C m- 3 to lxl0 17 cm- 3 .
  • the rectangular parallelepiped vertical channel region (2) has the same length and width, and is less than one times the source depletion layer width, the source depletion layer width ranges from 25 ⁇ to 1.5 ⁇ , and the vertical channel region (2) has a height greater than The length and width of the vertical channel region (2) are 1.5:1-5:1.
  • the vertical distance between the low doped drain region (8) and the control gate (6) is 10 ⁇ - 1 ⁇ .
  • the method for preparing the tunneling field effect transistor includes the following steps:
  • ion implantation forms a highly doped source region surrounding all four sides of the vertical channel region; photolithography exposes only one highly doped source region and etches, and the etching depth is greater than the ion implantation depth , leaving only the highly doped source region surrounded by three sides;
  • the semiconductor substrate material in the step (1) is selected from the group consisting of Si, Ge, SiGe, GaAs or other II-VI, III-V and IV-IV binary or ternary compound semiconductors, Silicon on insulator (SOI) or germanium on insulator (GOI).
  • the gate dielectric layer material in the step (3) is selected from the group consisting of SiO 2 , Si 3 N 4 and high-k gate dielectric materials.
  • the method of growing the gate dielectric layer in the step (3) is selected from one of the following methods: conventional thermal oxidation, nitrogen-doped thermal oxidation, chemical vapor deposition, and physical vapor deposition.
  • the control gate material in the step (3) is selected from the group consisting of doped polysilicon, metallic cobalt, nickel, and other metals or metal silicides.
  • the technical effects of the present invention are as follows: 1.
  • the PN junction provided by the highly doped source region surrounded by the three sides of the vertical channel region of the tunneling field effect transistor of the present invention can effectively deplete the channel region, so that the channel energy band of the lower surface of the gate is improved.
  • the device has band tunneling, a steeper energy band and a narrower tunneling barrier width than the conventional TFET can be obtained, and the effect of the steep tunneling junction doping concentration gradient is equivalently realized, thereby greatly Improve the subthreshold characteristics of conventional TFETs.
  • the three-sided enclosing structure of the invention can more effectively modulate the tunneling junction and obtain a more steep Subthreshold characteristics. 2.
  • the design of the vertical channel region of the present invention can effectively increase the tunneling area without increasing the area of the active region.
  • the tunneling area is determined by the interface between the highly doped source region and the gate, as shown in FIG. The area enclosed by the dotted line is shown.
  • the increase in tunneling area is beneficial to further increase the on-state current of the device.
  • the present invention employs a short gate design in which the gate electrode partially covers the channel region, and there is a gap between the gate and the drain. This design can not only effectively suppress the tunneling at the drain junction, that is, the bipolar conduction effect in the conventional TFET, but also effectively reduce the influence of the gate electrode on the uncovered region, thereby suppressing the tunneling of the small-sized parasitic tunneling junction.
  • the area where the parasitic tunneling junction occurs is shown in the position shown by point B in la.
  • the device preparation process is simple, and the preparation method is fully compatible with the conventional MOSFET process.
  • the device structure uses a vertical channel region to increase the tunneling area of the device.
  • the design of the channel region surrounded by three sides of the highly doped source region effectively modulates the source tunneling junction and suppresses bipolar conduction.
  • the effect and tunneling of the parasitic tunneling junction at a small size enhances the on-state current and subthreshold characteristics of the TFET device and is simple to fabricate.
  • the device can achieve higher on-current and steeper subthreshold slope under the same active area size, and can maintain low leakage current, which is expected to be in the low power field. It has been adopted and has high practical value.
  • FIG. 1a is a cross-sectional view of a junction modulation type vertical tunneling field effect transistor of the present invention
  • FIG. 1b is a plan view of the device along the AA' direction of FIG. 1a, wherein the arrow indicates a tunneling direction
  • FIG. 2a is an etching to form a vertical trench. After the circuit, under the protection of the hard mask, ion implantation is performed to form a high-doped drain region, and FIG. 2b is a top view of the corresponding device
  • FIG. 3a is a surface in which photolithography exposes only the vertical channel region and is etched.
  • FIG. 3b is a cross-sectional view of the device after forming the recess
  • FIG. 3b is a top view of the corresponding device
  • FIG. 4a is a cross-sectional view of the device after growing the gate dielectric layer and depositing the control gate material
  • FIG. 4b is a top view of the corresponding device;
  • Figure 5a is a cross-sectional view of the device after depositing the isolation layer and etching back, etching the unprotected polysilicon
  • Figure 5b is a top view of the corresponding device
  • Figure 6a is the continued deposition of the isolation layer and ion implantation to form another doping type
  • FIG. 6b is a cross-sectional view of the device after the lower doped drain region
  • FIG. 6b is a top view of the corresponding device
  • FIG. 7 is a cross-sectional view of the junction-modulated vertical tunneling field effect transistor after the deposition of the isolation layer, the opening of the contact hole, and the formation of the metal extraction. ;
  • a hard mask layer 3 on the bulk silicon silicon substrate 1 having a crystal orientation of (100), the hard mask layer being Si 3 N 4 , having a thickness of 300 nm, and the substrate doping concentration is lightly doped Then lithographically etching, defining a square pattern in which the vertical channel region 2 is located, each having a length and a width of 50 nm; under the protection of the hard mask, the silicon material is deeply etched to form a vertical channel region 2;
  • P + ion implantation is performed to form a highly doped source region 4 surrounding the four sides of the vertical channel region, the energy of ion implantation is 40 keV, and the impurity is BF 2 + , as shown in Fig. 2a, 2b. 3.
  • the lithography exposes only the highly doped source region surrounding one side of the vertical channel region, and etches the silicon to an etch depth of
  • a gate dielectric layer 5 is thermally grown, the gate dielectric layer is Si0 2 , and the thickness is 1-5 nm ; the gate material is deposited, the gate material is doped polysilicon layer, and the thickness is 150-300 nm, as shown in FIGS. 4a and 4b. .
  • the isolation layer is Si0 2 , the thickness is ⁇ , etch back, the stop layer is polysilicon above the highly doped source region; then the isotropic etched polysilicon layer under the protection of the isolation layer 7, leaving only The polysilicon layer covered by the isolation layer is used as the vertical control gate 6, as shown in Figs. 5a, 5b.
  • CMOS post-process including depositing a passivation layer, opening a contact hole, and metallization, can be performed to obtain the junction-modulated vertical tunneling field effect transistor, as shown in FIG.

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Abstract

本发明公开了一种结调制型隧穿场效应晶体管及其制备方法,属于CMOS超大集成电路(ULSI)中的场效应晶体管逻辑器件与电路领域。该隧穿场效应晶体管利用垂直沟道区三面包围的高掺杂源区提供的PN结能有效耗尽沟道区,使得栅下表面沟道能带提高,当器件发生带带隧穿时能获得比传统TFET更陡的能带和更窄的隧穿势垒宽度,等效实现了陡直的隧穿结掺杂浓度梯度的效果,从而大幅提高传统TFET的亚阈特性并同时提升器件的导通电流。本发明在与现有的CMOS工艺兼容的条件下,一方面有效地抑制了器件的双极导通效应,同时能抑制小尺寸下源结边角处的寄生隧穿电流,能等效实现陡直的源结掺杂浓度的效果。

Description

一种结调制型隧穿场效应晶体管及其制备方法 相关申请的交叉引用
本申请要求于 2013年 11月 8日提交的中国专利申请(201310552567.5 )的优先 权, 其全部内容通过引用合并于此。 技术领域 本发明属于 CMOS超大集成电路(ULSI)中的场效应晶体管逻辑器件与电路领 域, 具体涉及一种结调制型隧穿场效应晶体管及其制备方法。 背景技术
在摩尔定律的驱动下, 传统 MOSFET的特征尺寸不断缩小, 如今已经到进入纳 米尺度, 随之而来, 器件的短沟道效应等负面影响也愈加严重。 漏致势垒降低、 带带 隧穿等效应使得器件关态漏泄电流不断增大, 同时, 传统 MOSFET的亚阈值斜率受 至 IJ热电势的限制无法随着器件尺寸的缩小而同步减小, 由此增加了器件功耗。功耗问 题如今已经成为限制器件等比例缩小的最严峻的问题。 为了能将器件应用在超低压低功耗领域, 采用新型导通机制而获得超陡亚阈值 斜率的器件结构和工艺制备方法已经成为小尺寸器件下大家关注的焦点。近些年来研 究者们提出了一种可能的解决方案, 就是采用隧穿场效应晶体管 (TFET)。 TFET不 同于传统 MOSFET, 其源漏掺杂类型相反, 利用栅极控制反向偏置的 P-I-N结的带带 隧穿实现导通,能突破传统 MOSFET亚阈值斜率 60mV/dec的限制,并且其漏电流非 常小。 TFET具有低漏电流、 低亚阈值斜率、 低工作电压和低功耗等诸多优异特性, 但由于受源结隧穿几率和隧穿面积的限制, TFET面临着开态电流小的问题, 远远比 不上传统 MOSFET器件, 极大限制了 TFET器件的应用。 另外, 具有陡直亚阈值斜 率的 TFET器件在实验上也较难实现,这是因为实验较难在源结处实现陡直的掺杂浓 度梯度以致器件开启时隧穿结处的电场不够大,这会导致 TFET的亚阈值斜率相对理 论值退化。 因此, 如何在源结实现陡直的掺杂浓度梯度而获得超低的亚阈值斜率, 也 成为了 TFET器件的另一个重要问题。 发明内容 本发明的目的在于提出一种结调制型隧穿场效应晶体管及其制备方法。 在与现 有的 CMOS工艺兼容的条件下, 该器件能等效实现陡直的源结掺杂浓度的效果, 更 加显著地优化 TFET器件的亚阈值斜率, 并同时提升器件的导通电流, 且栅和漏之间 存在栅未覆盖区,一方面有效地抑制了器件的双极导通效应, 同时能抑制小尺寸下源 结边角处的寄生隧穿电流。 本发明的技术方案如下: 本发明隧穿场效应晶体管包括一个半导体衬底 (1)、 一个垂直沟道区 (2)、 一 个高掺杂源区 (4)、 一个低掺杂漏区 (8)、 一个栅介质层 (5) 和一个控制栅 (6), 以及与控制栅 (6)相连的栅电极 (9), 与高掺杂源区 (4)连接的源电极 (10)和与 低掺杂漏区 (8) 连接的漏电极 (11), 其特征在于, 半导体衬底 (1) 的上方为垂直 沟道区 (2), 垂直沟道区 (2)呈长方体状; 垂直沟道区 (2) 的下方一侧为栅介质层 (5)和控制栅 (6), 其它侧面为高掺杂源区 (4), 低掺杂漏区 (8)位于垂直沟道区 (2) 的顶端, 低掺杂漏区 (8) 和控制栅 (6) 之间为隔离区 (7), 低掺杂漏区 (8) 和高掺杂源区 (4) 掺有不同掺杂类型的杂质, 且低掺杂漏区 (8) 的掺杂浓度在 5xl017cm_3至 lxl019cm_3之间,高掺杂源区(4)的掺杂浓度在 lxl019cm_3至 lxl021cm_3 之间。 半导体衬底 (1) 的掺杂浓度在 lxl014 Cm-3至 lxl017cm— 3之间。 长方体状的垂 直沟道区 (2) 的长和宽相等, 且小于一倍的源耗尽层宽度, 源耗尽层宽度的范围为 25ηιη-1.5μιη, 垂直沟道区 (2) 的高大于长和宽, 垂直沟道区 (2) 的高度和长宽的 比例为 1.5:1-5:1。 低掺杂漏区 (8) 和控制栅 (6) 之间的垂直距离为 10ηιη-1μιη。 上述隧穿场效应晶体管的制备方法, 包括以下步骤:
(1) 在半导体衬底上淀积硬掩膜层, 并光刻刻蚀, 定义垂直沟道区图形; 在硬掩膜 的保护下, 深刻蚀形成垂直的沟道区;
(2) 在硬掩膜的保护下, 离子注入形成环绕垂直沟道区四面的高掺杂源区; 光刻仅 暴露出一面高掺杂源区, 并刻蚀, 刻蚀深度大于离子注入深度, 使得只剩下三面包围 的高掺杂源区;
(3) 生长栅介质层, 并淀积控制栅材料;
(4) 接着淀积隔离层材料并回刻直至高掺杂源区上方的多晶硅, 在隔离层的保护下 腐蚀多晶硅, 仅留下被隔离层覆盖的多晶硅层作为垂直控制栅; ( 5 ) 继续淀积隔离层, 淀积厚度决定了漏和栅之间栅未覆盖区的长度; 在隔离层的 保护下, 离子注入形成另一种掺杂类型的较低掺杂漏区,然后快速高温热退火激活掺 杂杂质;
(6) 最后进入常规 CMOS后道工序, 包括继续淀积隔离层、 开接触孔以及金属化, 即可制得所述的隧穿场效应晶体管, 如图 1所示。 上述的制备方法中, 所述步骤 (1 ) 中的半导体衬底材料选自 Si、 Ge、 SiGe、 GaAs或其他 II- VI, III-V和 IV-IV族的二元或三元化合物半导体、绝缘体上的硅( SOI) 或绝缘体上的锗 (GOI)。 上述的制备方法中, 所述步骤 (3 ) 中的栅介质层材料选自 Si02、 Si3N4和高 K 栅介质材料。 上述的制备方法中,所述步骤(3 )中的生长栅介质层的方法选自下列方法之一: 常规热氧化、 掺氮热氧化、 化学气相淀积和物理气相淀积。 上述的制备方法中, 所述步骤 (3 ) 中的控制栅材料选自掺杂多晶硅、 金属钴, 镍以及其他金属或金属硅化物。 本发明的技术效果如下: 一、 本发明隧穿场效应晶体管的垂直沟道区三面包围的高掺杂源区提供的 PN 结能有效耗尽沟道区, 使得栅下表面沟道能带提高, 因此当该器件发生带带隧穿时能 获得比传统 TFET更陡的能带和更窄的隧穿势垒宽度,等效实现了陡直的隧穿结掺杂 浓度梯度的效果, 从而大幅提高传统 TFET的亚阈特性。 同时相比平面条形栅的结耗 尽型隧穿场效应晶体管, 由于平面结构只能靠两边 PN结耗尽, 因此本发明的三面包 围结构能更加有效调制隧穿结, 获得更加陡直的亚阈特性。 二、 在不增加有源区面积的前提下, 本发明的垂直沟道区的设计能有效提高隧 穿面积, 隧穿面积由高掺杂源区和栅的交界面决定, 如图 la中的虚线框出的区域所 示。 隧穿面积的增加有利于进一步提高器件的开态电流。 三、 本发明采用了短栅的设计, 即栅电极部分覆盖沟道区, 在栅和漏之间存在 一定间距的未覆盖区域。这种设计不仅可以有效抑制漏结处的隧穿, 即常规 TFET中 的双极导通效应,还能有效降低栅电极对未覆盖区的影响, 因此可以抑制小尺寸下寄 生隧穿结的隧穿, 寄生隧穿结发生的区域如图 la中 B点所示位置。 因此能降低器件 开启时的亚阈值斜率。 另外, 漏区掺杂浓度较低也能进一步抑制双极导通效应。 四、 该器件制备工艺简单, 制备方法与传统的 MOSFET工艺完全兼容。 简而言之, 该器件结构采用垂直沟道区增加了器件的隧穿面积, 利用高掺杂源 区三面包围沟道区的设计有效调制了源端隧穿结,并且抑制了双极导通效应和小尺寸 下的寄生隧穿结的隧穿, 提高了 TFET器件的开态电流和亚阈特性且制备方法简单。 与现有的 TFET相比, 在同样的有源区尺寸下, 该器件可以得到更高的导通电流和更 陡直的亚阈值斜率, 且能保持低的泄漏电流, 有望在低功耗领域得到采用, 有较高的 实用价值。 附图说明
图 la是本发明的结调制型垂直隧穿场效应晶体管的剖面示意图, 图 lb是沿图 la中 AA'方向的器件俯视图, 其中箭头所示为隧穿方向; 图 2a是刻蚀形成垂直沟道之后,在硬掩膜的保护下离子注入形成高掺杂漏区后 的器件剖面图, 图 2b是相应的器件俯视图; 图 3a是光刻仅暴露出垂直沟道区的一面, 并刻蚀形成凹槽后的器件剖面图, 图 3b是相应的器件俯视图; 图 4a是生长栅介质层, 并淀积控制栅材料后的器件剖面图, 图 4b是相应的器 件俯视图;
图 5a是淀积隔离层并回刻, 腐蚀未被保护的多晶硅后的器件剖面图, 图 5b是 相应的器件俯视图; 图 6a是继续淀积隔离层, 并离子注入形成另一种掺杂类型的较低掺杂漏区后的 器件剖面图, 图 6b是相应的器件俯视图; 图 7是继续淀积隔离层、 开接触孔以及形成金属引出后的结调制型垂直隧穿场 效应晶体管剖面图; 图中:
1 ——半导体衬底 垂直沟道区 3 高掺杂源区
5 ——栅介质层 控制栅 低掺杂漏区 9——栅电极 10——源电极 11 ——漏电极 具体实施方式 下面通过实例对本发明做进一步说明。 需要注意的是, 公布实施例的目的在于 帮助进一步理解本发明,但是本领域的技术人员可以理解: 在不脱离本发明及所附权 利要求的精神和范围内, 各种替换和修改都是可能的。 因此, 本发明不应局限于实施 例所公开的内容, 本发明要求保护的范围以权利要求书界定的范围为准。 本发明制备方法的一具体实例包括图 2至图 7所示的工艺步骤:
1、在晶向为(100)的体硅硅片硅衬底 1上淀积硬掩膜层 3, 硬掩膜层为 Si3N4, 厚度为 300nm, 衬底掺杂浓度为轻掺杂; 然后光刻刻蚀, 定义出垂直沟道区 2所在的 正方形图形, 长宽均为 50nm; 在硬掩膜的保护下, 深刻蚀硅材料形成垂直的沟道区 2;
2、在硬掩膜的保护下, 进行 P+离子注入, 形成环绕垂直沟道区四面的高掺杂源 区 4, 离子注入的能量为 40keV, 注入杂质为 BF2 +, 如图 2a、 2b所示; 3、 光刻仅暴露出环绕垂直沟道区一面的高掺杂源区, 并刻蚀硅, 刻蚀深度为
500nm, 使得只剩下三面包围的高掺杂源区, 去除光刻胶, 如图 3a、 3b所示;
4、 热生长一层栅介质层 5, 栅介质层为 Si02, 厚度为 l~5nm; 淀积栅材料, 栅 材料为掺杂多晶硅层, 厚度为 150~300nm, 如图 4a、 4b所示。
5、 淀积隔离层 7, 隔离层为 Si02, 厚度为 Ιμιη, 回刻, 停止层为高掺杂源区上 方的多晶硅; 然后在隔离层 7的保护下各项同性腐蚀多晶硅层,仅留下被隔离层覆盖 的多晶硅层作为垂直控制栅 6, 如图 5a、 5b所示。
6、 继续淀积 Si02, 淀积厚度为 50nm, 然后进行 N离子注入, 形成另一种掺杂 类型的低掺杂漏区 8, 离子注入的能量为 50keV, 注入杂质为 As+, 如图 6a、 6b所示; 进行一次快速高温退火, 激活源漏掺杂的杂质。 7、 最后进入常规 CMOS后道工序, 包括淀积钝化层、 开接触孔以及金属化, 即可制得所述的结调制型垂直隧穿场效应晶体管, 如图 7所示。 虽然本发明已以较佳实施例披露如上, 然而并非用以限定本发明。 任何熟悉本 领域的技术人员,在不脱离本发明技术方案范围情况下, 都可利用上述揭示的方法和 技术内容对本发明技术方案作出许多可能的变动和修饰,或修改为等同变化的等效实 施例。 因此, 凡是未脱离本发明技术方案的内容, 依据本发明的技术实质对以上实施 例所做的任何简单修改、 等同变化及修饰, 均仍属于本发明技术方案保护的范围内。

Claims

权 利 要 求
1. 一种隧穿场效应晶体管,包括一个半导体衬底(1)、一个垂直沟道区(2)、 一个高掺杂源区 (4)、 一个低掺杂漏区 (8)、 一个栅介质层 (5) 和一个控制栅
(6), 以及与控制栅 (6)相连的栅电极(9), 与高掺杂源区 (4)连接的源电极 (10)和与低掺杂漏区 (8)连接的漏电极(11), 其特征在于, 半导体衬底 (1) 的上方为垂直沟道区 (2), 垂直沟道区 (2)呈长方体状; 垂直沟道区 (2) 的下 方一侧为栅介质层 (5) 和控制栅 (6), 其它侧面为高掺杂源区 (4), 低掺杂漏 区 (8)位于垂直沟道区 (2) 的顶端, 低掺杂漏区 (8)和控制栅 (6)之间为隔 离区 (7), 低掺杂漏区 (8)和高掺杂源区 (4)掺有不同掺杂类型的杂质, 且低 掺杂漏区 (8) 的掺杂浓度在 5xl017cm_3至 lxl019cm_3之间, 高掺杂源区 (4) 的 掺杂浓度在 lxl019cm_3至 lxl021cm_3之间。
2. 如权利要求 1所述的隧穿场效应晶体管, 其特征在于, 半导体衬底 (1) 的掺杂浓度在 lxl014cm_3至 lxl017cm_3之间。
3. 如权利要求 1所述的隧穿场效应晶体管, 其特征在于, 垂直沟道区 (2) 的长和宽相等, 且小于一倍的源耗尽层宽度, 源耗尽层宽度的范围为 25ηιη-1.5μιη, 垂直沟道区 (2) 的高大于垂直沟道区 (2) 的长和宽, 垂直沟道 区 (2) 的高度和宽的比例为 1.5:1-5:1。
4. 如权利要求 1所述的隧穿场效应晶体管, 其特征在于, 低掺杂漏区 (8) 和控制栅 (6) 之间的垂直距离为 10ηιη-1μιη。
5. 一种制备权利要求 1所述的隧穿场效应晶体管的方法, 包括以下步骤: (1) 在半导体衬底上淀积硬掩膜层, 并光刻刻蚀, 定义垂直沟道区图形; 在硬掩膜的保护下, 深刻蚀形成垂直的沟道区;
(2)在硬掩膜的保护下, 离子注入形成环绕垂直沟道区四面的高掺杂源区; 光刻仅暴露出一面高掺杂源区, 并刻蚀, 刻蚀深度大于离子注入深度, 使得只剩 下三面包围的高掺杂源区;
(3) 生长栅介质层, 并淀积控制栅材料;
(4) 淀积隔离层材料并回刻直至高掺杂源区上方的多晶硅, 在隔离层的保 护下腐蚀多晶硅, 仅留下被隔离层覆盖的多晶硅层作为垂直控制栅;
( 5 ) 继续淀积隔离层, 淀积厚度决定了漏和栅之间栅未覆盖区的长度; 在 隔离层的保护下, 离子注入形成另一种掺杂类型的低掺杂漏区, 然后快速热退火 激活掺杂杂质;
(6)最后进入 CMOS后道工序, 包括继续淀积隔离层、 开接触孔以及金属 化, 即可制得如权利要求 1所述的隧穿场效应晶体管。
6. 如权利要求 5所述的制备方法, 其特征在于, 所述步骤 (1 ) 中的半导体 衬底材料选自 Si、 Ge、 SiGe、 GaAs或其他 II- VI, III-V和 IV-IV族的二元或三 元化合物半导体、 绝缘体上的硅或绝缘体上的锗。
7. 如权利要求 5所述的制备方法, 其特征在于, 所述步骤 (3 ) 中的栅介质 层材料选自 Si02、 Si3N4和高 K栅介质材料。
8. 如权利要求 5所述的制备方法, 其特征在于, 所述步骤 (3 ) 中的生长栅 介质层的方法选自下列方法之一: 热氧化、掺氮热氧化、化学气相淀积和物理气 相淀积。
9. 如权利要求 5所述的制备方法, 其特征在于, 所述步骤 (3 ) 中的控制栅 材料选自掺杂多晶硅、 金属钴或镍。
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