CN105390531A - 一种隧穿场效应晶体管的制备方法 - Google Patents
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Abstract
本发明公开了一种隧穿场效应晶体管的制备方法,属于CMOS超大规模集成电路(ULSI)中场效应晶体管逻辑器件领域。该方法通过制备工艺设计实现了超陡源结的隧穿场效应晶体管。本发明可以显著改善器件特性;同时,该制备方法与标准的CMOS?IC工艺兼容,能有效地在CMOS集成电路中集成TFET器件,还可以利用标准工艺制备由TFET组成的低功耗集成电路,极大地降低了生产成本,简化了工艺流程。
Description
技术领域
本发明属于CMOS超大规模集成电路(ULSI)中场效应晶体管逻辑器件领域,具体涉及一种实现超陡源结的隧穿场效应晶体管的制备方法。
背景技术
自集成电路诞生以来,微电子集成技术一直按照“摩尔定律”不断发展,半导体器件尺寸不断缩小。随着半导体器件进入深亚微米范围,传统MOSFET器件由于受到自身扩散漂流的导通机制所限,亚阈斜率受到热电势kT/q的限制而无法随着器件尺寸的缩小而同步减小。这就导致MOSFET器件泄漏电流缩小无法达到器件尺寸缩小的要求,整个芯片的能耗不断上升,芯片功耗密度急剧增大,严重阻碍了芯片系统集成的发展。为了适应集成电路的发展趋势,新型超低功耗器件的开发和研究工作就显得特别重要。隧穿场效应晶体管(TFET,TunnelingField-EffectTransistor)采用带带隧穿(BTBT)新导通机制,是一种非常有发展潜力的适于系统集成应用发展的新型低功耗器件。TFET通过栅电极控制源端与沟道交界面处隧穿结的隧穿宽度,使得源端价带电子隧穿到沟道导带(或沟道价带电子隧穿到源端导带)形成隧穿电流。这种新型导通机制突破传统MOSFET亚阈斜率理论极限中热电势kT/q的限制,可以实现低于60mV/dec的具有超陡亚阈斜率,降低器件静态漏泄电流进而降低器件静态功耗。
其中,为了获得较高的隧穿几率和较陡的亚阈斜率,TFET器件需要实现较陡的隧穿源结。但是,传统的离子注入方法普遍形成的源漏结处浓度梯度较缓,难以实现较陡的隧穿源结,导致实验制备TFET器件难以实现较陡的亚阈斜率,器件性能与理论仿真结果差距较大,这非常不利于TFET器件在超低功耗领域的应用。因此,如何在实验制备中增大隧穿结处杂质浓度梯度,实现较陡直的隧穿源结,是TFET器件实际制备中需要解决的一个非常重要的问题。
发明内容
本发明的目的在于提供一种实现超陡源结的隧穿场效应晶体管制备方法。该制备方法可实现非常陡直的隧穿源结,从而有效改善隧穿场效应晶体管器件性能。
本发明提供的技术方案如下:
本发明隧穿场效应晶体管,如图1所示,包括隧穿源区5,沟道区6,漏区10,半导体衬底区1,栅介质层7,以及位于栅介质层之上的控制栅8,其特征是,所述器件为垂直沟道,且通过化学机械平坦化去除表面杂质浓度较低的部分源区,使得源区5表面处于杂质浓度峰值区域,在源区5和沟道区6间实现非常陡直的杂质分布梯度。对于N型器件来说,隧穿源区为P型重掺杂,其掺杂浓度约为1E20cm-3-1E21cm-3,漏区为N型重掺杂,其掺杂浓度约为1E18cm-3-1E19cm-3,沟道区为P型轻掺杂,其掺杂浓度约为1E13cm-3-1E15cm-3;而对于P型器件来说,隧穿源区为N型重掺杂,其掺杂浓度约为1E20cm-3-1E21cm-3,漏区为P型重掺杂,其掺杂浓度约为1E18cm-3-1E19cm-3,沟道区为N型轻掺杂,其掺杂浓度约为1E13cm-3-1E15cm-3。
所述器件中化学机械平坦化去除杂质注入表面浓度较低的部分源区的厚度,与源区掺杂条件有关。去除源区厚度大于离子注入射程,会导致剩余源区表面的杂质浓度偏低;而去除源区厚度小于离子注入射程,同样会导致剩余源区表面的杂质浓度偏低,达不到实现超陡源结的效果。该厚度的确定随不同离子注入能量而有所不同,一般情况下取值在10nm-100nm之间。
所述的隧穿场效应晶体管可以应用于Si,或Ge,也可以应用于其他II-VI,III-V和IV-IV族的二元或三元化合物半导体材料、或绝缘体上的硅(SOI)或绝缘体上的锗(GOI)。
本发明提供了一种实现超陡源结的隧穿场效应晶体管制备方法,包括以下步骤:
1)衬底准备:轻掺杂或未掺杂的半导体衬底;
2)在衬底上初始热氧化并淀积一层氮化物;
3)光刻后进行浅沟槽隔离(ShallowTrenchIsolation,STI),并淀积隔离材料填充深孔后进行化学机械平坦化(ChemicalMechanicalPolishing,CMP);
4)热氧化形成注入阻挡层,光刻暴露出隧穿源区,以光刻胶为掩膜,进行离子注入形成隧穿源区,浓度约为1E20cm-3-1E21cm-3;
5)进行化学机械平坦化CMP,去除注入阻挡层及表面杂质浓度较低的部分源区,使得表面处于杂质浓度峰值区域;
6)外延生长本征硅Si材料,并刻蚀形成垂直沟道;
7)生长栅介质材料和栅材料;
8)淀积掩膜层,该掩膜层厚度即为器件栅长,去除多余栅材料,形成L型双栅结构;
9)以掩膜层为掩膜,进行离子注入形成漏区掺杂,掺杂浓度约1E18cm-3-1E19cm-3;
10)快速高温退火激活杂质;
11)最后进入同CMOS一致的后道工序,包括淀积钝化层、开接触孔以及金属化等,即可制得具有超陡源结的隧穿场效应晶体管。
所述的制备方法,其特征是,步骤1)中所述的轻掺杂,其掺杂浓度约为1E13cm-3-1E15cm-3。
所述的制备方法,其特征是,步骤1)中所述的半导体衬底材料选自Si、或Ge,或其他II-VI,III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅(SOI)或绝缘体上的锗(GOI)。
所述的制备方法,其特征是,步骤7)中所述的栅介质材料选自SiO2、Si3N4或高K栅(介电常数K>3.9)介质材料。
所述的制备方法,其特征是,步骤7)中所述的淀积栅介质材料的方法选自下列方法之一:化学气相淀积或物理气相淀积。
所述的制备方法,其特征是,步骤7)中所述的栅材料选自掺杂多晶硅、金属钴,镍以及其他金属或金属硅化物。
本发明的技术效果(以N型器件为例):
1、由于该器件的垂直沟道设计,工艺上较易实现双栅结构,从而增强器件栅控能力,达到增大器件导通电流,获得更陡直亚阈斜率的效果。
2、由于源区表面杂质掺杂浓度较高,与沟道区表面掺杂浓度梯度较大,可以实现非常陡直的隧穿源结,从而可以有效提高隧穿效率并实现更陡的亚阈斜率。
3、由于该器件在源区存在一个过覆盖区域,在控制栅过覆盖的源区部分将会发生垂直于栅表面的隧穿,从而增大隧穿面积,增大器件导通电流。
5、由于器件的控制栅的L型结构,控制栅拐角处电场强度很大,将增大源端隧穿结处的隧穿电场,有利于增大器件导通电流,并获得更加陡直的亚阈斜率。
与现有的TFET相比,本发明的超陡源结隧穿场效应晶体管通过制备工艺设计可以显著改善器件特性。同时,该制备方法与标准的CMOSIC工艺兼容,能有效地在CMOS集成电路中集成TFET器件,还可以利用标准工艺制备由TFET组成的低功耗集成电路,极大地降低了生产成本,简化了工艺流程。
附图说明
图1为本发明实现超陡源结的隧穿场效应晶体管的结构示意图。
图2为在半导体衬底上形成STI隔离后去除氮化物后的器件剖面图;
图3为光刻暴露出TFET器件的隧穿源区并离子注入形成隧穿源区后的器件剖面图;
图4为进行化学机械平坦化CMP,去除注入阻挡层及表面杂质浓度较低的部分源区后的器件剖面图;
图5为外延生长本征硅Si材料,并刻蚀形成垂直沟道后的器件剖面图;
图6为淀积栅介质层和栅材料层后的器件剖面图;
图7为淀积掩膜层,通过各向同性回刻完成栅图形刻蚀后的器件剖面图;
图8为光刻暴露出TFET器件的漏区并离子注入形成漏区后的器件剖面图。
图中,
1-半导体衬底;2-STI隔离;3-氧化层;4-光刻胶;5-隧穿源区;6-沟道区;
7-栅介质层;8-控制栅;9-掩膜层;10-漏区;11-后道工序的金属。
具体实施方式
以下结合附图,通过具体的实施例对本发明所述的实现超陡源结的隧穿场效应晶体管的实施方法做进一步的说明。
具体实施步骤如图1-图8所示:(本例以N型器件为例,P型器件可以以此类推)
1、在衬底掺杂浓度为轻掺杂(约1E13cm-3-1E15cm-3)的,晶向为<001>的Si衬底1上初始热氧化一层二氧化硅,厚度约10nm,并淀积一层氮化硅(Si3N4),厚度约100nm,之后采用浅槽隔离技术制作有源区STI隔离2,然后进行CMP,如图2所示;
2、热氧化形成注入阻挡层3,光刻暴露出隧穿源区5,以光刻胶4为掩膜,进行隧穿源区,5离子注入(BF2,5E15/cm-2,40keV),如图3所示;
3、进行化学机械平坦化CMP,去除注入阻挡层3及表面杂质浓度较低的部分源区,其中源区去除厚度约40nm,使得表面处于杂质浓度峰值区域,如图4所示;
4、外延生长一层本征Si材料,厚度约为200nm,并刻蚀形成垂直沟道,沟道区6宽度在20nm-200nm之间,如图5所示;
5、热氧化生长栅介质层7(SiO2),厚度为5nm;采用LPCVD淀积控制栅8,栅材料为掺杂多晶硅层,厚度为50~200nm,如图6所示;
6、淀积掩膜层9(SiO2),厚度约为100nm,该掩膜层厚度即为器件栅长,采用稀H氢氟酸(DHF)各向同性腐蚀掉多余多晶硅栅部分,如图7所示;
7、以掩膜层9为掩膜,进行漏区10离子注入(As,4E15/cm-2,50keV),如图8所示;
8、进行一次快速高温退火,对注入杂质进行激活(1050℃,10s);
9、最后进入常规后道工序,包括淀积钝化层、开接触孔、以及金属化11等,图1所示为制得的所述基于标准CMOSIC工艺制备的N型的实现超陡源结的隧穿场效应晶体管结构示意图。
虽然本发明已以较佳实施例披露如上,然而并非用以限定本发明。任何熟悉本领域的技术人员,在不脱离本发明技术方案范围情况下,都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰,或修改为等同变化的等效实施例。因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。
Claims (6)
1.一种隧穿场效应晶体管的制备方法,包括以下步骤:
1)衬底准备:轻掺杂或未掺杂的半导体衬底;
2)在衬底上初始热氧化并淀积一层氮化物;
3)光刻后进行浅沟槽隔离,并淀积隔离材料填充深孔后进行化学机械平坦化;
4)热氧化形成注入阻挡层,光刻暴露出隧穿源区,以光刻胶为掩膜,进行离子注入形成隧穿源区,浓度约为1E20cm-3-1E21cm-3;
5)进行化学机械平坦化CMP,去除注入阻挡层及表面杂质浓度较低的部分源区,使得表面处于杂质浓度峰值区域;
6)外延生长本征硅Si材料,并刻蚀形成垂直沟道;
7)生长栅介质材料和栅材料;
8)淀积掩膜层,该掩膜层厚度即为器件栅长,去除多余栅材料,形成L型双栅结构;
9)以掩膜层为掩膜,进行离子注入形成漏区掺杂,掺杂浓度约1E18cm-3-1E19cm-3;
10)快速高温退火激活杂质;
11)最后进入同CMOS一致的后道工序,包括淀积钝化层、开接触孔以及金属化,即可制得具有超陡源结的隧穿场效应晶体管。
2.如权利要求1所述的制备方法,其特征在于,步骤1)中所述的轻掺杂,其掺杂浓度约为1E13cm-3-1E15cm-3。
3.如权利要求1所述的制备方法,其特征在于,步骤1)中所述的半导体衬底材料选自Si、或Ge,或其他II-VI,III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅或绝缘体上的锗。
4.如权利要求1所述的制备方法,其特征在于,步骤7)中所述的栅介质材料为SiO2、Si3N4或高K栅介质材料。
5.如权利要求1所述的制备方法,其特征在于,步骤7)中所述的淀积栅介质材料的方法选自下列方法之一:化学气相淀积或物理气相淀积。
6.如权利要求1所述的制备方法,其特征在于,步骤7)中所述的栅材料为掺杂多晶硅、金属钴,镍以及其金属硅化物。
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