CN102945861B - 条形栅调制型隧穿场效应晶体管及其制备方法 - Google Patents
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Abstract
本发明公开了一种条形栅调制型隧穿场效应晶体管及其制备方法，属于CMOS超大集成电路（ULSI）中的场效应晶体管逻辑器件与电路领域。该隧穿场效应晶体管包括一个控制栅，一个栅介质层，一个半导体衬底，一个高掺杂源区和一个高掺杂漏区，所述高掺杂源区和漏区分别位于控制栅的两侧，所述控制栅为栅长大于栅宽的条形结构，控制栅的一侧与高掺杂漏区连接，控制栅的另一侧向高掺杂源区横向延伸，位于控制栅下的区域为沟道区，该控制栅的栅宽小于2倍的源耗尽层宽度。采用条形栅结构调制了源端隧穿结，实现了等效于源结具有陡直掺杂浓度梯度的效果，提高了TFET器件的性能且制备方法简单。
Description
技术领域
本发明属于CMOS超大集成电路（ULSI）中的场效应晶体管逻辑器件与电路领域，具体涉及一种条形栅调制型隧穿场效应晶体管及其制备方法。
背景技术
在摩尔定律的驱动下，传统MOSFET的特征尺寸不断缩小，如今已经到进入纳米尺度，随之而来，器件的短沟道效应等负面影响也愈加严重。漏致势垒降低、带带隧穿等效应使得器件关态漏泄电流不断增大，同时，传统MOSFET的亚阈值斜率受到热电势的限制无法随着器件尺寸的缩小而同步减小，由此增加了器件功耗。功耗问题如今已经成为限制器件等比例缩小的最严峻的问题。
为了能将器件应用在超低压低功耗领域，采用新型导通机制而获得超陡亚阈值斜率的器件结构和工艺制备方法已经成为小尺寸器件下大家关注的焦点。近些年来研究者们提出了一种可能的解决方案，就是采用隧穿场效应晶体管（TFET）。TFET不同于传统MOSFET，其源漏掺杂类型相反，利用栅极控制反向偏置的P-I-N结的带带隧穿实现导通，能突破传统MOSFET亚阈值斜率60mV/dec的限制，并且其漏电流非常小。TFET具有低漏电流、低亚阈值斜率、低工作电压和低功耗等诸多优异特性，但由于受源结隧穿几率和隧穿面积的限制，TFET面临着开态电流小的问题，远远比不上传统MOSFET器件，极大限制了TFET器件的应用。另外，具有陡直亚阈值斜率的TFET器件在实验上也较难实现，这是因为实验较难在源结处实现陡直的掺杂浓度梯度以致器件开启时隧穿结处的电场不够大，这会导致TFET的亚阈值斜率相对理论值退化。因此，如何在源结实现陡直的掺杂浓度梯度而获得超低的亚阈值斜率，也成为了TFET器件的另一个重要问题。
发明内容
本发明的目的在于提出一种条形栅调制型隧穿场效应晶体管及其制备方法。在与现有的CMOS工艺完全兼容的条件下，该结构仅仅改变传统隧穿场效应晶体管的栅版图结构，能等效实现陡直的源结掺杂浓度的效果，显著地优化TFET器件的亚阈值斜率，并同时提升器件的导通电流。
本发明的技术方案如下：
本发明隧穿场效应晶体管包括一个半导体衬底、一个高掺杂源区、一个高掺杂漏区、一个栅介质层和一个控制栅，所述高掺杂源区和高掺杂漏区分别位于控制栅的两侧，且掺有不同掺杂类型的杂质，与通常的隧穿场效应晶体管的控制栅相比，本发明控制栅为栅长大于栅宽的条形结构，控制栅的一侧与高掺杂漏区连接，控制栅的另一侧向高掺杂源区横向延伸，即条形控制栅部分位于高掺杂源区和高掺杂漏区之间，另一部分延伸到高掺杂源区，位于控制栅下的区域仍是沟道区，所述高掺杂源区靠条形控制栅自对准形成，条形控制栅下无高掺杂源，控制栅的位于高掺杂源区和高掺杂漏区之间的长度与延伸到高掺杂源区的长度比为1：1—1：5。所述控制栅的栅宽小于2倍的源耗尽层宽度，源耗尽层宽度的范围为25nm-1.5um。
高掺杂源区和高掺杂漏区的掺杂浓度均在1×1019cm-3至1×1021cm-3之间，衬底掺杂浓度在1×1014cm-3至1×1017cm-3之间。
上述隧穿场效应晶体管的制备方法，包括以下步骤：
（1）在半导体衬底上通过浅槽隔离定义有源区；
（2）生长栅介质层；
（3）淀积控制栅材料，接着光刻和刻蚀，形成条形栅图形；
（4）光刻暴露出漏掺杂区，以光刻胶为掩膜，离子注入形成高掺杂漏区；
（5）光刻暴露出源掺杂区，以光刻胶及栅为掩膜，离子注入形成另一种掺杂类型的高掺杂源区，然后快速高温热退火激活掺杂杂质；
（6）最后进入常规CMOS后道工序，包括淀积钝化层、开接触孔以及金属化等，即可制得所述的隧穿场效应晶体管，如图5所示。
上述的制备方法中，所述步骤（1）中的半导体衬底材料选自Si、Ge、SiGe、GaAs或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅（SOI）或绝缘体上的锗（GOI）。
上述的制备方法中，所述步骤（2）中的栅介质层材料选自SiO2、Si3N4和高K栅介质材料。
上述的制备方法中，所述步骤（2）中的生长栅介质层的方法选自下列方法之一：常规热氧化、掺氮热氧化、化学气相淀积和物理气相淀积。
上述的制备方法中，所述步骤（3）中的控制栅材料选自掺杂多晶硅、金属钴，镍以及其他金属或金属硅化物。
本发明的技术效果如下：
一、在相同的有源区面积下，该器件利用延展进源区内的条形栅，能实现更大的隧穿面积，进而能得到高于传统TFET的导通电流；
二、在不增加工艺步骤的前提下，仅仅通过简单的版图设计（即条形栅形貌），利用条形栅两侧的PN结耗尽效应使得栅下表面沟道能带提高，因此当该器件发生带带隧穿时能获得比传统TFET更陡的能带和更窄的隧穿势垒宽度，等效实现了陡直的隧穿结掺杂浓度梯度的效果，从而大幅提高传统TFET的亚阈特性；
三、该器件制备工艺简单，制备方法与传统的MOSFET工艺完全兼容。
简而言之，该器件结构采用条形栅结构调制了源端隧穿结，实现了等效于源结具有陡直掺杂浓度梯度的效果，提高了TFET器件的性能且制备方法简单。与现有的TFET相比，在同样的工艺条件、同样的工艺步骤和同样的有源区尺寸下，该器件可以得到更高的导通电流和更陡直的亚阈值斜率，且能保持低的泄漏电流，有望在低功耗领域得到采用，有较高的实用价值。
附图说明
图1是半导体衬底上生长栅介质层并淀积栅材料的工艺步骤示意图；
图2a是光刻并刻蚀后形成的控制栅的器件沿图2b虚线方向的剖面图，图2b是相应的器件俯视图；
图3a是光刻暴露出漏区并离子注入形成高掺杂漏区后的器件沿图3b虚线方向的剖面图，图3b是相应的器件俯视图；
图4a是光刻暴露出源区并离子注入形成相反类型的高掺杂源区后的器件沿图4b虚线方向的剖面图，图4b是相应的器件俯视图；
图5是本发明的条形栅调制型隧穿场效应晶体管的器件俯视图；
图6a是本发明晶体管沿图5中AA’方向的剖面图；
图6b是本发明晶体管沿图5中BB’方向的剖面图；
图中：
1——半导体衬底2——栅介质层
3——控制栅4——光刻胶
5——高掺杂漏区6——相反类型的高掺杂源区
具体实施方式
下面通过实例对本发明做进一步说明。需要注意的是，公布实施例的目的在于帮助进一步理解本发明，但是本领域的技术人员可以理解：在不脱离本发明及所附权利要求的精神和范围内，各种替换和修改都是可能的。因此，本发明不应局限于实施例所公开的内容，本发明要求保护的范围以权利要求书界定的范围为准。
本发明制备方法的一具体实例包括图1至图4b所示的工艺步骤：
1、在晶向为（100）的体硅硅片硅衬底1上采用浅槽隔离技术制作有源区隔离层，衬底掺杂浓度为轻掺杂；然后热生长一层栅介质层2，栅介质层为SiO2，厚度为1~5nm；淀积栅材料3，栅材料为掺杂多晶硅层，厚度为150~300nm，如图1所示。
2、光刻出条形栅图形，刻蚀栅材料3直到栅介质层2，如图2a、2b所示，条形栅宽度典型为1μm。
3、光刻出漏区图形，以光刻胶4为掩膜进行P+离子注入，形成高掺杂P+漏区5，离子注入的能量为40keV，注入杂质为BF2 +，如图3a、3b所示。
4、光刻出源区图形，以光刻胶和栅为掩膜进行N+离子注入，形成高掺杂N+源区6，离子注入的能量为50keV，注入杂质为As+，如图4a、4b所示；进行一次快速高温退火，激活源漏掺杂的杂质。
5、最后进入常规CMOS后道工序，包括淀积钝化层、开接触孔以及金属化等，即可制得所述的条形栅调制型隧穿场效应晶体管，如图5—6所示。
虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。
Claims (9)
1.一种隧穿场效应晶体管，包括一个半导体衬底、一个高掺杂源区、一个高掺杂漏区、一个栅介质层和一个控制栅，所述高掺杂源区和高掺杂漏区分别位于控制栅的两侧，其特征在于，所述控制栅为栅长大于栅宽的条形结构，控制栅的一侧与高掺杂漏区连接，控制栅的另一侧向高掺杂源区横向延伸，控制栅的延伸部分仅被高掺杂源区包围，位于控制栅下的区域为沟道区，该控制栅的栅宽小于2倍的源耗尽层宽度。
2.如权利要求1所述的隧穿场效应晶体管，其特征在于，控制栅的位于高掺杂源区和高掺杂漏区之间的长度与延伸到高掺杂源区的长度比为1：1—1：5。
3.如权利要求1所述的隧穿场效应晶体管，其特征在于，源耗尽层宽度的范围为25nm-1.5um。
4.如权利要求1所述的隧穿场效应晶体管，其特征在于，高掺杂源区和高掺杂漏区的掺杂浓度均在1×1019cm-3至1×1021cm-3之间，衬底掺杂浓度在1×1014cm-3至1×1017cm-3之间。
5.如权利要求1所述的隧穿场效应晶体管的制备方法，包括以下步骤：
1)在半导体衬底上通过浅槽隔离定义有源区；
2)生长栅介质层；
3)淀积控制栅材料，接着光刻和刻蚀，形成条形栅图形；
4)光刻暴露出漏掺杂区，以光刻胶为掩膜，离子注入形成高掺杂漏区；
5)光刻暴露出源掺杂区，以光刻胶及栅为掩膜，离子注入形成另一种掺杂类型的高掺杂源区，然后快速高温热退火激活掺杂杂质；
6)最后进入常规CMOS后道工序，制得所述的隧穿场效应晶体管。
6.如权利要求5所述的制备方法，其特征在于，所述步骤1)中的半导体衬底材料选自Si、Ge、SiGe、GaAs或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅或绝缘体上的锗。
7.如权利要求5所述的制备方法，其特征在于，所述步骤2)中的栅介质层材料选自SiO2、Si3N4和高K栅介质材料。
8.如权利要求5所述的制备方法，其特征在于，所述步骤2)中的生长栅介质层的方法选自下列方法之一：常规热氧化、掺氮热氧化、化学气相淀积和物理气相淀积。
9.如权利要求5所述的制备方法，其特征在于，所述步骤3)中的控制栅材料选自掺杂多晶硅、金属钴，镍以及其他金属或金属硅化物。
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| US14/130,631 US8981421B2 (en) | 2012-11-26 | 2013-07-08 | Strip-shaped gate-modulated tunneling field effect transistor and a preparation method thereof |
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| CN102983168B (zh) * | 2012-11-29 | 2015-04-15 | 北京大学 | 带双扩散的条形栅隧穿场效应晶体管及其制备方法 |
| CN103474464B (zh) * | 2013-08-27 | 2016-02-17 | 北京大学 | 一种复合机制的条形栅隧穿场效应晶体管及其制备方法 |
| CN103560152B (zh) * | 2013-11-15 | 2016-02-17 | 中国科学院上海微系统与信息技术研究所 | 一种垂直结构的隧穿场效应晶体管及其制备方法 |
| US10504721B2 (en) | 2015-04-30 | 2019-12-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Staggered-type tunneling field effect transistor |
| CN107743503B (zh) | 2015-06-25 | 2020-03-31 | 陶氏环球技术有限责任公司 | 用于制造碳纤维复合材料的新型环氧树脂体系 |
| US9735267B1 (en) | 2016-01-28 | 2017-08-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure and formation method of semiconductor device structure |
| CN106531622A (zh) * | 2016-12-29 | 2017-03-22 | 中国科学院微电子研究所 | 一种砷化镓基mosfet栅介质的制备方法 |
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