WO2016150335A1 - 隧穿场效应晶体管及其制作方法 - Google Patents

隧穿场效应晶体管及其制作方法 Download PDF

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Publication number
WO2016150335A1
WO2016150335A1 PCT/CN2016/076632 CN2016076632W WO2016150335A1 WO 2016150335 A1 WO2016150335 A1 WO 2016150335A1 CN 2016076632 W CN2016076632 W CN 2016076632W WO 2016150335 A1 WO2016150335 A1 WO 2016150335A1
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Prior art keywords
gate
substrate
sidewall
forming
region
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PCT/CN2016/076632
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English (en)
French (fr)
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吴昊
张臣雄
杨喜超
赵静
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华为技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate

Definitions

  • the present invention relates to the field of field effect transistor technologies, and in particular, to a tunneling field effect transistor and a method of fabricating the same.
  • MOSFETs metal oxide semiconductor field effect transistors
  • CMOS Complementary Metal Oxide Semiconductor
  • the theoretical minimum value of the subthreshold swing is 60 mV/dec, that is, if the linearity decreases the threshold At a voltage of 60 millivolts, the off-state current is exponentially increased by an order of magnitude, resulting in increased power consumption of the CMOS circuit. Therefore, it is necessary to introduce a device based on the new switching state switching mechanism with low power consumption and low subthreshold swing to replace the traditional MOSFET.
  • a tunneling field effect transistor (English: Tunnel Field Effect Transistor; TFET) is a gate-controlled reverse biased P-type doping-intrinsic doping-N-type doping junction (abbreviation: pin junction) Device.
  • the source-side carrier and the channel carrier-band band tunneling are realized by the gate-controlled p-i-n junction, and the switching state of the device is controlled.
  • TFETs can achieve subthreshold swings below 60mV/dec, allowing them to operate at lower drive voltages, which in turn reduces static power consumption.
  • the TFET also features lower off-state currents at the same threshold voltage and lower threshold voltages under the same on-state current conditions.
  • Electron-hole double-layer conductive tunneling field effect transistor (English: Electro-Hole Bilayer-Tunnel Field Effect Transistor; referred to as: EHB-TFET) As a TFET, it has extremely low subthreshold swing and high drive current.
  • EHB-TFET Electron-hole double-layer conductive tunneling field effect transistor
  • a P-type heavily doped region 01 is a source region
  • an N-type heavily doped region 02 is a drain region
  • an intermediate region is an undoped region or a lightly doped region.
  • the upper surface 03 of the channel region is a top gate (also referred to as a control gate)
  • the lower surface 04 of the channel region is a bottom gate (also referred to as a bias gate).
  • the doped regions of the top gate and the drain region overlap, and the top gate is separated from the doped region of the source region.
  • the bottom gate overlaps the doped region of the source region, and the bottom gate is separated from the doped region of the drain region.
  • the principle of turning on the EHB-TFET control device is: by electrostatic induction, the top gate is applied with a forward voltage, the forward voltage is called a control voltage, and the upper surface of the channel region induces N-type carriers; The negative voltage is called the bias voltage, and the lower surface of the channel region induces P-type carriers.
  • the band bends when the band (ie, the conduction band bottom of the upper surface of the channel region and the valence band top of the lower surface of the channel region)
  • the principle of controlling the device to be turned off by the EHB-TFET is that the top gate is applied with a voltage of 0 volts, and no induced carriers are generated on the upper surface of the channel region. The channel area is closed.
  • the area of the channel region is limited, and the doped regions of the drain region and the source region are required to be close to each other, so that the off-state current is large, and the off-state current is larger, and the static work is performed.
  • the present invention provides a tunneling field effect transistor and a method of fabricating the same.
  • the technical solution is as follows:
  • a tunneling field effect transistor comprising:
  • a substrate having a first doped region and a second doped region respectively disposed at both ends;
  • a first gate and a second gate are formed on the substrate on which the gate insulating dielectric layer is formed, and the first gate and the second gate are respectively located on both sides of the channel region;
  • the first doped region is spaced apart from the doped region of the second doped region by a predetermined distance, the predetermined distance being greater than a width of the channel region and smaller than a length of the substrate.
  • the channel region has a trapezoidal axial section, and the trapezoidal upper base length is less than the trapezoidal lower base length.
  • the doping type of the channel region is either intrinsic or shallow doped.
  • the tunneling field effect transistor further includes: a heterojunction,
  • the heterojunction is formed on a substrate on which the channel region is formed, and two ends of the heterojunction are respectively in contact with the protective layer and the second doped region, and one of the heterojunctions The side is in contact with the gate insulating dielectric layer.
  • the tunneling field effect transistor is an N-type tunneling field effect transistor
  • the first doped region is an N-type heavily doped drain region
  • the second doped region is P-type heavily doped a source region
  • the first gate is a control gate
  • the second gate is a bias gate
  • a doping type of the channel region is intrinsic doping or P-type shallow doping
  • the tunneling field effect transistor is a P-type tunneling field effect transistor
  • the first doped region is an N-type heavily doped source region
  • the second doped region is P-type heavily doped a drain region
  • the first gate is a bias gate
  • the second gate is a control gate
  • the doping type of the channel region is intrinsic doping or N-type shallow doping.
  • a method of fabricating a tunneling field effect transistor comprising:
  • the first doped region and the doped region of the second doped region being spaced apart by a predetermined distance, The predetermined distance is greater than a width of the channel region and smaller than a length of the substrate;
  • a second sub-insulating material filling layer is formed on the substrate on which the second gate is formed, and the second sub-insulating material filling layer and the first sub-insulating material filling layer constitute an insulating material filling layer.
  • the axial section of the channel region has a trapezoidal shape, and the length of the upper base of the trapezoid is smaller than the length of the lower base of the trapezoid.
  • the doping type of the channel region is either intrinsic or shallow doped.
  • the forming a sidewall etched channel etch hard mask layer structure on the substrate on which the protective layer is formed includes:
  • the method further includes:
  • a first gate contact hole pad is formed on the substrate on which the first gate is formed.
  • the method further includes:
  • An oxide fill, an oxide etch or a planarization process is performed on the etched substrate to insulate the first gate and expose the sidewall material.
  • the forming a second sidewall of the channel on the substrate formed with the first sub-insulating material filling layer comprises:
  • the exposed protective layer and substrate are etched to form a second sidewall of the trench.
  • the method further includes:
  • a second gate contact hole pad is formed on the substrate on which the second gate is formed.
  • the method further includes:
  • a contact process and a back end interconnection process are performed on the substrate on which the second sub-insulating material filling layer is formed.
  • the method before the forming the second oxide protective layer on the substrate on which the second sidewall of the trench is formed, the method further includes:
  • a heterojunction is formed on the substrate on which the channel region is formed.
  • the heterojunction is made of a Group IV element or a Group III-V element.
  • the tunneling field effect transistor is an N-type tunneling field effect transistor
  • the first doped region is an N-type heavily doped drain region
  • the second doped region is P-type heavily doped a source region
  • the first gate is a control gate
  • the second gate is a bias gate
  • a doping type of the channel region is intrinsic doping or P-type shallow doping
  • the tunneling field effect transistor is a P-type tunneling field effect transistor
  • the first doped region is an N-type heavily doped source region
  • the second doped region is P-type heavily doped Drain region
  • the first gate is a bias gate
  • the second gate is a control gate
  • the doping type of the channel region is intrinsic doping or N-type shallow doping.
  • the invention provides a tunneling field effect transistor and a manufacturing method thereof, wherein a substrate of a first doping region and a second doping region is respectively disposed at two ends of the tunneling field effect transistor, and a fin shape is formed on the substrate a raised channel region, a protective layer is formed on the substrate on which the channel region is formed, and a channel etching hard mask layer structure having a sidewall shape formed on the substrate on which the protective layer is formed is formed with a sidewall shape a gate insulating dielectric layer is formed on the substrate of the trench etch hard mask layer structure, and the first gate and the second gate are formed on the substrate on which the gate insulating dielectric layer is formed, and the first gate And the second gates are respectively located at two sides of the channel region, and the substrate formed with the first gate and the second gate is formed with a filling layer of an insulating material, and the doping of the first doped region and the second doped region
  • the preset distance between the regions is independent of the source and drain.
  • FIG. 1 is a schematic structural diagram of an EHB-TFET according to an embodiment of the present invention.
  • FIG. 2 is a schematic structural diagram of a tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of still another tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 4 is a flowchart of a method for fabricating a tunneling field effect transistor according to an embodiment of the present invention
  • FIG. 5 is a flowchart of another method for fabricating a tunneling field effect transistor according to an embodiment of the present invention.
  • FIG. 6 is a flow chart of a method for forming a channel etch hard mask layer in a sidewall shape according to an embodiment of the present invention
  • FIG. 7 is a side view showing a structure of forming a protective layer, a sidewall material, and an etching hard mask layer according to an embodiment of the present invention
  • FIG. 8 is a schematic diagram of forming a protective layer, a sidewall material, and an etching hard mask layer according to an embodiment of the present invention. Schematic diagram of the top view;
  • FIG. 9 is a schematic side view showing a structure for forming a steep side wall according to an embodiment of the present invention.
  • FIG. 10 is a top plan view showing a steep sidewall formed by an embodiment of the present invention.
  • FIG. 11 is a schematic side view showing a material for depositing a channel etch hard mask layer according to an embodiment of the present invention.
  • FIG. 12 is a top plan view showing a material for depositing a channel etch hard mask layer according to an embodiment of the present invention
  • FIG. 13 is a schematic side view showing a first sidewall of a channel according to an embodiment of the present invention.
  • FIG. 14 is a schematic top plan view showing a first sidewall of a channel according to an embodiment of the present invention.
  • FIG. 15 is a flowchart of a method for forming a first doped region according to an embodiment of the present invention.
  • FIG. 16 is a schematic side view showing a first doped region according to an embodiment of the present invention.
  • 17 is a top plan view showing a first doped region formed by an embodiment of the present invention.
  • FIG. 18 is a schematic side view showing a structure of forming a first gate according to an embodiment of the present invention.
  • FIG. 19 is a top plan view showing a first gate formed by an embodiment of the present invention.
  • 20 is a side view showing a structure of forming a first sub-insulating material filling layer according to an embodiment of the present invention
  • 21 is a top plan view showing a first sub-insulating material filling layer according to an embodiment of the present invention.
  • FIG. 22 is a side view showing a structure of a substrate on which a first sub-insulating material filling layer is formed according to an embodiment of the present invention
  • FIG. 23 is a top plan view showing the processing of a substrate on which a first sub-insulating material filling layer is formed according to an embodiment of the present invention
  • 24 is a schematic side view showing a second sidewall of a channel according to an embodiment of the present invention.
  • 25 is a top plan view showing a second sidewall of a channel according to an embodiment of the present invention.
  • FIG. 26 is a schematic side view showing a second doped region according to an embodiment of the present invention.
  • FIG. 27 is a top plan view showing a second doped region according to an embodiment of the present invention.
  • FIG. 28 is a schematic side view showing a structure of forming a second gate according to an embodiment of the present invention.
  • FIG. 29 is a top plan view showing a second gate formed according to an embodiment of the present invention.
  • FIG. 30 is a side view showing a structure of a contact process and a back end interconnection process according to an embodiment of the present invention
  • FIG. 31 is a top view of a contact process and a back end interconnection process according to an embodiment of the present invention. Schematic;
  • FIG. 33 is a schematic structural view of forming a heterojunction on a substrate according to an embodiment of the present invention.
  • FIG. 34 is a schematic structural diagram of forming a second gate on a substrate according to an embodiment of the present invention.
  • FIG. 35 is a schematic structural diagram of adjusting energy band distribution in a channel region according to an embodiment of the present invention.
  • the embodiment of the present invention provides a tunneling field effect transistor 10.
  • the schematic diagram of the tunneling field effect transistor 10 is as shown in FIG. 2, and includes: a first doping region 101 and a second doping region 102 respectively disposed at two ends. a substrate 103; a channel region 104 having a fin-shaped protrusion formed on the substrate 103; a protective layer 105 formed on the substrate 103 on which the channel region 104 is formed; and a substrate 103 formed with the protective layer 105 formed thereon a channel etch hard mask layer structure 106 having a sidewall shape; a gate insulating dielectric layer 107 formed on the substrate 103 having the sidewall etched channel etch hard mask layer structure 106; A first gate 108 and a second gate 109 are formed on the substrate 103 of the insulating dielectric layer 107, and the first gate 108 and the second gate 109 are respectively located on both sides of the channel region 104; a first gate is formed An insulating material filling layer 110 is formed on the substrate
  • the tunneling field effect transistor has a substrate with a first doped region and a second doped region respectively disposed on both ends of the tunneling field effect transistor, and a fin is formed on the substrate.
  • a gate insulating dielectric layer is formed on the substrate of the shaped channel etching hard mask layer structure, and the first gate and the second gate are formed on the substrate on which the gate insulating dielectric layer is formed, and the first gate
  • the pole and the second gate are respectively located at two sides of the channel region, and the substrate on which the first gate and the second gate are formed is formed with a filling layer of an insulating material, and the first doped region and the second doped region are doped
  • the shape of the side wall refers to a shape formed by a process combining isotropic deposition and anisotropic etching.
  • the axial section of the channel region has a trapezoidal shape, and the length of the upper base of the trapezoid is smaller than the length of the lower base of the trapezoid.
  • the doping type of the channel region may be intrinsic doping or shallow doping.
  • the tunneling field effect transistor is an N-type tunneling field effect transistor
  • the first doped region is an N-type heavily doped drain region
  • the second doped region is a P-type heavily doped region.
  • the first gate is a control gate
  • the second gate is a bias gate
  • the doping type of the channel region is intrinsic doping or P-type shallow doping
  • the first doped region is an N-type heavily doped source region
  • the second doped region is a P-type heavily doped drain region
  • the first gate is a bias gate
  • the second gate is a control gate
  • the doping type of the channel region is either intrinsic doping or N-type shallow doping.
  • N-type heavy doping refers to the incorporation of pentavalent impurity elements (such as phosphorus, arsenic) and the higher dose of impurities incorporated.
  • P-type heavy doping refers to the incorporation of trivalent impurity elements (such as boron).
  • the dose of impurities incorporated is higher, intrinsic doping refers to the absence of any conductive elements, and shallow doping refers to the lower dose of impurities incorporated.
  • the tunneling field effect transistor 10 further includes a heterojunction 111.
  • a heterojunction 111 is formed on the substrate 103 on which the channel region 104 is formed, and two ends of the heterojunction 111 are respectively in contact with the protection layer 105 and the second doping region 102, and one of the heterojunctions 111 The side is in contact with the gate insulating dielectric layer 107.
  • the first doped region 101, the first gate 108, the second gate 109, the insulating material filling layer 110, and the sidewall-shaped channel etch hard mask layer structure 106 in FIG. 3 can refer to FIG. 2 .
  • the method for controlling the on state of the device is: the second gate is applied with a negative bias, so that the surface of the channel region near the second gate generates induced holes, and the first gate
  • the forward bias is applied such that induced electrons are generated on the surface of the channel region adjacent to the first gate.
  • the band-band tunneling current (on-state tunneling current) is positively correlated with the channel length, ie, the vertical channel height, and negatively correlated with the channel thickness.
  • the tunneling field effect transistor has two schemes for controlling the off state of the device.
  • the first scheme is that the first gate and the second gate are not biased (zero bias), and the channel region is two. The surface does not generate induced charges, there is a high barrier in the channel region, the channel region is closed, and there is no tunneling current.
  • This scheme is applied to devices with small subthreshold swing and N-type and P-type TFET interchangeable devices.
  • the second solution is that the bias of the second gate when the bias gate is kept in an on state is unchanged, and the first gate is biased. When the first gate bias is reset to zero, the surface of the channel region near the drain region induces electrons below a threshold, the channel region has a high barrier, and the device is turned off.
  • the fixed bias of the second gate can also be adjusted by adjusting the metal gate function of the second gate to reduce the bias voltage of the second gate and reduce the complexity of the peripheral circuit.
  • the tunneling field effect transistor has a substrate with a first doped region and a second doped region respectively disposed on both ends of the tunneling field effect transistor, and a fin is formed on the substrate.
  • a gate insulating dielectric layer is formed on the substrate of the shaped channel etching hard mask layer structure, and the first gate and the second gate are formed on the substrate on which the gate insulating dielectric layer is formed, and the first gate
  • the pole and the second gate are respectively located at two sides of the channel region, and the substrate on which the first gate and the second gate are formed is formed with a filling layer of an insulating material, and the first doped region and the second doped region are doped
  • the pre-set distance of the impurity region is
  • tunneling field effect transistor provided by the embodiment of the present invention can be applied to the fabrication of a fin field effect transistor device and the fabrication of a collision ionization MOSFET device.
  • Embodiments of the present invention provide a method for fabricating a tunneling field effect transistor. As shown in FIG. 4, the method includes:
  • Step 501 Form a protective layer on the substrate that completes the shallow trench isolation (English: Shallow Trench Isolation; STI) structure.
  • shallow trench isolation English: Shallow Trench Isolation; STI
  • Step 502 forming a trench etched hard mask layer structure in a sidewall shape on the substrate on which the protective layer is formed.
  • Step 503 forming a first sidewall of the channel on the substrate formed with the sidewall etched hard mask layer structure.
  • Step 504 forming a first oxide protective layer on the substrate on which the first sidewall of the trench is formed.
  • Step 505 forming a first dummy sidewall spacer on the substrate on which the first oxide protective layer is formed.
  • Step 506 implanting a first doped region at a side of the substrate on which the first dummy sidewall spacer is formed.
  • Step 507 forming a first sub-gate insulating dielectric layer on the substrate on which the first doped region is formed.
  • Step 508 forming a first gate on the substrate on which the first sub-gate insulating dielectric layer is formed.
  • Step 509 forming a first sub-insulating material filling layer on the substrate on which the first gate is formed.
  • Step 510 Form a second sidewall of the channel on the substrate formed with the first sub-insulating material filling layer, and the channel second sidewall forms a channel region with the first sidewall of the channel.
  • Step 511 forming a second oxide protective layer on the substrate on which the second sidewall of the trench is formed.
  • Step 512 forming a second dummy sidewall spacer on the substrate on which the second oxide protective layer is formed.
  • Step 513 implanting a second doped region at the other end of the substrate formed with the second dummy sidewall spacer, the doped region of the first doped region and the second doped region being separated by a predetermined distance, the preset distance It is larger than the width of the channel region and smaller than the length of the substrate.
  • Step 514 forming a second sub-gate insulating dielectric layer on the substrate on which the second doped region is formed, and the second sub-gate insulating dielectric layer and the first sub-gate insulating dielectric layer constitute a gate insulating dielectric layer.
  • Step 515 forming a second gate on the substrate on which the second sub-gate insulating dielectric layer is formed.
  • Step 516 forming a second sub-insulating material filling layer on the substrate formed with the second gate, and the second sub-insulating material filling layer and the first sub-insulating material filling layer composing the insulating material filling layer.
  • the method for fabricating a tunneling field effect transistor forms a protective layer, a sidewall-shaped channel etching hard mask layer structure, and a trench on the STI structure substrate by a sidewall transfer technique.
  • the second sidewall of the channel forms a channel region with the first sidewall of the channel, and the doped region of the first doped region and the second doped region are separated by a predetermined distance, and the second sub-gate insulating dielectric layer and the first A sub-gate insulating dielectric layer constitutes a gate insulating dielectric layer, and a second sub-insulating material filling layer and a first sub-insulating material filling layer constitute an insulating material filling layer, thereby realizing independent design of source and drain, compared with existing ones.
  • the EHB-TFET structure has a smaller off-state current, lower static power consumption, and a simpler process, thus improving versatility.
  • the axial section of the channel region has a trapezoidal shape, and the length of the upper base of the trapezoid is smaller than the length of the lower base of the trapezoid.
  • the doping type of the channel region is either intrinsic or shallow doping.
  • Step 502 can include: depositing sidewall material on the substrate on which the protective layer is formed; Forming an etch hard mask layer on the substrate of the sidewall material; forming a steep sidewall on the substrate on which the etch hard mask layer is formed; depositing a channel on the substrate on which the steep sidewall is formed Etching a hard mask layer material; forming a trench etched hard mask layer structure in a sidewall shape on a substrate on which a channel etch hard mask layer material is deposited.
  • the method may further include forming a first gate contact hole pad on the substrate on which the first gate is formed.
  • the method may further include: exposing the first gate contact hole pad on the substrate on which the first sub-insulating material filling layer is formed, forming the lining after exposing the first gate contact hole pad a substrate; the substrate after the first gate contact pad is exposed is etched back to form a substrate after etching; and the substrate after etching is subjected to oxide filling, oxide etching or planarization treatment, so that The first gate is insulated and the sidewall material is exposed.
  • Step 510 can include etching the exposed sidewall material to expose a protective layer formed on the STI structure substrate, and etching the exposed protective layer and the substrate to form a second sidewall of the trench.
  • the method may further include forming a second gate contact hole pad on the substrate on which the second gate is formed.
  • the method may further include: performing a contact process and a back end interconnection process on the substrate on which the second sub-insulating material filling layer is formed.
  • the method may further include forming a heterojunction on the substrate on which the channel region is formed.
  • the heterojunction can be made of a Group IV material or a Group III-V material.
  • the tunneling field effect transistor is an N-type tunneling field effect transistor
  • the first doped region is an N-type heavily doped drain region
  • the second doped region is a P-type heavily doped region.
  • the first gate is a control gate
  • the second gate is a bias gate
  • the doping type of the channel region is intrinsic doping or P-type shallow doping
  • the first doped region is an N-type heavily doped source region
  • the second doped region is a P-type heavily doped drain region
  • the first gate is a bias gate
  • the second gate is a control gate
  • the doping type of the channel region is either intrinsic doping or N-type shallow doping.
  • the method for fabricating a tunneling field effect transistor forms a protective layer, a sidewall-shaped channel etching hard mask layer structure, and a trench on the STI structure substrate by a sidewall transfer technique.
  • the second sidewall of the channel and the first sidewall of the channel Forming a channel region, the first doped region and the doped region of the second doped region are spaced apart by a predetermined distance, and the second sub-gate insulating dielectric layer and the first sub-gate insulating dielectric layer form a gate insulating dielectric layer,
  • the two sub-insulating material filling layer and the first sub-insulating material filling layer constitute an insulating material filling layer, and realize independent design of source and drain.
  • the off-state current is smaller, and the static power consumption is more. Low, the process is simpler, thus improving versatility.
  • Another embodiment of the present invention provides a method for fabricating a tunneling field effect transistor. As shown in FIG. 5, an N-type tunneling field effect transistor is taken as an example. The method includes:
  • Step 701 forming a protective layer on the substrate on which the STI structure is completed.
  • the substrate of the tunneling field effect transistor may be made of silicon (English: Silicon; abbreviation: Si), germanium (English: Germanium; abbreviation: Ge), or III-V material. Taking Si as an example, a layer of about 4 nm (nanometer) of oxide is deposited or grown as a protective layer on a substrate made of Si, which is also an etch stop layer and an interface protective layer.
  • Step 702 forming a channel etching hard mask layer structure in a sidewall shape on the substrate on which the protective layer is formed.
  • step 702 can include:
  • Step 7021 depositing a sidewall material on the substrate on which the protective layer is formed.
  • the substrate 103 is made of Si, and a layer of amorphous silicon (Amorphous Silicon; abbreviated as ⁇ -Si) of about 200 nm is deposited as the sidewall material 001 over the protective layer 105.
  • amorphous silicon Amorphous Silicon; abbreviated as ⁇ -Si
  • Step 7022 forming an etch hard mask layer on the substrate on which the sidewall material is deposited.
  • an oxide-nitride-oxide material (English: Oxide-Nitride-Oxide; abbreviated as ONO) structure is deposited over the sidewall material 001 as an etch hard mask layer 002.
  • FIG. 7 is a side view showing a protective layer 105, a sidewall material 001, and an etch hard mask layer 002.
  • FIG. 8 is a schematic plan view corresponding to FIG. As can be seen from FIG. 7, the protective layer 105 is over the substrate 103 made of Si, the sidewall material 001 is over the protective layer 105, and the etch hard mask layer 002 is over the sidewall material 001.
  • Step 7023 forming a steep sidewall on the substrate on which the etch hard mask layer is formed.
  • the substrate on which the etched hard mask layer is formed is subjected to pattern exposure, and the ONO structure is etched, and then the photoresist is removed and the ONO structure is used as a hard mask for ⁇ -Si etching.
  • the etching conditions are adjusted so that the side walls of the ⁇ -Si structure are steep and the substrate forms steep sidewalls.
  • 9 is a schematic side view showing a structure in which a steep sidewall is formed on a substrate on which an etch hard mask layer is formed
  • FIG. 10 is a schematic plan view corresponding to FIG. From As can be seen in Figure 10, the protective layer 105 has been etched.
  • Step 7024 depositing a channel etch hard mask layer material on the substrate on which the steep sidewalls are formed.
  • a low-pressure silicon nitride layer of a channel etching hard mask layer material having a thickness of less than 20 nm is deposited on the substrate (English: Low Pressure-Silicon Nitride; abbreviated as: LP-SiN). It should be noted that the thickness of the LP-SiN may be determined according to an actual process, which is not limited by the embodiment of the present invention.
  • Step 7025 forming a sidewall etched channel etch hard mask layer structure on the substrate on which the channel etch hard mask layer material is deposited.
  • step 7024 as shown in FIG. 11, after the LP-SiN is precipitated, the sidewall structure is etched by reactive ion etching (English: Reactive Ion Etching; RIE), that is, the trench etching of the sidewall shape is hard.
  • the mask layer structure 106 which serves as a hard mask structure for channel etching, needs to adjust the RIE etching conditions to optimize the sidewall morphology to make the sidewalls of the sidewalls steep.
  • 11 is a side view of a trench etched hard mask layer structure 106 forming a sidewall shape
  • FIG. 12 is a top plan view corresponding to FIG.
  • Step 703 forming a first sidewall of the channel on the substrate formed with the trench etched hard mask layer structure of the sidewall shape.
  • the channel-etched hard mask layer structure is used as a hard mask to perform dry etching of the drain end step to form a first sidewall of the trench, that is, The front side wall of the channel. Then, the first sidewall surface recovery process of the channel is performed to reduce the surface defect density caused by dry etching.
  • FIG. 13 is a schematic side view showing a first sidewall of the channel
  • FIG. 14 is a top plan view corresponding to FIG. 13, and 103 in FIG.
  • Step 704 implanting a first doped region at one end of the substrate on which the first sidewall of the channel is formed.
  • step 704 may include:
  • Step 7041 forming a first oxide protective layer on the substrate on which the first sidewall of the trench is formed.
  • a first oxide protective layer 003 is formed on a substrate on which a first sidewall of the trench is formed.
  • the first oxide protective layer 003 may be Oxide.
  • Step 7042 forming a first dummy sidewall spacer on the substrate on which the first oxide protective layer is formed.
  • a plasma-enhanced silicon nitride (Plasma Enhanced-Silicon Nitride; PE-SiN) material of about 20 nm is deposited on the substrate on which the first oxide protective layer is formed, that is, the first dummy side Wall grid 004.
  • the thickness of the side wall determines the doping distance of the drain end, so it is necessary to adjust the sidewall shape until the side wall is steep. It should be noted that the thickness of the PE-SiN can be determined according to an actual process, which is not limited by the embodiment of the present invention.
  • Step 7043 implanting a first doped region at a side of the substrate on which the first dummy sidewall spacer is formed.
  • the drain-side implantation is performed to form the first doping region 101.
  • arsenic or phosphorus may be implanted to form a drain end region having a drain end doping concentration of 5 ⁇ 10 19 cm ⁇ 3 to 2 ⁇ 10 20 cm ⁇ 3 and a junction depth of 15 to 25 nm, that is, the first doping.
  • the doping type of the impurity region is N-type heavily doped.
  • 16 is a schematic side view showing a first doped region
  • FIG. 17 is a top plan view corresponding to FIG. 16.
  • Step 705 forming a first sub-gate insulating dielectric layer on the substrate on which the first doped region is formed.
  • the substrate in step 705 is the substrate after removing the first dummy sidewall spacer PE-SiN.
  • the first dummy sidewall spacer 004 of FIG. 16 is etched away by boiling phosphoric acid, and the first oxide protective layer 003 is etched by a hydrofluoric acid solution to form a first sub-gate insulating dielectric layer 005.
  • the gate insulating dielectric layer may be a high-k insulating layer or a separate oxide layer.
  • Step 706 forming a first gate on the substrate on which the first sub-gate insulating dielectric layer is formed.
  • the first dummy sidewall spacer 004 of FIG. 16 is etched by boiling phosphoric acid and the first oxide protective layer 003 is etched by a hydrofluoric acid solution, and then an N-type CMOS standard polysilicon gate is performed.
  • Process or high-k metal gate process in this patent, a high-k metal gate process is taken as an example. Adjust the Fermi level or work function of the gate to bring it closer to the bottom of the conduction band. Then, RIE dry etching is performed to form a metal sidewall spacer structure, that is, the first gate electrode 108 in FIG.
  • FIG. 18 is a schematic side view showing a first gate
  • FIG. 19 is a top plan view corresponding to FIG. 18.
  • Step 707 forming a first sub-insulating material filling layer on the substrate on which the first gate is formed.
  • the oxide 1101 is filled on the substrate.
  • PE-Oxide or tetraethylorthosilicate (TEOS) may be filled.
  • 20 is a schematic side view showing a first sub-insulating material filling layer
  • FIG. 21 is a top plan view corresponding to FIG.
  • Step 708 processing the substrate formed with the first sub-insulating material filling layer to insulate the first gate and expose the sidewall material.
  • step 708 may include: forming a first sub-insulating material filling layer 1101 The first gate contact hole pad on the substrate is exposed to form a substrate after the first gate contact hole pad is exposed; and the exposed substrate of the first gate contact hole pad is etched back to form a back The engraved substrate; an oxide fill, an oxide etch or a planarization process on the etched substrate to insulate the first gate and expose the sidewall material.
  • the substrate on which the first sub-insulating material filling layer is formed may be planarized.
  • chemical mechanical polishing English: Chemical Mechanical Polishing; CMP
  • low temperature may be performed.
  • Oxidation + glass spin coating English: low-temperature oxidation + spin-on glass; referred to as: LTO + SOG
  • the first gate contact hole pad is exposed, and the first gate etch back is performed, so that the height of the CG PAD structure of the first gate is increased from the CMP plane, and the two gates are shorted. risks of.
  • FIG. 22 is a side view showing a structure of a substrate on which a first sub-insulating material filling layer is formed
  • FIG. 23 is a top plan view corresponding to FIG.
  • Step 709 forming a channel second sidewall on the substrate formed with the first sub-insulating material filling layer, and the channel second sidewall and the channel first sidewall forming a channel region.
  • the doping type of the channel region is either intrinsic or P-type shallow doping.
  • the second sidewall of the trench is the trench back sidewall. It should be noted that the axial section of the channel region has a trapezoidal shape, and the length of the upper base of the trapezoid is smaller than the length of the lower base of the trapezoid.
  • the step 709 may include: etching the exposed sidewall material, exposing the protective layer 105 on the STI structure, and etching the exposed protective layer 105 and the substrate 103 to form a second sidewall of the trench.
  • FIG. 24 is a schematic side view showing a second sidewall of the channel
  • FIG. 25 is a schematic plan view corresponding to FIG.
  • Step 710 implanting a second doped region at the other end of the substrate formed with the second sidewall of the channel, the first doped region and the doped region of the second doped region are separated by a preset distance, and the preset distance is greater than The width of the channel region is less than the length of the substrate.
  • step 710 may include: forming a second on the substrate on which the second sidewall of the channel is formed An oxide protective layer; a second dummy sidewall spacer formed on the substrate on which the second oxide protective layer is formed; and a second doped region is formed on the other end of the substrate on which the second dummy sidewall spacer is formed. It should be noted that the specific process of forming the second doping region method may be described corresponding to FIG. 15 .
  • a second oxide protective layer 006 is formed on the substrate on which the second sidewall of the trench is formed.
  • the second oxide protective layer 006 may be Oxide.
  • the same deposition and etching as the first dummy sidewall spacer of the drain end is performed to form a second dummy sidewall spacer 007, and then the source is implanted to form the second doped region 102.
  • boron atoms or difluoride may be used.
  • the boron is formed to form a source end region having a source doping concentration of 5 ⁇ 10 19 cm -3 to 2 ⁇ 10 20 cm -3 and a junction depth of 15 to 25 nm, that is, a doping type of the second doping region is P. Type heavily doped.
  • 26 is a schematic side view showing a second doped region
  • FIG. 27 is a schematic plan view corresponding to FIG.
  • the preset distance between the first doped region and the doped region of the second doped region may be adjusted according to the thicknesses of the first false sidewall grille and the second false sidewall grill.
  • Step 711 forming a second sub-gate insulating dielectric layer on the substrate on which the second doped region is formed, and the second sub-gate insulating dielectric layer and the first sub-gate insulating dielectric layer constitute a gate insulating dielectric layer.
  • the second dummy sidewall 007 and the second oxide protective layer 006 in FIG. 26 are wet etched to form a second sub-gate insulating dielectric layer 008.
  • the second sub-gate insulating dielectric layer 008 and the first sub-gate insulating dielectric layer constitute a gate insulating dielectric layer 107.
  • Step 712 forming a second gate on the substrate on which the second sub-gate insulating dielectric layer is formed.
  • the second dummy sidewall 007 of FIG. 26 is etched by boiling phosphoric acid and the second oxide protective layer 006 is etched by a hydrofluoric acid solution, and then an N-type CMOS standard polysilicon gate is performed.
  • Process or high-k metal gate process in this patent, a high-k metal gate process is taken as an example. Adjust the Fermi level or work function of the grid to bring it closer to the top of the valence band. Then, RIE dry etching is performed to form a metal side wall gate structure, that is, the second gate electrode 109 in FIG.
  • FIG. 28 is a schematic side view showing the structure of the second gate
  • FIG. 29 is a schematic plan view corresponding to FIG. 28.
  • Step 713 forming a second sub-insulating material filling layer on the substrate formed with the second gate, and the second sub-insulating material filling layer and the first sub-insulating material filling layer composing the insulating material filling layer.
  • the oxide 1102 is filled on the substrate, and for example, TEOS or LTO may be filled.
  • the second sub-insulating material filling layer 1102 and the first sub-insulating material filling layer constitute an insulating material filling layer 110.
  • Step 714 performing a contact process and a back end interconnection process on the substrate on which the second sub-insulating material filling layer is formed.
  • FIG. 30 is a schematic side view showing a contact process and a back end interconnection process
  • FIG. 31 is a top plan view corresponding to FIG.
  • step 714 It should be noted that the related art may be referred to in step 714, and details are not described herein again.
  • the method for fabricating the tunneling field effect transistor is described by taking an N-type tunneling field effect transistor as an example, wherein the first doped region is an N-type heavily doped drain region.
  • the second doped region is a P-type heavily doped source region, the first gate is a control gate, the second gate is a bias gate, and the doping type of the channel region is intrinsic doping Miscellaneous or P-type shallow doping.
  • the tunneling field effect transistor is a P-type tunneling field effect transistor
  • the first doped region is an N-type heavily doped source region
  • the second doped region is a P-type heavily doped drain region
  • first The gate is a bias gate
  • the second gate is a control gate
  • the doping type of the channel region is intrinsic doping or N-type shallow doping.
  • the specific fabrication process can refer to the fabrication process of the N-type tunneling field effect transistor.
  • the tunneling field effect transistor fabricated by the method for fabricating the tunneling field effect transistor has a scheme of controlling the on state of the device: the second gate is negatively biased, so that the channel surface near the second gate generates induced holes.
  • the first gate is forward biased such that induced surface electrons are generated near the channel surface of the first gate.
  • the tunneling field effect transistor controls the off state of the device in two ways.
  • the first scheme is that the first gate and the second gate are not biased (zero bias), and the two surfaces of the channel are not Generates induced charge, high barrier in the channel, channel is closed, no tunneling current, this scheme is applied to devices with small subthreshold swing, and N-type and P-type TFET interchangeable devices;
  • the solution is that the second gate is not biased when the bias gate is kept in an on state, and the first gate is biased.
  • the first gate bias is reset to zero, the channel surface near the drain terminal induces electrons below the threshold, the channel has a high barrier, and the device is turned off.
  • the fixed bias of the second gate can also be adjusted by adjusting the metal gate function of the second gate to reduce the bias voltage of the second gate and reduce the complexity of the peripheral circuit.
  • the tunneling mechanism of the tunneling field effect transistor fabricated by the fabrication method provided by the embodiment of the present invention is band tunneling, and the magnitude of the banding tunneling current is related to the area of the channel region, so Adjusting the height and length of the sidewall structure to adjust the area of the channel region, so that the banding tunneling current can be adjusted to achieve a high driving current; since the doping type of the channel region of the tunneling field effect transistor is With doping or shallow doping, there are fewer defects in the channel region, so defect-assisted tunneling can be suppressed, so that the subthreshold swing of the device can be reduced; due to the first doping region and the first doping region of the tunneling field effect transistor The two doped regions are far apart, and in the off state, the first gate and the second gate are both biased and the channel is closed, so the device has a very low band-band tunneling current; due to the tunneling field effect
  • the channel region of the transistor has a trapezoidal axial section, and the on-state current is determined
  • the method for fabricating a tunneling field effect transistor forms a protective layer, a sidewall-shaped channel etched hard mask layer structure, and a first side of the channel on the STI structure substrate.
  • the second sidewall of the channel forms a channel region with the first sidewall of the channel, and the doped region of the first doped region and the second doped region are separated by a predetermined distance, and the second sub-gate insulating dielectric layer and the first A sub-gate insulating dielectric layer constitutes a gate insulating dielectric layer, a second sub-insulating material filling layer and a first sub-insulating material filling layer constitute an insulating material filling layer, and a process of manufacturing a tunneling field effect transistor is realized by a sidewall transfer technology The process completes the independent design of the source and drain. Compared with the existing EHB-TFET structure, the off-state current is smaller, the static power consumption is lower, and the process is simpler, thus improving the versatility.
  • the embodiment of the present invention provides a method for fabricating a tunneling field effect transistor. As shown in FIG. 32, an N-type tunneling field effect transistor is taken as an example. The method includes:
  • Step 1001 forming a protective layer on the substrate on which the STI structure is completed.
  • step 100 For the specific process of step 1001, reference may be made to the specific process in step 701.
  • Step 1002 Form a channel etching hard mask layer structure in a sidewall shape on the substrate on which the protective layer is formed.
  • the specific process of step 1002 can refer to the specific process in step 702.
  • Step 1003 Form a first sidewall of the trench on the substrate formed with the trench etched hard mask layer structure of the sidewall shape.
  • step 1003 For the specific process of step 1003, refer to the specific process in step 703.
  • Step 1004 implanting a first doped region at a side of the substrate on which the first sidewall of the trench is formed.
  • the specific process of step 1004 can refer to the specific process in step 704.
  • Step 1005 forming a first sub-gate insulating dielectric layer on the substrate on which the first doped region is formed.
  • the specific process in step 1005 can refer to the specific process in step 705.
  • Step 1006 forming a first gate on the substrate on which the first sub-gate insulating dielectric layer is formed.
  • the specific process of step 1006 can refer to the specific process in step 706.
  • Step 1007 forming a first sub-insulating material filling layer on the substrate on which the first gate is formed.
  • the specific process in step 1007 can refer to the specific process in step 707.
  • Step 1008 Treat the substrate formed with the first sub-insulating material filling layer to insulate the first gate and expose the sidewall material.
  • step 1008 can be referred to the specific process in step 708.
  • Step 1009 forming a steep sidewall structure on the substrate on which the first sub-insulating material filling layer is formed.
  • Step 1010 Epitaxial heterojunction is formed on the substrate formed with the steep sidewall structure to form a heterojunction and a second sidewall of the trench, and the second sidewall of the trench forms a channel region with the first sidewall of the trench.
  • the sidewall formed after the addition of the heterojunction is the second sidewall of the channel, and the doping type of the channel region is either intrinsic or shallow doping.
  • the specific process in step 1010 can refer to the specific process in step 709.
  • a heterojunction 111 is formed on the substrate, and the heterojunction can be made of a group IV element or a group III-V element.
  • the substrate is a Group IV material
  • the heterojunction can be formed by other Group IV materials
  • the substrate material is a III-V material
  • the heterojunction can be formed by other Group III-V materials.
  • 101 is a first doped region
  • 103 is a substrate
  • 108 is a first gate
  • 105 is a protective layer
  • 106 is a channel-etched hard mask layer structure of a sidewall shape
  • 1101 is the first sub- The insulating material filling layer
  • 005 is a first sub-gate insulating dielectric layer.
  • Step 1011 forming a second doped region at the other end of the substrate formed with the heterojunction, the first doped region and the doped region of the second doped region are separated by a predetermined distance, and the preset distance is greater than the channel region The width is less than the length of the substrate.
  • the specific process in step 1011 can refer to the specific process in step 710.
  • Step 1012 Form a second sub-gate insulating dielectric layer on the substrate on which the second doped region is formed, and the second sub-gate insulating dielectric layer and the first sub-gate insulating dielectric layer form a gate insulating dielectric layer.
  • the specific process in step 1012 can refer to the specific process in step 711.
  • Step 1013 forming a second gate on the substrate on which the second sub-gate insulating dielectric layer is formed.
  • FIG. 34 is a schematic structural view of forming a second gate on the substrate 103 having the heterojunction 111 added thereto. Both ends of the heterojunction 111 are in contact with the protective layer 105 and the second doped region 102, and one side of the heterojunction 111 is in contact with the gate insulating dielectric layer 107.
  • 101 is a first doped region
  • 108 is a first gate
  • 109 is a second gate
  • 106 is a sidewall-shaped channel etch hard mask layer structure
  • 1101 is filled with a first sub-insulating material.
  • Floor is a schematic structural view of forming a second gate on the substrate 103 having the heterojunction 111 added thereto. Both ends of the heterojunction 111 are in contact with the protective layer 105 and the second doped region 102, and one side of the heterojunction 111 is in contact with the gate insulating dielectric layer 107.
  • 101 is a first doped region
  • 108 is a first gate
  • 109 is
  • the specific process in step 1013 can refer to the specific process in step 712.
  • Step 1014 Form a second sub-insulating material filling layer on the substrate on which the second gate is formed, and the second sub-insulating material filling layer and the first sub-insulating material filling layer constitute an insulating material filling layer.
  • the specific process in step 1014 can refer to the specific process in step 713.
  • Step 1015 Perform a contact process and a back end interconnection process on the substrate on which the second sub-insulating material filling layer is formed.
  • the specific process in step 1015 can refer to the specific process in step 714.
  • FIG. 3 is a schematic structural diagram of a tunneling field effect transistor after adding a heterojunction, that is, a schematic structural diagram of a heterojunction vertical electron hole double layer conductive tunneling transistor.
  • the band distribution in the channel region is adjusted, thereby increasing the on-state tunneling current of the device.
  • the main principle is: in the N-type TFET and the P-type TFET, a material with a narrow band gap is added as a heterojunction on the side of the negative biased gate. For example, it can be SiGe (silicon germanium). ).
  • the second gate is a bias gate, and a negative bias is applied, and the energy band of the channel region near the second gate surface is bent upward.
  • the valence band top 1031 Further bending upward to the position identified by 1032, thereby reducing the tunneling distance d of the carriers in the channel region, and increasing the on-state tunneling current.
  • the second gate is a control gate, and a negative bias is applied, and the energy band of the channel region near the second gate surface is bent upward, and when replaced by a SiGe layer, the valence band The top 1031 is further bent upward to reduce the channel region
  • the carrier tunneling distance d in the domain increases the on-state tunneling current.
  • 1033 is the conduction band bottom, P+ means P-type (hole type) heavily doped, and N+ means N-type (electron type) heavily doped.
  • the method for fabricating a tunneling field effect transistor forms a protective layer, a sidewall-shaped channel etched hard mask layer structure, and a first side of the channel on the STI structure substrate.
  • the second sidewall of the channel forms a channel region with the first sidewall of the channel, and the doped region of the first doped region and the second doped region are separated by a predetermined distance, and the second sub-gate insulating dielectric layer and the first A sub-gate insulating dielectric layer constitutes a gate insulating dielectric layer, a second sub-insulating material filling layer and a first sub-insulating material filling layer constitute an insulating material filling layer, and a process of manufacturing a tunneling field effect transistor is realized by a sidewall transfer technology
  • the process completes the independent design of the source and drain, and at the same time forms the energy band structure of the heterojunction structure to adjust the channel region.
  • the on-state tunneling current of the device is larger, and the off-state current is more. Small, static power consumption is lower, and the process is simpler, thus improving versatility.

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Abstract

提供了一种隧穿场效应晶体管及其制作方法，属于场效应晶体管技术领域。隧穿场效应晶体管（10）包括：两端分别设置有第一掺杂区域（101）和第二掺杂区域（102）的衬底（103）；衬底（103）上形成有鱼鳍形凸起的沟道区域（104），保护层（105），侧墙形状的沟道刻蚀硬掩膜层结构（106），栅极绝缘介质层（107）；形成有栅极绝缘介质层（107）的衬底（103）上形成有第一栅极（108）和第二栅极（109），且第一栅极（108）和第二栅极（109）分别位于沟道区域（104）的两侧；形成有第一栅极（108）和第二栅极（109）的衬底（103）上形成有绝缘材料填充层（110）；第一掺杂区域（101）与第二掺杂区域（102）的掺杂区域间隔预设距离，预设距离大于沟道区域的宽度且小于衬底（103）的长度。解决了EHB-TFET结构通用性较低的问题，实现了提高通用性的效果，用于控制器件的开启与关闭。

Description

隧穿场效应晶体管及其制作方法
本申请要求于2015年3月23日提交中国专利局、申请号为201510128390.5、发明名称为“隧穿场效应晶体管及其制作方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及场效应晶体管技术领域，特别涉及一种隧穿场效应晶体管及其制作方法。
背景技术
随着集成电路的发展，金属氧化物半导体场效应晶体管(英文：Metal Oxide Semiconductor field effect transistor；简称：MOSFET)的尺寸不断按照“摩尔定律”进行缩微，电路的动态功耗和静态功耗密度会增加，动态功耗和静态功耗可统称为功耗。为了降低互补金属氧化物半导体(英文：Complementary Metal Oxide Semiconductor；简称：CMOS)电路的功耗，可以降低MOSFET的驱动电压。降低MOSFET的驱动电压需要通过降低阈值电压来实现，但由于MOSFET亚阈值区开关特性受控于载流子扩散机制，其亚阈值摆幅的理论最小值为60mV/dec，即如果线性规律降低阈值电压60毫伏，关态电流会以指数规律增加一个数量级，从而导致CMOS电路的功耗增加。所以，需要引入一种基于新的开关态转换机制的、具有低功耗、低亚阈值摆幅等特性的器件来替代传统的MOSFET。
现有技术中，隧穿场效应晶体管(英文：Tunnel Field Effect Transistor；简称：TFET)是栅控反偏的P型掺杂-本征掺杂-N型掺杂结(简称：p-i-n结)的器件。通过栅控p-i-n结实现源端载流子与沟道载流子带带隧穿，控制器件开关态转换。在理论上，TFET可以实现低于60mV/dec的亚阈值摆幅，从而可以工作在较低的驱动电压中，进而可以降低静态功耗。TFET还具有在相同的阈值电压条件下能实现更低的关态电流，在相同的开态电流条件下具有更低的阈值电压等特点。电子空穴双层导电隧穿场效应晶体管(英文：Electron-Hole Bilayer- Tunnel Field Effect Transistor；简称：EHB-TFET) 作为一种TFET，具有极低亚阈值摆幅、高驱动电流等特性。图1为EHB-TFET的结构示意图，图1中P型重掺杂区域01为源极区域，N型重掺杂区域02为漏极区域，中间区域为非掺杂区域或轻掺杂区域。沟道区域上表面03为顶栅(又称为控制栅)，沟道区域下表面04为底栅(又称为偏置栅)。顶栅与漏极区域的掺杂区域交叠，顶栅与源极区域的掺杂区域分离。底栅与源极区域的掺杂区域交叠，底栅与漏极区域的掺杂区域分离。具体的，通过该EHB-TFET控制器件开启的原理为：通过静电感应，顶栅加正向电压，该正向电压称为控制电压，沟道区域上表面感应出N型载流子；底栅加负向电压，该负向电压称为偏置电压，沟道区域下表面感应出P型载流子。当沟道区域上表面和沟道区域下表面的感应载流子的数量增加时，能带弯曲，当能带(即沟道区域上表面的导带底和沟道区域下表面的价带顶)发生交叠时，沟道中央会发生载流子带带隧穿；通过该EHB-TFET控制器件关闭的原理为：顶栅加0伏电压，沟道区域上表面不产生感应载流子，沟道区域关闭。
但是由于EHB-TFET的结构导致其沟道区域的面积受到限制，要求漏极区域和源极区域的掺杂区域相距较近，从而使得关态电流较大，而关态电流越大，静态功耗就越高，同时，该结构在工艺上较难实现，因此，通用性较低。
发明内容
为了解决EHB-TFET的通用性较低的问题，本发明提供了一种隧穿场效应晶体管及其制作方法。所述技术方案如下：
第一方面，提供了一种隧穿场效应晶体管，所述隧穿场效应晶体管包括：
两端分别设置有第一掺杂区域和第二掺杂区域的衬底；
所述衬底上形成有鱼鳍形凸起的沟道区域；
形成有所述沟道区域的衬底上形成有保护层；
形成有所述保护层的衬底上形成有侧墙形状的沟道刻蚀硬掩膜层结构；
形成有所述侧墙形状的沟道刻蚀硬掩膜层结构的衬底上形成有栅极绝缘介质层；
形成有所述栅极绝缘介质层的衬底上形成有第一栅极和第二栅极，且所述第一栅极和所述第二栅极分别位于所述沟道区域的两侧；
形成有所述第一栅极和所述第二栅极的衬底上形成有绝缘材料填充层；
所述第一掺杂区域与所述第二掺杂区域的掺杂区域间隔预设距离，所述预设距离大于所述沟道区域的宽度且小于所述衬底的长度。
结合第一方面，在第一种可实现方式中，所述沟道区域的轴截面呈梯形，所述梯形的上底长度小于所述梯形的下底长度。
结合第一方面，在第二种可实现方式中，
所述沟道区域的掺杂类型为本征掺杂或浅掺杂。
结合第二种可实现方式，在第三种可实现方式中，
所述隧穿场效应晶体管还包括：异质结，
形成有所述沟道区域的衬底上形成有所述异质结，所述异质结的两端分别与所述保护层、所述第二掺杂区域接触，所述异质结的一侧与所述栅极绝缘介质层接触。
结合第一方面至第三种可实现方式中的任意一种，在第四种可实现方式中，
当所述隧穿场效应晶体管为N型隧穿场效应晶体管时，所述第一掺杂区域为N型重掺杂的漏极区域，所述第二掺杂区域为P型重掺杂的源极区域，所述第一栅极为控制栅，所述第二栅极为偏置栅，所述沟道区域的掺杂类型为本征掺杂或P型浅掺杂；
当所述隧穿场效应晶体管为P型隧穿场效应晶体管时，所述第一掺杂区域为N型重掺杂的源极区域，所述第二掺杂区域为P型重掺杂的漏极区域，所述第一栅极为偏置栅，所述第二栅极为控制栅，所述沟道区域的掺杂类型为本征掺杂或N型浅掺杂。
第二方面，提供了一种隧穿场效应晶体管的制作方法，所述方法包括：
在完成浅槽隔离STI的衬底上形成保护层；
在形成有所述保护层的衬底上形成侧墙形状的沟道刻蚀硬掩膜层结构；
在形成有所述侧墙形状的沟道刻蚀硬掩膜层结构的衬底上形成沟道第一侧壁；
在形成有所述沟道第一侧壁的衬底上形成第一氧化物保护层；
在形成有所述第一氧化物保护层的衬底上形成第一假侧墙栅；
在形成有所述第一假侧墙栅的衬底的一端注入形成第一掺杂区域；
在形成有所述第一掺杂区域的衬底上形成第一子栅极绝缘介质层；
在形成有所述第一子栅极绝缘介质层的衬底上形成第一栅极；
在形成有所述第一栅极的衬底上形成第一子绝缘材料填充层；
在形成有所述第一子绝缘材料填充层的衬底上形成沟道第二侧壁，所述沟道第二侧壁与所述沟道第一侧壁形成沟道区域；
在形成有所述沟道第二侧壁的衬底上形成第二氧化物保护层；
在形成有所述第二氧化物保护层的衬底上形成第二假侧墙栅；
在形成有所述第二假侧墙栅的衬底的另一端注入形成第二掺杂区域，所述第一掺杂区域与所述第二掺杂区域的掺杂区域间隔预设距离，所述预设距离大于所述沟道区域的宽度且小于所述衬底的长度；
在形成有所述第二掺杂区域的衬底上形成第二子栅极绝缘介质层，所述第二子栅极绝缘介质层与所述第一子栅极绝缘介质层组成栅极绝缘介质层；
在形成有所述第二子栅极绝缘介质层的衬底上形成第二栅极；
在形成有所述第二栅极的衬底上形成第二子绝缘材料填充层，所述第二子绝缘材料填充层与所述第一子绝缘材料填充层组成绝缘材料填充层。
结合第二方面，在第一种可实现方式中，
所述沟道区域的轴截面呈梯形，所述梯形的上底长度小于所述梯形的下底长度。
结合第二方面，在第二种可实现方式中，
所述沟道区域的掺杂类型为本征掺杂或浅掺杂。
结合第二方面，在第三种可实现方式中，所述在形成有所述保护层的衬底上形成侧墙形状的沟道刻蚀硬掩膜层结构，包括：
在形成有所述保护层的衬底上淀积侧壁材料；
在淀积有所述侧壁材料的衬底上形成刻蚀硬掩膜层；
在形成有所述刻蚀硬掩膜层的衬底上形成陡直侧壁；
在形成有所述陡直侧壁的衬底上淀积沟道刻蚀硬掩膜层材料；
在淀积有所述沟道刻蚀硬掩膜层材料的衬底上形成所述侧墙形状的沟道刻蚀硬掩膜层结构；
结合第二方面，在第四种可实现方式中，在所述在形成有所述第一子栅极绝缘介质层的衬底上形成第一栅极之后，所述方法还包括：
在形成有所述第一栅极的衬底上形成第一栅极接触孔焊盘。
结合第二方面，在第五种可实现方式中，在所述在形成有所述第一栅极的衬底上形成第一子绝缘材料填充层之后，所述方法还包括：
对形成有所述第一子绝缘材料填充层的衬底上的第一栅极接触孔焊盘进行暴露，形成所述第一栅极接触孔焊盘暴露后的衬底；
对所述第一栅极接触孔焊盘暴露后的衬底进行回刻，形成回刻后的衬底；
对所述回刻后的衬底进行氧化物填充、氧化物刻蚀或平坦化处理，使所述第一栅极绝缘，且使所述侧壁材料暴露。
结合第五种可实现方式，在第六种可实现方式中，所述在形成有所述第一子绝缘材料填充层的衬底上形成沟道第二侧壁，包括：
对所述暴露后的侧壁材料进行刻蚀，暴露出所述STI结构的衬底上形成的保护层；
对暴露的保护层及衬底进行刻蚀，形成所述沟道第二侧壁。
结合第四种可实现方式，在第七种可实现方式中，在所述在形成有所述第二子栅极绝缘介质层的衬底上形成第二栅极之后，所述方法还包括：
在形成有所述第二栅极的衬底上形成第二栅极接触孔焊盘。
结合第二方面，在第八种可实现方式中，在所述在形成有所述第二栅的衬底上形成第二子绝缘材料填充层之后，所述方法还包括：
对形成有所述第二子绝缘材料填充层的衬底进行接触工艺和后端互连工艺。
结合第二方面，在第九种可实现方式中，在所述在形成有所述沟道第二侧壁的衬底上形成第二氧化物保护层之前，所述方法还包括：
在形成有所述沟道区域的衬底上形成异质结。
结合第九种可实现方式，在第十种可实现方式中，
所述异质结由IV族元素或III-V族元素制成。
结合第二方面至第十种可实现方式中的任意一种，在第十一种可实现方式中，
当所述隧穿场效应晶体管为N型隧穿场效应晶体管时，所述第一掺杂区域为N型重掺杂的漏极区域，所述第二掺杂区域为P型重掺杂的源极区域，所述第一栅极为控制栅，所述第二栅极为偏置栅，所述沟道区域的掺杂类型为本征掺杂或P型浅掺杂；
当所述隧穿场效应晶体管为P型隧穿场效应晶体管时，所述第一掺杂区域为N型重掺杂的源极区域，所述第二掺杂区域为P型重掺杂的漏极区域， 所述第一栅极为偏置栅，所述第二栅极为控制栅，所述沟道区域的掺杂类型为本征掺杂或N型浅掺杂。
本发明提供了一种隧穿场效应晶体管及其制作方法，该隧穿场效应晶体管两端分别设置有第一掺杂区域和第二掺杂区域的衬底，衬底上形成有鱼鳍形凸起的沟道区域，形成有沟道区域的衬底上形成有保护层，形成有保护层的衬底上形成有侧墙形状的沟道刻蚀硬掩膜层结构，形成有侧墙形状的沟道刻蚀硬掩膜层结构的衬底上形成有栅极绝缘介质层，形成有栅极绝缘介质层的衬底上形成有第一栅极和第二栅极，且第一栅极和第二栅极分别位于沟道区域的两侧，形成有第一栅极和第二栅极的衬底上形成有绝缘材料填充层，第一掺杂区域与第二掺杂区域的掺杂区域间隔预设距离，实现源漏极独立设计，相较于现有的EHB-TFET结构，关态电流更小，静态功耗更低，工艺更简单，因此，提高了通用性。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明实施例提供的一种EHB-TFET的结构示意图；
图2是本发明实施例提供的一种隧穿场效应晶体管的结构示意图；
图3是本发明实施例提供的又一种隧穿场效应晶体管的结构示意图；
图4是本发明实施例提供的一种隧穿场效应晶体管的制作方法的流程图；
图5是本发明实施例提供的另一种隧穿场效应晶体管的制作方法的流程图；
图6是本发明实施例提供的一种形成侧墙形状的沟道刻蚀硬掩膜层结构方法的流程图；
图7是本发明实施例提供的一种形成保护层、侧壁材料及刻蚀硬掩膜层的侧视结构示意图；
图8是本发明实施例提供的一种形成保护层、侧壁材料及刻蚀硬掩膜层 的俯视结构示意图；
图9是本发明实施例提供的一种形成陡直侧壁的侧视结构示意图；
图10是本发明实施例提供的一种形成陡直侧壁的俯视结构示意图；
图11是本发明实施例提供的一种淀积沟道刻蚀硬掩膜层材料的侧视结构示意图；
图12是本发明实施例提供的一种淀积沟道刻蚀硬掩膜层材料的俯视结构示意图；
图13是本发明实施例提供的一种形成沟道第一侧壁的侧视结构示意图；
图14是本发明实施例提供的一种形成沟道第一侧壁的俯视结构示意图；
图15是本发明实施例提供的一种形成第一掺杂区域方法的流程图；
图16是本发明实施例提供的一种形成第一掺杂区域的侧视结构示意图；
图17是本发明实施例提供的一种形成第一掺杂区域的俯视结构示意图；
图18是本发明实施例提供的一种形成第一栅极的侧视结构示意图；
图19是本发明实施例提供的一种形成第一栅极的俯视结构示意图；
图20是本发明实施例提供的一种形成第一子绝缘材料填充层的侧视结构示意图；
图21是本发明实施例提供的一种形成第一子绝缘材料填充层的俯视结构示意图；
图22是本发明实施例提供的一种对形成有第一子绝缘材料填充层的衬底进行处理的侧视结构示意图；
图23是本发明实施例提供的一种对形成有第一子绝缘材料填充层的衬底进行处理的俯视结构示意图；
图24是本发明实施例提供的一种形成沟道第二侧壁的侧视结构示意图；
图25是本发明实施例提供的一种形成沟道第二侧壁的俯视结构示意图；
图26是本发明实施例提供的一种形成第二掺杂区域的侧视结构示意图；
图27是本发明实施例提供的一种形成第二掺杂区域的俯视结构示意图；
图28是本发明实施例提供的一种形成第二栅极的侧视结构示意图；
图29是本发明实施例提供的一种形成第二栅极的俯视结构示意图；
图30是本发明实施例提供的一种进行接触工艺和后端互连工艺的侧视结构示意图；
图31是本发明实施例提供的一种进行接触工艺和后端互连工艺的俯视 结构示意图；
图32是本发明实施例提供的又一种隧穿场效应晶体管的制作方法的流程图；
图33是本发明实施例提供的一种在衬底上形成异质结的结构示意图；
图34是本发明实施例提供的一种在衬底上形成第二栅极的结构示意图；
图35是本发明实施例提供的一种调节沟道区域中能带分布的结构示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明实施方式作进一步地详细描述。
本发明实施例提供一种隧穿场效应晶体管10，该隧穿场效应晶体管10的结构示意图如图2所示，包括：两端分别设置有第一掺杂区域101和第二掺杂区域102的衬底103；衬底103上形成有鱼鳍形凸起的沟道区域104；形成有沟道区域104的衬底103上形成有保护层105；形成有保护层105的衬底103上形成有侧墙形状的沟道刻蚀硬掩膜层结构106；形成有侧墙形状的沟道刻蚀硬掩膜层结构106的衬底103上形成有栅极绝缘介质层107；形成有栅极绝缘介质层107的衬底103上形成有第一栅极108和第二栅极109，且第一栅极108和第二栅极109分别位于沟道区域104的两侧；形成有第一栅极108和第二栅极109的衬底103上形成有绝缘材料填充层110；第一掺杂区域101与第二掺杂区域102的掺杂区域间隔预设距离，该预设距离大于沟道区域104的宽度且小于衬底103的长度。
综上所述，本发明实施例提供的隧穿场效应晶体管，该隧穿场效应晶体管两端分别设置有第一掺杂区域和第二掺杂区域的衬底，衬底上形成有鱼鳍形凸起的沟道区域，形成有沟道区域的衬底上形成有保护层，形成有保护层的衬底上形成有侧墙形状的沟道刻蚀硬掩膜层结构，形成有侧墙形状的沟道刻蚀硬掩膜层结构的衬底上形成有栅极绝缘介质层，形成有栅极绝缘介质层的衬底上形成有第一栅极和第二栅极，且第一栅极和第二栅极分别位于沟道区域的两侧，形成有第一栅极和第二栅极的衬底上形成有绝缘材料填充层，第一掺杂区域与第二掺杂区域的掺杂区域间隔预设距离，实现源漏极独立设计，相较于现有的EHB-TFET结构，关态电流更小，静态功耗更低，工艺更 简单，因此，提高了通用性。
需要说明的是，侧墙形状指的是各向同性淀积与各向异性刻蚀相结合的工艺方法形成的形状。
进一步的，沟道区域的轴截面呈梯形，且梯形的上底长度小于梯形的下底长度。
沟道区域的掺杂类型可以为本征掺杂或浅掺杂。
需要补充说明的是，当隧穿场效应晶体管为N型隧穿场效应晶体管时，第一掺杂区域为N型重掺杂的漏极区域，第二掺杂区域为P型重掺杂的源极区域，第一栅极为控制栅，第二栅极为偏置栅，沟道区域的掺杂类型为本征掺杂或P型浅掺杂；当隧穿场效应晶体管为P型隧穿场效应晶体管时，第一掺杂区域为N型重掺杂的源极区域，第二掺杂区域为P型重掺杂的漏极区域，第一栅极为偏置栅，第二栅极为控制栅，沟道区域的掺杂类型为本征掺杂或N型浅掺杂。N型重掺杂指的是掺入的是五价杂质元素(如磷、砷)且掺入的杂质剂量较高，P型重掺杂指的是掺入的是三价杂质元素(如硼)且掺入的杂质剂量较高，本征掺杂指的是未掺入任何导电元素，浅掺杂指的是掺入的杂质剂量较低。需要说明的是，当隧穿场效应晶体管为N型隧穿场效应晶体管或P型隧穿场效应晶体管时，漏极区域和源极区域的掺杂类型可互换，控制栅和偏置栅对应互换，同时控制栅和偏置栅的栅极材料也需要对应互换。
如图3所示，该隧穿场效应晶体管10还包括：异质结111。具体的，形成有沟道区域104的衬底103上形成有异质结111，该异质结111的两端分别与保护层105、第二掺杂区域102接触，该异质结111的一侧与栅极绝缘介质层107接触。此外，图3中的第一掺杂区域101、第一栅极108、第二栅极109、绝缘材料填充层110、及侧墙形状的沟道刻蚀硬掩膜层结构106可以参考图2中的相关说明。
本发明实施例提供的隧穿场效应晶体管，控制器件开态的方案为：第二栅极加负向偏压，使得靠近第二栅极的沟道区域表面产生感应空穴，第一栅极加正向偏压，使得靠近第一栅极的沟道区域表面产生感应电子。当沟道区域两个表面的能带弯曲达到一定程度时，电子浓度与空穴浓度达到一定条件，则沿着沟道区域中央产生带带隧穿。带带隧穿电流(开态隧穿电流)大小与沟道长度即竖直沟道高度正相关，与沟道的厚度负相关。
相应的，该隧穿场效应晶体管，控制器件关态的方案有两种，第一种方案是第一栅极和第二栅极都不加偏压(零偏压)，沟道区域两个表面不产生感应电荷，沟道区域存在高势垒，沟道区域关闭，无隧穿电流，这种方案应用于亚阈值摆幅较小的器件，及N型和P型TFET可互换的器件；第二种方案是第二栅极为偏置栅保持开态时的偏置不变，第一栅极进行偏置变化。当第一栅极偏置归零时，靠近漏极区域的沟道区域表面感应电子低于阈值，沟道区域存在高势垒，器件关闭。而第二栅极的固定偏置还可以通过调节第二栅极的金属栅功函数进行调节，降低第二栅极的偏置电压，减小外围电路的复杂度。
综上所述，本发明实施例提供的隧穿场效应晶体管，该隧穿场效应晶体管两端分别设置有第一掺杂区域和第二掺杂区域的衬底，衬底上形成有鱼鳍形凸起的沟道区域，形成有沟道区域的衬底上形成有保护层，形成有保护层的衬底上形成有侧墙形状的沟道刻蚀硬掩膜层结构，形成有侧墙形状的沟道刻蚀硬掩膜层结构的衬底上形成有栅极绝缘介质层，形成有栅极绝缘介质层的衬底上形成有第一栅极和第二栅极，且第一栅极和第二栅极分别位于沟道区域的两侧，形成有第一栅极和第二栅极的衬底上形成有绝缘材料填充层，第一掺杂区域与第二掺杂区域的掺杂区域间隔预设距离，实现源漏极独立设计，相较于现有的EHB-TFET结构，关态电流更小，静态功耗更低，工艺更简单，因此，提高了通用性。
需要说明的是，本发明实施例提供的隧穿场效应晶体管，可以应用到鳍形场效应晶体管器件制作和碰撞电离MOSFET器件制作中。
本发明实施例提供一种隧穿场效应晶体管的制作方法，如图4所示，该方法包括：
步骤501、在完成浅槽隔离(英文：Shallow Trench Isolation；简称：STI)结构的衬底上形成保护层。
步骤502、在形成有保护层的衬底上形成侧墙形状的沟道刻蚀硬掩膜层结构。
步骤503、在形成有侧墙形状的沟道刻蚀硬掩膜层结构的衬底上形成沟道第一侧壁。
步骤504、在形成有沟道第一侧壁的衬底上形成第一氧化物保护层。
步骤505、在形成有第一氧化物保护层的衬底上形成第一假侧墙栅。
步骤506、在形成有第一假侧墙栅的衬底的一端注入形成第一掺杂区域。
步骤507、在形成有第一掺杂区域的衬底上形成第一子栅极绝缘介质层。
步骤508、在形成有第一子栅极绝缘介质层的衬底上形成第一栅极。
步骤509、在形成有第一栅极的衬底上形成第一子绝缘材料填充层。
步骤510、在形成有第一子绝缘材料填充层的衬底上形成沟道第二侧壁，沟道第二侧壁与沟道第一侧壁形成沟道区域。
步骤511、在形成有沟道第二侧壁的衬底上形成第二氧化物保护层。
步骤512、在形成有第二氧化物保护层的衬底上形成第二假侧墙栅。
步骤513、在形成有第二假侧墙栅的衬底的另一端注入形成第二掺杂区域，第一掺杂区域与第二掺杂区域的掺杂区域间隔预设距离，该预设距离大于沟道区域的宽度且小于衬底的长度。
步骤514、在形成有第二掺杂区域的衬底上形成第二子栅极绝缘介质层，第二子栅极绝缘介质层与第一子栅极绝缘介质层组成栅极绝缘介质层。
步骤515、在形成有第二子栅极绝缘介质层的衬底上形成第二栅极。
步骤516、在形成有第二栅极的衬底上形成第二子绝缘材料填充层，第二子绝缘材料填充层与第一子绝缘材料填充层组成绝缘材料填充层。
综上所述，本发明实施例提供的隧穿场效应晶体管的制作方法，通过侧墙转移技术在STI结构衬底上形成保护层、侧墙形状的沟道刻蚀硬掩膜层结构、沟道第一侧壁、第一氧化物保护层、第一假侧墙栅、第一掺杂区域、第一子栅极绝缘介质层、第一栅极、第一子绝缘材料填充层、沟道第二侧壁、第二氧化物保护层、第二假侧墙栅、第二掺杂区域、第二子栅极绝缘介质层、第二栅极及第二子绝缘材料填充层。其中，沟道第二侧壁与沟道第一侧壁形成沟道区域，第一掺杂区域与第二掺杂区域的掺杂区域间隔预设距离，第二子栅极绝缘介质层与第一子栅极绝缘介质层组成栅极绝缘介质层，第二子绝缘材料填充层与第一子绝缘材料填充层组成绝缘材料填充层，实现了源漏极的独立设计，相较于现有的EHB-TFET结构，关态电流更小，静态功耗更低，工艺更简单，因此，提高了通用性。
进一步的，沟道区域的轴截面呈梯形，梯形的上底长度小于梯形的下底长度。沟道区域的掺杂类型为本征掺杂或浅掺杂。
步骤502可以包括：在形成有保护层的衬底上淀积侧壁材料；在淀积有 侧壁材料的衬底上形成刻蚀硬掩膜层；在形成有刻蚀硬掩膜层的衬底上形成陡直侧壁；在形成有陡直侧壁的衬底上淀积沟道刻蚀硬掩膜层材料；在淀积有沟道刻蚀硬掩膜层材料的衬底上形成侧墙形状的沟道刻蚀硬掩膜层结构。
在步骤508之后，该方法还可以包括：在形成有第一栅极的衬底上形成第一栅极接触孔焊盘。
在步骤509之后，该方法还可以包括：对形成有第一子绝缘材料填充层的衬底上的第一栅极接触孔焊盘进行暴露，形成第一栅极接触孔焊盘暴露后的衬底；对第一栅极接触孔焊盘暴露后的衬底进行回刻，形成回刻后的衬底；对回刻后的衬底进行氧化物填充、氧化物刻蚀或平坦化处理，使第一栅极绝缘，且使侧壁材料暴露。
步骤510可以包括：对暴露的侧壁材料进行刻蚀，暴露出STI结构的衬底上形成的保护层；对暴露的保护层及衬底进行刻蚀，形成沟道第二侧壁。
在步骤515之后，该方法还可以包括：在形成有第二栅极的衬底上形成第二栅极接触孔焊盘。
在步骤516之后，该方法还可以包括：对形成有第二子绝缘材料填充层的衬底进行接触工艺和后端互连工艺。
在步骤511之前，该方法还可以包括：在形成有沟道区域的衬底上形成异质结。示例的，该异质结可以由IV族材料或III-V族材料制成。
需要补充说明的是，当隧穿场效应晶体管为N型隧穿场效应晶体管时，第一掺杂区域为N型重掺杂的漏极区域，第二掺杂区域为P型重掺杂的源极区域，第一栅极为控制栅，第二栅极为偏置栅，沟道区域的掺杂类型为本征掺杂或P型浅掺杂；当隧穿场效应晶体管为P型隧穿场效应晶体管时，第一掺杂区域为N型重掺杂的源极区域，第二掺杂区域为P型重掺杂的漏极区域，第一栅极为偏置栅，第二栅极为控制栅，沟道区域的掺杂类型为本征掺杂或N型浅掺杂。
综上所述，本发明实施例提供的隧穿场效应晶体管的制作方法，通过侧墙转移技术在STI结构衬底上形成保护层、侧墙形状的沟道刻蚀硬掩膜层结构、沟道第一侧壁、第一氧化物保护层、第一假侧墙栅、第一掺杂区域、第一子栅极绝缘介质层、第一栅极、第一子绝缘材料填充层、沟道第二侧壁、第二氧化物保护层、第二假侧墙栅、第二掺杂区域、第二子栅极绝缘介质层、第二栅极及第二子绝缘材料填充层。其中，沟道第二侧壁与沟道第一侧壁形 成沟道区域，第一掺杂区域与第二掺杂区域的掺杂区域间隔预设距离，第二子栅极绝缘介质层与第一子栅极绝缘介质层组成栅极绝缘介质层，第二子绝缘材料填充层与第一子绝缘材料填充层组成绝缘材料填充层，实现了源漏极的独立设计，相较于现有的EHB-TFET结构，关态电流更小，静态功耗更低，工艺更简单，因此，提高了通用性。
本发明实施例提供另一种隧穿场效应晶体管的制作方法，如图5所示，以N型隧穿场效应晶体管为例，该方法包括：
步骤701、在完成STI结构的衬底上形成保护层。
隧穿场效应晶体管的衬底可以由硅(英文：Silicon；简称：Si)、锗(英文：Germanium；简称：Ge)、或III-V材料制成。以Si为例，在由Si制成的衬底上沉淀或者生长一层约4nm(纳米)的氧化物作为保护层，该保护层亦为刻蚀阻挡层和界面保护层。
步骤702、在形成有保护层的衬底上形成侧墙形状的沟道刻蚀硬掩膜层结构。
具体的，如图6所示，步骤702可以包括：
步骤7021、在形成有保护层的衬底上淀积侧壁材料。
假设衬底103由Si制成，在形成有保护层105的上方淀积一层约200nm的非晶硅(英文：Amorphous Silicon；简称：α-Si)作为侧壁材料001。
步骤7022、在淀积有侧壁材料的衬底上形成刻蚀硬掩膜层。
根据步骤7022，在侧壁材料001上方沉积氧化物-氮化物-氧化物材料(英文：Oxide-Nitride-Oxide；简称：ONO)结构作为刻蚀硬掩膜层002。
图7为形成的保护层105、侧壁材料001及刻蚀硬掩膜层002的侧视结构示意图，图8为图7对应的俯视结构示意图。从图7中可以看出，保护层105位于由Si制成的衬底103之上，侧壁材料001位于保护层105之上，刻蚀硬掩膜层002位于侧壁材料001之上。
步骤7023、在形成有刻蚀硬掩膜层的衬底上形成陡直侧壁。
对形成有刻蚀硬掩膜层的衬底进行图形曝光，并对ONO结构进行刻蚀，然后去掉光刻胶以ONO结构为硬掩膜进行α-Si刻蚀。调节刻蚀条件，使α-Si结构侧壁陡直，衬底形成陡直侧壁。图9为在形成有刻蚀硬掩膜层的衬底上形成陡直侧壁的侧视结构示意图，图10为图9对应的俯视结构示意图。从 图10中可以看出，已经刻蚀出保护层105。
步骤7024、在形成有陡直侧壁的衬底上淀积沟道刻蚀硬掩膜层材料。
如图11所示，在衬底上淀积厚度小于20nm的沟道刻蚀硬掩膜层材料低压氮化硅(英文：Low Pressure-Silicon Nitride；简称：LP-SiN)。需要说明的是，LP-SiN的厚度可以根据实际工艺确定，本发明实施例对此不作限定。
步骤7025、在淀积有沟道刻蚀硬掩膜层材料的衬底上形成侧墙形状的沟道刻蚀硬掩膜层结构。
根据步骤7024，如图11所示，沉淀了LP-SiN之后，通过反应离子刻蚀(英文：Reactive Ion Etching；简称：RIE)刻蚀出侧墙结构，即侧墙形状的沟道刻蚀硬掩膜层结构106，该结构作为沟道刻蚀的硬掩膜结构，需要调节RIE刻蚀条件进行侧墙形貌的优化，使侧墙侧壁陡直。图11为形成侧墙形状的沟道刻蚀硬掩膜层结构106的侧视结构示意图，图12为图11对应的俯视结构示意图。
步骤703、在形成有侧墙形状的沟道刻蚀硬掩膜层结构的衬底上形成沟道第一侧壁。
在步骤702的基础上，如图13所示，以侧墙形状的沟道刻蚀硬掩膜层结构为硬掩膜进行漏端台阶的干法刻蚀，形成沟道第一侧壁，即沟道正面侧壁。然后进行沟道第一侧壁表面恢复处理，降低干法刻蚀造成的表面缺陷密度。图13为形成沟道第一侧壁的侧视结构示意图，图14为图13对应的俯视结构示意图，图14中的103为衬底。
步骤704、在形成有沟道第一侧壁的衬底的一端注入形成第一掺杂区域。
具体的，如图15所示，步骤704可以包括：
步骤7041、在形成有沟道第一侧壁的衬底上形成第一氧化物保护层。
如图16所示，在形成有沟道第一侧壁的衬底上形成第一氧化物保护层003，示例的，第一氧化物保护层003可以为Oxide。
步骤7042、在形成有第一氧化物保护层的衬底上形成第一假侧墙栅。
如图16所示，在形成有第一氧化物保护层的衬底上沉积约20nm的等离子增强氮化硅(英文：Plasma Enhanced-Silicon Nitride；简称：PE-SiN)材料，即第一假侧墙栅004。该侧墙厚度决定漏端掺杂距离，所以需要调节侧墙形貌直至侧墙陡直。需要说明的是，PE-SiN的厚度可以根据实际工艺确定，本发明实施例对此不作限定。
步骤7043、在形成有第一假侧墙栅的衬底的一端注入形成第一掺杂区域。
如图16所示，形成第一假侧墙栅004之后，进行漏端注入形成第一掺杂区域101。示例的，可以注入砷元素或磷元素，形成漏端掺杂浓度为5×1019cm-3～2×1020cm-3，结深为15～25nm的漏端区域，也就是第一掺杂区域的掺杂类型为N型重掺杂。图16为形成第一掺杂区域的侧视结构示意图，图17为图16对应的俯视结构示意图。
步骤705、在形成有第一掺杂区域的衬底上形成第一子栅极绝缘介质层。
需要说明的是，步骤705中的衬底为去除第一假侧墙栅PE-SiN之后的衬底。如图18所示，通过沸腾的磷酸腐蚀掉图16中的第一假侧墙栅004，通过氢氟酸溶液腐蚀第一氧化物保护层003，形成第一子栅极绝缘介质层005。需要说明的是，栅极绝缘介质层可以为高k绝缘层，也可以为单独的氧化物层。
步骤706、在形成有第一子栅极绝缘介质层的衬底上形成第一栅极。
结合步骤705，如图18所示，通过沸腾的磷酸腐蚀掉图16中的第一假侧墙栅004及通过氢氟酸溶液腐蚀第一氧化物保护层003，然后进行N型CMOS标准多晶硅栅工艺或高k金属栅工艺，本专利中以高k金属栅工艺为例。调节栅极的费米能级或功函数，使其靠近导带底。然后进行RIE干法刻蚀，形成金属侧墙栅结构，即图18中的第一栅极108。需要说明的是，在进行干法刻蚀之前需要进行一次光刻工艺，制作第一栅极接触孔焊盘结构，也就是从俯视图19中看到的CG(英文：contact to gate)PAD(接触焊盘)结构。图18为形成第一栅极的侧视结构示意图，图19为图18对应的俯视结构示意图。
步骤707、在形成有第一栅极的衬底上形成第一子绝缘材料填充层。
如图20所示，在衬底上进行氧化物1101填充，示例的，可以填充PE-Oxide或者正硅酸乙酯(英文：tetraethylorthosilicate；简称：TEOS)。图20为形成第一子绝缘材料填充层的侧视结构示意图，图21为图20对应的俯视结构示意图。
步骤708、对形成有第一子绝缘材料填充层的衬底进行处理，使第一栅极绝缘，且使侧壁材料暴露。
具体的，步骤708可以包括：对形成有第一子绝缘材料填充层1101的 衬底上的第一栅极接触孔焊盘进行暴露，形成第一栅极接触孔焊盘暴露后的衬底；对第一栅极接触孔焊盘暴露后的衬底进行回刻，形成回刻后的衬底；对回刻后的衬底进行氧化物填充、氧化物刻蚀或平坦化处理，使第一栅极绝缘，且使侧壁材料暴露。
如图22所示，可以对形成有第一子绝缘材料填充层的衬底进行平坦化处理，示例的，可以进行化学机械研磨(英文：Chemical Mechanical Polishing；简称：CMP)工艺，也可以进行低温氧化+玻璃旋涂(英文：low-temperature oxidation+spin-on glass；简称：LTO+SOG)工艺。经过平坦化处理后，暴露出第一栅极接触孔焊盘，进行第一栅极回刻，使第一栅极的CG PAD结构的高度离CMP平面距离增大，降低两个栅极短接的风险。完成回刻后，进行PE-Oxide沉积，填充第一栅极回刻过程中CG PAD上方的孔结构。然后通过RIE刻蚀工艺、CMP或者LTO+SOG等平坦化工艺，暴露出侧壁材料001。图23中的H为进行回刻与填充处理的位置。图22为对形成有第一子绝缘材料填充层的衬底进行处理的侧视结构示意图，图23为图22对应的俯视结构示意图。
步骤709、在形成有第一子绝缘材料填充层的衬底上形成沟道第二侧壁，沟道第二侧壁与沟道第一侧壁形成沟道区域。
沟道区域的掺杂类型为本征掺杂或P型浅掺杂。
沟道第二侧壁即为沟道背面侧壁。需要说明的是，沟道区域的轴截面呈梯形，梯形的上底长度小于梯形的下底长度。
具体的，步骤709可以包括：对暴露的侧壁材料进行刻蚀，暴露出STI结构上的保护层105，对暴露的保护层105及衬底103进行刻蚀，形成沟道第二侧壁。
如图24所示，湿法腐蚀图22中的侧壁材料001，自停止于衬底氧化物保护层上，然后通过干法腐蚀进行与沟道第一侧壁腐蚀条件相同的沟道第二侧壁腐蚀。图24为形成沟道第二侧壁的侧视结构示意图，图25为图24对应的俯视结构示意图。
步骤710、在形成有沟道第二侧壁的衬底的另一端注入形成第二掺杂区域，第一掺杂区域与第二掺杂区域的掺杂区域间隔预设距离，预设距离大于沟道区域的宽度且小于衬底的长度。
具体的，步骤710可以包括：在形成有沟道第二侧壁的衬底上形成第二 氧化物保护层；在形成有第二氧化物保护层的衬底上形成第二假侧墙栅；在形成有第二假侧墙栅的衬底的另一端注入形成第二掺杂区域。需要说明的是，形成第二掺杂区域方法的具体过程可以对应参考图15进行说明。
如图26所示，在形成有沟道第二侧壁的衬底上形成第二氧化物保护层006，示例的，第二氧化物保护层006可以为Oxide。接着进行与漏端第一假侧墙栅相同的淀积与刻蚀，形成第二假侧墙栅007，然后进行源端注入形成第二掺杂区域102，示例的，可以硼原子或二氟化硼，形成源端掺杂浓度为5×1019cm-3～2×1020cm-3，结深为15～25nm的源端区域，也就是第二掺杂区域的掺杂类型为P型重掺杂。图26为形成第二掺杂区域的侧视结构示意图，图27为图26对应的俯视结构示意图。
需要说明的是，第一掺杂区域与第二掺杂区域的掺杂区域间隔的预设距离可以根据第一假侧墙栅和第二假侧墙栅的厚度进行调节。
步骤711、在形成有第二掺杂区域的衬底上形成第二子栅极绝缘介质层，第二子栅极绝缘介质层与第一子栅极绝缘介质层组成栅极绝缘介质层。
如图28所示，湿法腐蚀图26中的第二假侧墙栅007及第二氧化物保护层006，形成第二子栅极绝缘介质层008。第二子栅极绝缘介质层008与第一子栅极绝缘介质层组成栅极绝缘介质层107。
步骤712、在形成有第二子栅极绝缘介质层的衬底上形成第二栅极。
结合步骤711，如图28所示，通过沸腾的磷酸腐蚀掉图26中的第二假侧墙栅007及通过氢氟酸溶液腐蚀第二氧化物保护层006，然后进行N型CMOS标准多晶硅栅工艺或高k金属栅工艺，本专利中以高k金属栅工艺为例。调节栅极的费米能级或功函数，使其靠近价带顶。然后进行RIE干法刻蚀，形成金属侧墙栅结构，即图28中的第二栅极109。需要说明的是，在进行干法刻蚀之前需要进行一次光刻工艺，制作第二栅极接触孔焊盘结构，也就是从俯视图29中看到的CG PAD结构。图28为形成第二栅极的侧视结构示意图，图29为图28对应的俯视结构示意图。
步骤713、在形成有第二栅极的衬底上形成第二子绝缘材料填充层，第二子绝缘材料填充层与第一子绝缘材料填充层组成绝缘材料填充层。
如图30所示，在衬底上进行氧化物1102填充，示例的，可以填充TEOS或LTO。第二子绝缘材料填充层1102与第一子绝缘材料填充层组成绝缘材料填充层110。
步骤714、对形成有第二子绝缘材料填充层的衬底进行接触工艺和后端互连工艺。
如图30所示，进行氧化物填充后，完成硅的金属化、进行接触工艺和后端互连工艺等。图30为进行接触工艺和后端互连工艺的侧视结构示意图，图31为图30对应的俯视结构示意图。
需要说明的是，步骤714可以参考现有相关技术，在此不再赘述。
进一步的，需要补充说明的是，该隧穿场效应晶体管的制作方法是以N型隧穿场效应晶体管为例进行说明的，其中第一掺杂区域为N型重掺杂的漏极区域，所述第二掺杂区域为P型重掺杂的源极区域，所述第一栅极为控制栅，所述第二栅极为偏置栅，所述沟道区域的掺杂类型为本征掺杂或P型浅掺杂。
如果隧穿场效应晶体管为P型隧穿场效应晶体管，那么第一掺杂区域为N型重掺杂的源极区域，第二掺杂区域为P型重掺杂的漏极区域，第一栅极为偏置栅，第二栅极为控制栅，沟道区域的掺杂类型为本征掺杂或N型浅掺杂。其具体制作过程可以参考N型隧穿场效应晶体管的制作过程。
该隧穿场效应晶体管的制作方法制作的隧穿场效应晶体管，控制器件开态的方案为：第二栅极加负向偏压，使得靠近第二栅极的沟道表面产生感应空穴，第一栅极加正向偏压，使得靠近第一栅极的沟道表面产生感应电子。当沟道两个表面能带弯曲达到一定程度时，电子与空穴浓度达到一定条件，则沿着沟道中央产生带带隧穿。带带隧穿电流大小与沟道长度即竖直沟道高度正相关，与沟道的厚度负相关。
相应的，该隧穿场效应晶体管控制器件关态的方案有两种，第一种方案是第一栅极和第二栅极都不加偏压(零偏压)，沟道两个表面不产生感应电荷，沟道存在高势垒，沟道关闭，无隧穿电流，这种方案应用于亚阈值摆幅较小的器件，及N型和P型TFET可互换的器件；第二种方案是第二栅极为偏置栅保持开态时的偏置不变，第一栅极进行偏置变化。当第一栅极偏置归零时，靠近漏端的沟道表面感应电子低于阈值，沟道存在高势垒，器件关闭。而第二栅极的固定偏置还可以通过调节第二栅极的金属栅功函数进行调节，降低第二栅极的偏置电压，减小外围电路的复杂度。
由于本发明实施例提供的制作方法制作的隧穿场效应晶体管的隧穿机制为带带隧穿，而带带隧穿电流的大小与沟道区域的面积相关，所以可以通 过调节侧墙结构的高度和长度来调节沟道区域的面积，从而可以调节带带隧穿电流大小，以便实现高驱动电流；由于该隧穿场效应晶体管的沟道区域的掺杂类型为本征掺杂或浅掺杂，沟道区域的缺陷较少，所以可以抑制缺陷辅助隧穿，从而可以减小器件的亚阈值摆幅；由于该隧穿场效应晶体管的第一掺杂区域和第二掺杂区域相距较远，而且在关态时，第一栅极和第二栅极都处于零偏，沟道关闭，所以器件具有极低的带带隧穿电流；由于该隧穿场效应晶体管的沟道区域的轴截面呈梯形，而开态电流决定于沟道厚度较薄的沟道顶端，器件阈值电压决定于沟道厚度较厚的沟道底端，而且梯形结构可以降低沟道两侧台阶高度变化引起的器件特性的波动。
综上所述，本发明实施例提供的隧穿场效应晶体管的制作方法，通过在STI结构衬底上形成保护层、侧墙形状的沟道刻蚀硬掩膜层结构、沟道第一侧壁、第一氧化物保护层、第一假侧墙栅、第一掺杂区域、第一子栅极绝缘介质层、第一栅极、第一子绝缘材料填充层、沟道第二侧壁、第二氧化物保护层、第二假侧墙栅、第二掺杂区域、第二子栅极绝缘介质层、第二栅极及第二子绝缘材料填充层。其中，沟道第二侧壁与沟道第一侧壁形成沟道区域，第一掺杂区域与第二掺杂区域的掺杂区域间隔预设距离，第二子栅极绝缘介质层与第一子栅极绝缘介质层组成栅极绝缘介质层，第二子绝缘材料填充层与第一子绝缘材料填充层组成绝缘材料填充层，通过侧墙转移技术实现了制作隧穿场效应晶体管的工艺流程，完成了源漏极的独立设计，相较于现有的EHB-TFET结构，关态电流更小，静态功耗更低，工艺更简单，因此，提高了通用性。
本发明实施例提供又一种隧穿场效应晶体管的制作方法，如图32所示，以N型隧穿场效应晶体管为例，该方法包括：
步骤1001、在完成STI结构的衬底上形成保护层。
步骤1001的具体过程可以参考步骤701中的具体过程。
步骤1002、在形成有保护层的衬底上形成侧墙形状的沟道刻蚀硬掩膜层结构。
步骤1002的具体过程可以参考步骤702中的具体过程。
需要说明的是，在形成有陡直侧壁的衬底上淀积沟道刻蚀硬掩膜层材料的过程中，在衬底上可以淀积约10nm的LP-SiN作为沟道刻蚀硬掩膜层材 料。
步骤1003、在形成有侧墙形状的沟道刻蚀硬掩膜层结构的衬底上形成沟道第一侧壁。
步骤1003的具体过程可以参考步骤703中的具体过程。
步骤1004、在形成有沟道第一侧壁的衬底的一端注入形成第一掺杂区域。
步骤1004的具体过程可以参考步骤704中的具体过程。
步骤1005、在形成有第一掺杂区域的衬底上形成第一子栅极绝缘介质层。
步骤1005的具体过程可以参考步骤705中的具体过程。
步骤1006、在形成有第一子栅极绝缘介质层的衬底上形成第一栅极。
步骤1006的具体过程可以参考步骤706中的具体过程。
步骤1007、在形成有第一栅极的衬底上形成第一子绝缘材料填充层。
步骤1007的具体过程可以参考步骤707中的具体过程。
步骤1008、对形成有第一子绝缘材料填充层的衬底进行处理，使第一栅极绝缘，且使侧壁材料暴露。
步骤1008的具体过程可以参考步骤708中的具体过程。
步骤1009、在形成有第一子绝缘材料填充层的衬底上形成陡直侧壁结构。
为了较好地形成异质结，需要在衬底上先形成陡直侧壁结构。
步骤1010、在形成有陡直侧壁结构的衬底上外延异质结，形成异质结和沟道第二侧壁，沟道第二侧壁与沟道第一侧壁形成沟道区域。
添加异质结之后形成的侧壁为沟道第二侧壁，沟道区域的掺杂类型为本征掺杂或浅掺杂。步骤1010的具体过程可以参考步骤709中的具体过程。
如图33所示，在衬底上形成异质结111，该异质结可以由IV族元素或III-V族元素制成。当衬底为IV族材料时，则可以通过其他IV族材料形成异质结，当衬底材料为III-V材料时，则可以通过其他III-V族材料形成异质结。通过在衬底上增加异质结，调节能带结构，增加器件开态隧穿电流。图33中，101为第一掺杂区域，103为衬底，108为第一栅极，105为保护层，106为侧墙形状的沟道刻蚀硬掩膜层结构，1101为第一子绝缘材料填充层，005为第一子栅极绝缘介质层。
步骤1011、在形成有异质结的衬底的另一端注入形成第二掺杂区域，第一掺杂区域与第二掺杂区域的掺杂区域间隔预设距离，预设距离大于沟道区域的宽度且小于衬底的长度。
步骤1011的具体过程可以参考步骤710中的具体过程。
步骤1012、在形成有第二掺杂区域的衬底上形成第二子栅极绝缘介质层，第二子栅极绝缘介质层与第一子栅极绝缘介质层组成栅极绝缘介质层。
步骤1012的具体过程可以参考步骤711中的具体过程。
步骤1013、在形成有第二子栅极绝缘介质层的衬底上形成第二栅极。
具体的，图34为在增加有异质结111的衬底103上形成第二栅极的结构示意图。异质结111的两端分别与保护层105、第二掺杂区域102接触，异质结111的一侧与栅极绝缘介质层107接触。图34中，101为第一掺杂区域，108为第一栅极，109为第二栅极，106为侧墙形状的沟道刻蚀硬掩膜层结构，1101为第一子绝缘材料填充层。
步骤1013的具体过程可以参考步骤712中的具体过程。
步骤1014、在形成有第二栅极的衬底上形成第二子绝缘材料填充层，第二子绝缘材料填充层与第一子绝缘材料填充层组成绝缘材料填充层。
步骤1014的具体过程可以参考步骤713中的具体过程。
步骤1015、对形成有第二子绝缘材料填充层的衬底进行接触工艺和后端互连工艺。
步骤1015的具体过程可以参考步骤714中的具体过程。
具体的，图3为增加异质结之后的隧穿场效应晶体管的结构示意图，即异质结竖直电子空穴双层导电隧穿晶体管的结构示意图。
如图35所示，通过增加异质结，调节沟道区域中能带分布，从而增加器件开态隧穿电流。主要原理为：在N型TFET与P型TFET中，在加负向偏压的栅极一侧增加一层禁带宽度较窄的材料作为异质结，示例的，可以为SiGe(锗化硅)。在N型TFET中，器件开启时，第二栅极为偏置栅，加负向偏压，沟道区域靠近第二栅极表面的能带向上弯曲，当换为SiGe层时，价带顶1031进一步向上弯曲至1032标识的位置，从而减小沟道区域中载流子的隧穿距离d，增加开态隧穿电流。同样的，在P型TFET中，器件开启时，第二栅极为控制栅，加负向偏压，沟道区域靠近第二栅极表面的能带向上弯曲，当换为SiGe层时，价带顶1031进一步向上弯曲，从而减小沟道区 域中载流子隧穿距离d，增加开态隧穿电流。图35中的1033为导带底，P+表示P型(空穴型)重掺杂，N+表示N型(电子型)重掺杂。
综上所述，本发明实施例提供的隧穿场效应晶体管的制作方法，通过在STI结构衬底上形成保护层、侧墙形状的沟道刻蚀硬掩膜层结构、沟道第一侧壁、第一氧化物保护层、第一假侧墙栅、第一掺杂区域、第一子栅极绝缘介质层、第一栅极、第一子绝缘材料填充层、沟道第二侧壁、第二氧化物保护层、第二假侧墙栅、第二掺杂区域、第二子栅极绝缘介质层、第二栅极及第二子绝缘材料填充层。其中，沟道第二侧壁与沟道第一侧壁形成沟道区域，第一掺杂区域与第二掺杂区域的掺杂区域间隔预设距离，第二子栅极绝缘介质层与第一子栅极绝缘介质层组成栅极绝缘介质层，第二子绝缘材料填充层与第一子绝缘材料填充层组成绝缘材料填充层，通过侧墙转移技术实现了制作隧穿场效应晶体管的工艺流程，完成了源漏极的独立设计，同时形成异质结结构调节沟道区域的能带结构，相较于现有的EHB-TFET结构，器件开态隧穿电流更大，关态电流更小，静态功耗更低，工艺更简单，因此，提高了通用性。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (17)

  1. 一种隧穿场效应晶体管，其特征在于，所述隧穿场效应晶体管包括：
    两端分别设置有第一掺杂区域和第二掺杂区域的衬底；
    所述衬底上形成有鱼鳍形凸起的沟道区域；
    形成有所述沟道区域的衬底上形成有保护层；
    形成有所述保护层的衬底上形成有侧墙形状的沟道刻蚀硬掩膜层结构；
    形成有所述侧墙形状的沟道刻蚀硬掩膜层结构的衬底上形成有栅极绝缘介质层；
    形成有所述栅极绝缘介质层的衬底上形成有第一栅极和第二栅极，且所述第一栅极和所述第二栅极分别位于所述沟道区域的两侧；
    形成有所述第一栅极和所述第二栅极的衬底上形成有绝缘材料填充层；
    所述第一掺杂区域与所述第二掺杂区域的掺杂区域间隔预设距离，所述预设距离大于所述沟道区域的宽度且小于所述衬底的长度。
  2. 根据权利要求1所述的隧穿场效应晶体管，其特征在于，
    所述沟道区域的轴截面呈梯形，所述梯形的上底长度小于所述梯形的下底长度。
  3. 根据权利要求1所述的隧穿场效应晶体管，其特征在于，
    所述沟道区域的掺杂类型为本征掺杂或浅掺杂。
  4. 根据权利要求3所述的隧穿场效应晶体管，其特征在于，所述隧穿场效应晶体管还包括：异质结，
    形成有所述沟道区域的衬底上形成有所述异质结，所述异质结的两端分别与所述保护层、所述第二掺杂区域接触，所述异质结的一侧与所述栅极绝缘介质层接触。
  5. 根据权利要求1至4任意一项权利要求所述的隧穿场效应晶体管，其特征在于，
    当所述隧穿场效应晶体管为N型隧穿场效应晶体管时，所述第一掺杂区域为N型重掺杂的漏极区域，所述第二掺杂区域为P型重掺杂的源极区域， 所述第一栅极为控制栅，所述第二栅极为偏置栅，所述沟道区域的掺杂类型为本征掺杂或P型浅掺杂；
    当所述隧穿场效应晶体管为P型隧穿场效应晶体管时，所述第一掺杂区域为N型重掺杂的源极区域，所述第二掺杂区域P型重掺杂的漏极区域，所述第一栅极为偏置栅，所述第二栅极为控制栅，所述沟道区域的掺杂类型为本征掺杂或N型浅掺杂。
  6. 一种隧穿场效应晶体管的制作方法，其特征在于，所述方法包括：
    在完成浅槽隔离STI结构的衬底上形成保护层；
    在形成有所述保护层的衬底上形成侧墙形状的沟道刻蚀硬掩膜层结构；
    在形成有所述侧墙形状的沟道刻蚀硬掩膜层结构的衬底上形成沟道第一侧壁；
    在形成有所述沟道第一侧壁的衬底上形成第一氧化物保护层；
    在形成有所述第一氧化物保护层的衬底上形成第一假侧墙栅；
    在形成有所述第一假侧墙栅的衬底的一端注入形成第一掺杂区域；
    在形成有所述第一掺杂区域的衬底上形成第一子栅极绝缘介质层；
    在形成有所述第一子栅极绝缘介质层的衬底上形成第一栅极；
    在形成有所述第一栅极的衬底上形成第一子绝缘材料填充层；
    在形成有所述第一子绝缘材料填充层的衬底上形成沟道第二侧壁，所述沟道第二侧壁与所述沟道第一侧壁形成沟道区域；
    在形成有所述沟道第二侧壁的衬底上形成第二氧化物保护层；
    在形成有所述第二氧化物保护层的衬底上形成第二假侧墙栅；
    在形成有所述第二假侧墙栅的衬底的另一端注入形成第二掺杂区域，所述第一掺杂区域与所述第二掺杂区域的掺杂区域间隔预设距离，所述预设距离大于所述沟道区域的宽度且小于所述衬底的长度；
    在形成有所述第二掺杂区域的衬底上形成第二子栅极绝缘介质层，所述第二子栅极绝缘介质层与所述第一子栅极绝缘介质层组成栅极绝缘介质层；
    在形成有所述第二子栅极绝缘介质层的衬底上形成第二栅极；
    在形成有所述第二栅极的衬底上形成第二子绝缘材料填充层，所述第二子绝缘材料填充层与所述第一子绝缘材料填充层组成绝缘材料填充层。
  7. 根据权利要求6所述的方法，其特征在于，
    所述沟道区域的轴截面呈梯形，所述梯形的上底长度小于所述梯形的下底长度。
  8. 根据权利要求6所述的方法，其特征在于，
    所述沟道区域的掺杂类型为本征掺杂或浅掺杂。
  9. 根据权利要求6所述的方法，其特征在于，所述在形成有所述保护层的的衬底上形成侧墙形状的沟道刻蚀硬掩膜层结构，包括：
    在形成有所述保护层的衬底上淀积侧壁材料；
    在淀积有所述侧壁材料的衬底上形成刻蚀硬掩膜层；
    在形成有所述刻蚀硬掩膜层的衬底上形成陡直侧壁；
    在形成有所述陡直侧壁的衬底上淀积沟道刻蚀硬掩膜层材料；
    在淀积有所述沟道刻蚀硬掩膜层材料的衬底上形成所述侧墙形状的沟道刻蚀硬掩膜层结构。
  10. 根据权利要求6所述的方法，其特征在于，在所述在形成有所述第一子栅极绝缘介质层的衬底上形成第一栅极之后，所述方法还包括：
    在形成有所述第一栅极的衬底上形成第一栅极接触孔焊盘。
  11. 根据权利要求10所述的方法，其特征在于，在所述在形成有所述第一栅极的衬底上形成第一子绝缘材料填充层之后，所述方法还包括：
    对形成有所述第一子绝缘材料填充层的衬底上的第一栅极接触孔焊盘进行暴露，形成所述第一栅极接触孔焊盘暴露后的衬底；
    对所述第一栅极接触孔焊盘暴露后的衬底进行回刻，形成回刻后的衬底；
    对所述回刻后的衬底进行氧化物填充、氧化物刻蚀或平坦化处理，使所述第一栅极绝缘，且使所述侧壁材料暴露。
  12. 根据权利要求11所述的方法，其特征在于，所述在形成有所述第一子绝缘材料填充层的衬底上形成沟道第二侧壁，包括：
    对所述暴露的侧壁材料进行刻蚀，暴露出所述STI结构的衬底上形成的保护层；
    对暴露的保护层及所述衬底进行刻蚀，形成所述沟道第二侧壁。
  13. 根据权利要求10所述的方法，其特征在于，在所述在形成有所述第二子栅极绝缘介质层的衬底上形成第二栅极之后，所述方法还包括：
    在形成有所述第二栅极的衬底上形成第二栅极接触孔焊盘。
  14. 根据权利要求6所述的方法，其特征在于，在所述在形成有所述第二栅极的衬底上形成第二子绝缘材料填充层之后，所述方法还包括：
    对形成有所述第二子绝缘材料填充层的衬底进行接触工艺和后端互连工艺。
  15. 根据权利要求6所述的方法，其特征在于，在所述在形成有所述沟道第二侧壁的衬底上形成第二氧化物保护层之前，所述方法还包括：
    在形成有所述沟道区域的衬底上形成异质结。
  16. 根据权利要求15所述的方法，其特征在于，
    所述异质结由IV族元素或III-V族元素制成。
  17. 根据权利要求6至16任意一项权利要求所述的方法，其特征在于，
    当所述隧穿场效应晶体管为N型隧穿场效应晶体管时，所述第一掺杂区域为N型重掺杂的漏极区域，所述第二掺杂区域为P型重掺杂的源极区域，所述第一栅极为控制栅，所述第二栅极为偏置栅，所述沟道区域的掺杂类型为本征掺杂或P型浅掺杂；
    当所述隧穿场效应晶体管为P型隧穿场效应晶体管时，所述第一掺杂区域为N型重掺杂的源极区域，所述第二掺杂区域为P型重掺杂的漏极区域，所述第一栅极为偏置栅，所述第二栅极为控制栅，所述沟道区域的掺杂类型为本征掺杂或N型浅掺杂。
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