CN108122976B - 半导体结构及其形成方法、以及sram - Google Patents

半导体结构及其形成方法、以及sram Download PDF

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CN108122976B
CN108122976B CN201611072328.XA CN201611072328A CN108122976B CN 108122976 B CN108122976 B CN 108122976B CN 201611072328 A CN201611072328 A CN 201611072328A CN 108122976 B CN108122976 B CN 108122976B
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pull
region
forming
doped
fin
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CN108122976A (zh
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李勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN201611072328.XA priority Critical patent/CN108122976B/zh
Priority to EP17203763.2A priority patent/EP3327788B1/en
Priority to US15/824,830 priority patent/US10256243B2/en
Publication of CN108122976A publication Critical patent/CN108122976A/zh
Priority to US16/277,254 priority patent/US20190181146A1/en
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Abstract

一种半导体结构及其形成方法、以及SRAM，所述方法包括：提供基底，包括衬底以及位于衬底上分立的鳍部，衬底包括相邻上拉晶体管区和下拉晶体管区；形成横跨鳍部且覆盖部分鳍部顶部和侧壁表面的栅极结构；在上拉晶体管区栅极结构两侧鳍部内形成上拉掺杂外延层；在下拉晶体管区栅极结构一侧鳍部内形成第一下拉掺杂区，用于与相邻上拉掺杂外延层相连；在下拉晶体管区栅极结构另一侧鳍部内形成第二下拉掺杂区，第二下拉掺杂区采用对鳍部进行离子掺杂的非外延层方式形成。相比通过形成下拉外延层以形成第二下拉掺杂区的方案，本发明可以避免因鳍部之间距离过近的原因，而出现第二下拉掺杂区与上拉掺杂外延层发生桥接的问题。

Description

半导体结构及其形成方法、以及SRAM
技术领域
本发明涉及半导体领域，尤其涉及一种半导体结构及其形成方法、以及SRAM。
背景技术
在半导体制造中，随着超大规模集成电路的发展趋势，集成电路特征尺寸持续减小。为了适应特征尺寸的减小，MOSFET的沟道长度也相应不断缩短。然而，随着器件沟道长度的缩短，器件源极与漏极间的距离也随之缩短，因此栅极对沟道的控制能力随之变差，栅极电压夹断(pinch off)沟道的难度也越来越大，使得亚阈值漏电(subthresholdleakage)现象，即所谓的短沟道效应(SCE：short-channel effects)更容易发生。
因此，为了更好的适应特征尺寸的减小，半导体工艺逐渐开始从平面MOSFET向具有更高功效的三维立体式的晶体管过渡，如鳍式场效应管(FinFET)。FinFET中，栅至少可以从两侧对超薄体(鳍部)进行控制，与平面MOSFET相比，栅极对沟道的控制能力更强，能够很好的抑制短沟道效应；且FinFET相对于其他器件，与现有集成电路制造具有更好的兼容性。
但是，现有技术形成的鳍式场效应管的电学性能有待提高。
发明内容
本发明解决的问题是提供一种半导体结构及其形成方法、以及SRAM，优化半导体器件的电学性能。
为解决上述问题，本发明提供一种半导体结构的形成方法，包括：提供基底，所述基底包括衬底以及位于所述衬底上分立的鳍部，所述衬底包括相邻的上拉晶体管区和下拉晶体管区；形成横跨所述鳍部的栅极结构，且所述栅极结构覆盖部分鳍部顶部表面和侧壁表面；在所述上拉晶体管区栅极结构两侧的鳍部内形成上拉掺杂外延层；在所述下拉晶体管区栅极结构一侧的鳍部内形成第一下拉掺杂区，所述第一下拉掺杂区用于与相邻上拉掺杂外延层相连；在所述下拉晶体管区栅极结构另一侧的鳍部内形成第二下拉掺杂区，且所述第二下拉掺杂区采用对所述鳍部进行离子掺杂的非外延层方式形成。
相应的，本发明还提供半导体结构，包括：基底，包括衬底以及位于所述衬底上分立的鳍部，所述衬底包括相邻的上拉晶体管区和下拉晶体管区；横跨所述鳍部的栅极结构，且所述栅极结构覆盖部分鳍部顶部表面和侧壁表面；上拉掺杂外延层，位于所述上拉晶体管区栅极结构两侧的鳍部内；第一下拉掺杂区，位于所述下拉晶体管区栅极结构一侧的鳍部内，所述第一下拉掺杂区用于与相邻上拉掺杂外延层相连；第二下拉掺杂区，位于所述下拉晶体管区栅极结构另一侧的鳍部内，且所述第二下拉掺杂区为非外延层掺杂区。
相应的，本发明还提供一种SRAM，包括前述半导体结构。
与现有技术相比，本发明的技术方案具有以下优点：
本发明在下拉晶体管区栅极结构另一侧的鳍部内形成第二下拉掺杂区，且所述第二下拉掺杂区采用对所述鳍部进行离子掺杂的非外延层方式形成，也就是说，所述下拉晶体管区栅极结构另一侧的鳍部内未形成下拉外延层；由于所述下拉晶体管区与上拉晶体管区相邻，因此相比通过在下拉晶体管区栅极结构另一侧的鳍部内形成下拉外延层以形成第二下拉掺杂区的方案，本发明可以避免因所述下拉晶体管区鳍部和上拉晶体管区鳍部之间距离过近的原因，而出现所述第二下拉掺杂区与所述上拉掺杂外延层发生桥接的问题。
本发明提供一种半导体结构，所述半导体结构包括第二下拉掺杂区，所述第二下拉掺杂区位于所述下拉晶体管区栅极结构另一侧鳍部内，且所述第二下拉掺杂区为非外延层掺杂区，也就是说，所述下拉晶体管区栅极结构另一侧鳍部内不具有下拉外延层；由于所述下拉晶体管区与上拉晶体管区相邻，因此相比所述下拉晶体管区栅极结构另一侧鳍部内具有下拉外延层的方案，本发明所述半导体结构可以避免因所述下拉晶体管区鳍部和上拉晶体管区鳍部之间距离过近的原因，而出现所述第二下拉掺杂区与所述上拉掺杂外延层发生桥接的问题。
本发明还提供一种SRAM，由于所述SRAM中，位于所述下拉晶体管区栅极结构另一侧鳍部内的第二下拉掺杂区为非外延层掺杂区，也就是说，所述下拉晶体管区栅极结构另一侧鳍部内不具有下拉外延层；由于所述下拉晶体管区与上拉晶体管区相邻，因此相比所述下拉晶体管区栅极结构另一侧鳍部内具有下拉外延层的方案，本发明所述半导体结构可以避免因所述下拉晶体管区鳍部和上拉晶体管区鳍部之间距离过近的原因，而出现所述第二下拉掺杂区与所述上拉掺杂外延层发生桥接的问题。
附图说明
图1是一种半导体结构的形成方法对应的俯视图；
图2是采用图1所述形成方法所形成半导体结构的电镜图；
图3至图16是本发明半导体结构的形成方法一实施例中各步骤对应结构示意图；
图17至图19是本发明半导体结构一实施例的结构示意图。
具体实施方式
由背景技术可知，半导体器件的电学性能仍有待提高。结合一种半导体结构的形成方法分析其原因。
参考图1，示出了一种半导体结构的形成方法对应的俯视图(仅示意出衬底和鳍部)，所述形成方法包括：提供用于形成SRAM(静态随机随机存储器)的基底，所述基底包括衬底10以及位于所述衬底10上分立的鳍部(未标示)，所述衬底10包括相邻的上拉晶体管区(未标示)和下拉晶体管区(未标示)，所述下拉晶体管区包括第一下拉晶体管区(未标示)和第二下拉晶体管区(未标示)，且所述第一下拉晶体管区与所述上拉晶体管区相邻，其中位于所述上拉晶体管区衬底10上的鳍部为第一鳍部11，位于所述第一下拉晶体管区衬底10上的鳍部为第二鳍部12，位于所述第二下拉晶体管区衬底10上的鳍部为第三鳍部13；形成横跨所述鳍部的栅极结构，且所述栅极结构覆盖部分鳍部顶部表面和侧壁表面；在所述上拉晶体管区栅极结构两侧的第一鳍部11内形成上拉掺杂外延层(图未示)；在所述第一下拉晶体管区栅极结构两侧的第二鳍部12内以及第二下拉晶体管区栅极结构两侧的第三鳍部13内形成下拉掺杂外延层(图未示)。
在半导体结构的形成过程中，所述基底除了用于形成SRAM器件之外，所述基底还包括用于形成逻辑器件的逻辑区。为了提高所形成器件的载流子迁移率、减小后续所形成金属硅化物与掺杂外延层的接触电阻，所形成上拉掺杂外延层和下拉掺杂外延层的体积较大，所形成逻辑区的掺杂外延层体积也较大。
结合参考图2，示出了采用上述形成方法所形成的一种半导体结构的电镜图，然而随着集成电路特征尺寸持续减小，所述第一鳍部11和所述第二鳍部12之间的距离L(如图1所示)也相应减小，从而容易导致所述第一鳍部11内的上拉掺杂外延层21和所述第二鳍部12内的下拉掺杂外延层22出现桥接(bridge)的现象(如图2中区域A所示)，且为了避免对逻辑区器件的电学性能产生不良影响，目前难以通过减小掺杂外延层体积的方法来改善所述桥接现象。
为了解决所述技术问题，本发明在下拉晶体管区栅极结构另一侧的鳍部内形成第二下拉掺杂区，，且所述第二下拉掺杂区采用对所述鳍部进行离子掺杂的非外延层方式形成，也就是说，所述下拉晶体管区栅极结构另一侧的鳍部内未形成下拉外延层；由于所述下拉晶体管区与上拉晶体管区相邻，因此相比通过在下拉晶体管区栅极结构另一侧的鳍部内形成下拉外延层以形成第二下拉掺杂区的方案，本发明可以避免因所述下拉晶体管区鳍部和上拉晶体管区鳍部之间距离过近的原因，而出现所述第二下拉掺杂区与所述上拉掺杂外延层发生桥接的问题。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图3至图16是本发明半导体结构的形成方法一实施例中各步骤对应结构示意图。
结合参考图3和图4，图3为俯视图(仅示意出衬底和鳍部)，图4是图3沿BB1割线的剖面图，提供基底，所述基底包括衬底100以及位于所述衬底100上分立的鳍部(未标示)，所述衬底100包括相邻的上拉晶体管区I(如图4所示)和下拉晶体管区II(如图4所示)。
所述基底为后续形成半导体结构提供工艺平台。本实施例中，所述基底为后续形成SRAM(静态随机随机存储器)提供工艺平台，且所形成SRAM为鳍式场效应管结构，所述上拉晶体管区I为PMOS区域，所述下拉晶体管区II为NMOS区域。
为了提高SRAM单元区的器件电流，所述下拉晶体管区II包括相邻的第一下拉晶体管区31和第二下拉晶体管区32，且所述第一下拉晶体管区31与所述上拉晶体管区I相邻。
所述下拉晶体管区II用于形成下拉晶体管，所述第一下拉晶体管区31用于形成第一下拉晶体管，所述第二下拉晶体管区32用于形成第二下拉晶体管，且所述第一下拉晶体管和第二下拉晶体管构成并联的下拉晶体管。相应的，所述第一下拉晶体管区31和第二下拉晶体管区32均为NMOS区域。因此，本实施例中，所述第一下拉晶体管区31的衬底100上具有鳍部，所述第二下拉晶体管区32的衬底100上也具有鳍部。
本实施例中，位于所述上拉晶体管区I衬底100上的鳍部为第一鳍部110，位于所述第一下拉晶体管区31衬底100上的鳍部为第二鳍部120，位于所述第二下拉晶体管区32衬底100上的鳍部为第三鳍部130。
本实施例中，所述衬底100为硅衬底。在其他实施例中，所述衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟，所述衬底还能够为绝缘体上的硅衬底、绝缘体上的锗衬底、玻璃基底或III-V族化合物衬底(例如氮化镓基底或砷化镓衬底等)。
所述鳍部的材料与所述衬底100的材料相同。本实施例中，所述鳍部的材料为硅，即所述第一鳍部110、第二鳍部120和第三鳍部130的材料为硅。在其他实施例中，所述鳍部的材料还可以是锗、锗化硅、碳化硅、砷化镓或镓化铟。
具体地，形成所述衬底100和鳍部的工艺步骤包括：提供初始衬底；在所述初始衬底表面形成图形化的第一硬掩膜层(图未示)；以所述第一硬掩膜层为掩膜刻蚀所述初始衬底，形成衬底100以及凸出于所述衬底100表面的鳍部。
本实施例中，形成所述衬底100和鳍部后，保留位于所述鳍部顶部的第一硬掩膜层。所述第一硬掩膜层的材料为氮化硅，后续在进行平坦化处理工艺时，所述第一硬掩膜层顶部表面用于定义平坦化处理工艺的停止位置，并起到保护鳍部顶部的作用。
继续参考图4，需要说明的是，提供所述基底后，所述形成方法还包括：在所述鳍部(未标示)露出的衬底100上形成隔离结构101，所述隔离结构101覆盖所述鳍部的部分侧壁，且所述隔离结构101的顶部低于所述鳍部的顶部。
所述隔离结构101作为半导体结构的隔离结构，用于对相邻器件起到隔离作用。本实施例中，所述隔离结构101的材料为氧化硅。在其他实施例中，所述隔离结构的材料还可以为氮化硅或氮氧化硅。
具体地，形成所述隔离结构101的步骤包括：在所述鳍部露出的衬底100上填充隔离材料，所述隔离材料顶部高于所述第一硬掩膜层(图未示)顶部；研磨去除高于所述第一硬掩膜层顶部的隔离材料，形成隔离膜；回刻蚀部分厚度的所述隔离膜，暴露出所述鳍部110顶部以及部分侧壁，形成所述隔离结构101；去除所述第一硬掩膜层。
需要说明的是，后续步骤包括形成横跨所述鳍部的栅极结构，在所述下拉晶体管区II栅极结构一侧的鳍部内形成第二下拉掺杂区，且所述第二下拉掺杂区采用对所述鳍部进行离子掺杂的非外延层方式形成，也就是说，形成所述第二下拉掺杂区的步骤中，未形成有外延层，而是直接对所述鳍部进行离子掺杂工艺；因此为了使所形成的下拉晶体管的电学性能不受影响，本实施例中，形成所述隔离膜后，回刻蚀部分厚度的所述隔离膜之前，所述形成方法还包括：对所述第二下拉掺杂区所对应的基底进行下拉阈值调节掺杂(VTImplant)处理，所述下拉阈值调节掺杂处理的掺杂离子为N型离子，N型离子可以为P、As或Sb。
所述下拉阈值调节掺杂处理的参数可以根据工艺需求而定。本实施例中，所述下拉阈值调节掺杂处理的参数包括：注入的离子能量为1KeV至10KeV，注入的离子剂量为1E13atom/cm2至5E14atom/cm2。
结合参考图5和图6，图5是立体图(未示出第二硬掩膜层)，图6是图5沿E1E2割线的剖面图，形成横跨所述鳍部(未标示)的栅极结构102，且所述栅极结构102覆盖部分鳍部顶部表面和侧壁表面。
本实施例中，所述上拉晶体管区I和下拉晶体管区II的鳍部上均形成有所述栅极结构102。具体的，位于所述上拉晶体管区I的栅极结构102横跨所述第一鳍部110，且覆盖所述第一鳍部110的部分顶部表面和侧壁表面；位于所述第一下拉晶体管区31的栅极结构102横跨所述第二鳍部120，且覆盖所述第二鳍部120的部分顶部表面和侧壁表面；位于所述第二下拉晶体管区32的栅极结构102横跨所述第三鳍部130，且覆盖所述第三鳍部130的部分顶部表面和侧壁表面。
本实施例中，采用后形成高k栅介质层后形成栅电极层(high k last metal gatelast)的工艺，因此所述栅极结构102为伪栅结构(dummy gate)，所述栅极结构102为后续所形成半导体结构的实际栅极结构占据空间位置。
所述栅极结构102为单层结构或叠层结构。所述栅极结构102包括伪栅层；或者所述栅极结构102包括伪氧化层以及位于所述伪氧化层上的伪栅层。其中，所述伪栅层的材料为多晶硅、氧化硅、氮化硅、氮氧化硅、碳化硅、碳氮化硅、碳氮氧化硅或非晶碳，所述伪氧化层的材料为氧化硅或氮氧化硅。
具体地，形成所述栅极结构102的步骤包括：在所述隔离结构101上形成伪栅膜，所述伪栅膜横跨所述鳍部，且覆盖鳍部顶部表面和侧壁表面；在所述伪栅膜表面形成第二硬掩膜层200，所述第二硬掩膜层200定义出待形成的栅极结构102的图形；以所述第二硬掩膜层200为掩膜，图形化所述伪栅膜，在所述上拉晶体管区I和下拉晶体管区II的隔离结构101上形成栅极结构102。
在其他实施例中，所述栅极结构还能够为后续所形成鳍式场效应管的实际栅极结构，所述栅极结构包括栅介质层以及位于栅介质层表面的栅电极层，其中，所述栅介质层的材料为氧化硅或高k栅介质材料，所述栅电极层的材料为多晶硅或金属材料，所述金属材料包括Ti、Ta、TiN、TaN、TiAl、TiAlN、Cu、Al、W、Ag或Au中的一种或多种。
需要说明的是，本实施例中，形成所述栅极结构102后，保留位于所述栅极结构102顶部上的第二硬掩膜层200。所述第二硬掩膜层200的材料为氮化硅，所述第二硬掩膜层200在后续工艺过程中用于对所述栅极结构102顶部起到保护作用。在其他实施例中，所述第二硬掩膜层的材料还可以为氮氧化硅、碳化硅或氮化硼。
后续步骤还包括：在所述上拉晶体管区I栅极结构102两侧的第一鳍部110内形成上拉掺杂外延层；在所述第一下拉晶体管区31栅极结构102一侧(如图5中区域C1所示)的第二鳍部120内形成第一下拉掺杂区，且所述第一下拉掺杂区用于与相邻上拉掺杂外延层相连；在所述第一下拉晶体管区31栅极结构102另一侧(如图5中区域C2所示)的第二鳍部120内形成第二下拉掺杂区；在所述第二下拉晶体管区32栅极结构102两侧的第三鳍部130内形成第三下拉掺杂区。
需要说明的是，随着集成电路特征尺寸持续减小，沿垂直于鳍部延伸方向上，所述第一鳍部110和第二鳍部120之间的距离也相应减小，因此为了避免所述第二下拉掺杂区与相邻所述上拉掺杂外延层发生桥接(bridge)现象，后续形成所述第二下拉掺杂区的步骤中，采用对所述鳍部进行离子掺杂的非外延层方式形成，相比采用选择性外延的工艺，本实施例所述方式可以减小所述第二下拉掺杂区与相邻所述上拉掺杂外延层发生桥接的风险。
本实施例中，以先形成所述上拉掺杂外延层作为示例进行详细说明。相应的，形成横跨所述鳍部(未标示)的栅极结构(未标示)后，所述方法还包括：
结合参考图7和图8，图7为图6基础上的剖面结构示意图，图8是沿F1F2(如图5所示)割线的剖面结构示意图，在所述上拉晶体管区I的鳍部(未标示)侧壁和顶部上形成P区掩膜层310。
具体地，在所述第一鳍部110的侧壁和顶部上形成所述P区掩膜层310。
本实施例中，所述P区掩膜层310还位于所述第二鳍部120顶部和侧壁上、第三鳍部130顶部和侧壁上，所述P区掩膜层310还位于上拉晶体管区I的栅极结构102顶部和侧壁、下拉晶体管区II的栅极结构102顶部和侧壁上，且还位于所述隔离结构101上。形成所述P区掩膜层310的工艺可以为化学气相沉积工艺、物理气相沉积工艺或原子层沉积工艺。本实施例中，采用原子层沉积工艺形成所述P区掩膜层310。
所述P区掩膜层310的作用包括：所述P区掩膜层310对所述鳍部侧壁起到保护的作用，避免后续形成上拉掺杂外延层时，在所述第一鳍部110、第二鳍部120和第三鳍部130的侧壁上进行外延生长工艺；此外，位于所述下拉晶体管区II的P区掩膜层310后续还作为下拉晶体管区II的N区掩膜层的一部分。
所述P区掩膜层310的材料可以为氮化硅、氧化硅、氮化硼或氮氧化硅。所述P区掩膜层310的材料与所述鳍部的材料不同，所述P区掩膜层310的材料与所述隔离结构101的材料也不相同。本实施例中，所述P区掩膜层310的材料为氮化硅。
如无特别说明，后续工艺过程中提供的剖面结构示意图均为在图8基础上的示意图。
参考图9，刻蚀位于所述上拉晶体管区I栅极结构102(如图5所示)两侧鳍部(未标示)顶部上的P区掩膜层310，暴露出所述上拉晶体管区I栅极结构102两侧的鳍部顶部表面，且还刻蚀所述上拉晶体管区I部分厚度的鳍部，在所述上拉晶体管区I的鳍部内形成P区凹槽111。
具体地，刻蚀位于所述上拉晶体管区I栅极结构102两侧第一鳍部110顶部上的P区掩膜层310，且还刻蚀部分厚度的第一鳍部110，在所述第一鳍部110内形成所述P区凹槽111。
所述P区凹槽111为后续形成上拉掺杂外延层提供空间位置。
需要说明的是，在刻蚀位于所述上拉晶体管区I栅极结构102两侧第一鳍部110顶部上的P区掩膜层310之前，还在所述下拉晶体管区II上形成第一图形层210，所述第一图形层210覆盖所述下拉晶体管区II的P区掩膜层310。所述第一图形层210起到保护所述下拉晶体管区II上P区掩膜层310的作用，所述第一图形层210还可以覆盖所述上拉晶体管区I中不期望被刻蚀的区域。
本实施例中，所述第一图形层210的材料为光刻胶材料。在形成所述P区凹槽111之后，采用湿法去胶或灰化工艺去除所述第一图形层210。
具体地，采用干法刻蚀工艺去除位于所述上拉晶体管区I栅极结构102两侧第一鳍部110顶部上的P区掩膜层310；其中，在刻蚀位于所述上拉晶体管区I栅极结构102两侧第一鳍部110顶部上P区掩膜层310的工艺过程中，还刻蚀位于上拉晶体管区I栅极结构102顶部上以及部分隔离结构101上的P区掩膜层310；在所述上拉晶体管区I栅极结构102两侧的第一鳍部110顶部被暴露出来后，继续刻蚀所暴露出的部分厚度的所述第一鳍部110，以形成所述P区凹槽111。
需要说明的是，后续步骤还包括在所述P区凹槽111内形成上拉掺杂外延层；所述上拉掺杂外延层用于向上拉晶体管沟道区提供压应力，以提高上拉晶体管的载流子迁移率，且增大所述上拉掺杂外延层的体积有利于提高载流子迁移率；此外，增大所述上拉掺杂外延层的体积还有利于降低后续所形成金属硅化物与所述上拉掺杂外延层的接触电阻。
因此本实施例中，为了增加后续在所述P区凹槽111内所形成上拉掺杂外延层的体积，在刻蚀所述第一鳍部110的同时，还刻蚀位于所述第一鳍部110侧壁上的P区掩膜层310，使得形成P区凹槽111后，位于所述第一鳍部110侧壁上的P区掩膜层310与所述第一鳍部110顶部齐平。
还需要说明的是，形成所述P区凹槽111后，所述形成方法还包括：对所述P区凹槽111进行清洗工艺。所述清洗工艺既用于去除所述P区凹槽111表面的杂质，还用于去除位于所述第一鳍部110表面的氧化层(图未示)，为后续在所述P区凹槽111内形成上拉掺杂外延层提供良好的界面态。
所述清洗工艺采用的清洗溶液可以是氨水、双氧水和水的混合溶液(SC1溶液)以及稀释氢氟酸(DHF)的组合，也可以是臭氧水、SC1溶液和DHF的组合。
参考图10，在所述上拉晶体管区I栅极结构102两侧的鳍部(未标示)内形成上拉掺杂外延层131。
本实施例中，所述上拉晶体管区I为PMOS区域，因此所述上拉掺杂外延层131的掺杂离子为P型离子。
本实施例中，形成所述上拉掺杂外延层131的工艺为原位掺杂的选择性外延工艺。形成所述上拉掺杂外延层131的步骤包括：在所述上拉晶体管区I栅极结构102两侧的第一鳍部110内形成上拉外延层(图未示)，且在形成所述上拉外延层的工艺过程中原位自掺杂P型离子，以形成所述上拉掺杂外延层131。
具体地，在所述P区凹槽111(如图9所示)内形成上拉外延层，且在形成所述上拉外延层的工艺过程中原位自掺杂P型离子，以形成所述上拉掺杂外延层131。
所述上拉掺杂外延层131的材料为P型掺杂的Si或SiGe。本实施例中，所述上拉外延层的材料为Si，所述P型离子为Ge离子，因此所述上拉掺杂外延层131为掺杂有Ge离子的Si，即所述上拉掺杂外延层131的材料为SiGe。
所述上拉掺杂外延层131的Ge离子浓度可以根据工艺需求而定。本实施例中，所述上拉掺杂外延层131的Ge离子浓度为5.02E21atom/cm3至2.5E22atom/cm3。
在其他实施例中，还可以在所述P区凹槽内形成上拉外延层后，对所述上拉外延层进行P型离子掺杂形成上拉掺杂外延层。
所述上拉外延层为上拉晶体管区I的沟道区提供压应力作用，从而提高下拉晶体管的载流子迁移率。
需要说明的是，本实施例中，所述上拉掺杂外延层131的顶部高于所述P区凹槽111的顶部，且由于选择性外延工艺的特性，高于所述P区凹槽111的上拉掺杂外延层131侧壁表面具有向远离所述第一鳍部110方向突出的顶角。在其他实施例中，所述上拉掺杂外延层顶部还可以与所述P区凹槽顶部齐平。
还需要说明的是，所述上拉掺杂外延层131的体积较大，因此所述上拉掺杂外延层131用于提高下拉晶体管载流子迁移率的效果较好；且所述上拉掺杂外延层131的顶部表面面积相应也较大，从而使得后续在所述上拉掺杂外延层131上形成金属硅化物后，所述金属硅化物与所述上拉掺杂外延层131的接触电阻较小。
此外，为了避免后续工艺对所述上拉掺杂外延层131表面造成工艺损伤，形成所述上拉掺杂外延层131后，所述方法还包括：对所述上拉掺杂外延层131表面进行氧化处理，在所述上拉掺杂外延层131表面形成氧化保护层(图未示)，所述氧化处理可以为干氧氧化、湿氧氧化或水汽氧化。
结合参考图11，形成所述上拉掺杂外延层131后，所述形成方法还包括：在所述下拉晶体管区II鳍部(未标示)的顶部和侧壁上形成N区掩膜层330。
具体的，形成所述N区掩膜层330的步骤包括：在形成所述上拉掺杂外延层131之后，在所述下拉晶体管区II的P区掩膜层310上形成N区掩膜侧墙320，其中，位于所述下拉晶体管区II的P区掩膜层310和所述N区掩膜侧墙320作为所述N区掩膜层330。
本实施例中，所述N区掩膜层330还位于所述下拉晶体管区II的栅极结构102顶部和侧壁上，且还位于所述下拉晶体管区II的隔离结构101上。
为了降低工艺难度、节约光罩，本实施例中，所述N区掩膜侧墙320还位于所述上拉掺杂外延层131上以及所述上拉晶体管区I的栅极结构102顶部和侧壁上，且还位于所述上拉晶体管区I的隔离结构101上。
有关所述N区掩膜侧墙320的材料和形成工艺可参考前述P区掩膜层310的相关描述，在此不再赘述。
所述N区掩膜侧墙320的作用包括：由所述N区掩膜侧墙320与所述P区掩膜层310构成叠层结构的N区掩膜层330，后续在所述下拉晶体管区II栅极结构120两侧的鳍部内形成下拉掺杂区时，以所述N区掩膜层330作为掩膜，因此通过所述N区掩膜侧墙320，可以增加后续所形成下拉掺杂区与所述下拉晶体管区II沟道区的距离，有利于改善短沟道效应。
参考图12，刻蚀位于所述下拉晶体管区II栅极结构102一侧(如图5中区域C1所示)鳍部(未标示)顶部上的N区掩膜层330，暴露出所述下拉晶体管区II栅极结构102一侧的鳍部顶部表面，且还刻蚀所述下拉晶体管区II部分厚度的鳍部，在所述下拉晶体管区II栅极结构102一侧的鳍部内形成N区凹槽121。
由于为了避免后续所形成第二下拉掺杂区与相邻所述上拉掺杂外延层131发生桥接现象，后续采用离子掺杂的非外延层方式形成所述第二下拉掺杂区，因此本实施例中，形成所述N区凹槽121的步骤中，仅在所述第一下拉晶体管区31栅极结构102一侧的第二鳍部120内形成所述N区凹槽121。
本实施例中，所述形成方法还包括：刻蚀位于所述第二下拉晶体管区32栅极结构102两侧第三鳍部130顶部上的N区掩膜层330，暴露出所述第二下拉晶体管区32栅极结构102两侧的第三鳍部130顶部表面，且还刻蚀部分厚度的第三鳍部130，在所述第二下拉晶体管区32栅极结构102两侧的第三鳍部130内形成N区凹槽121。
本实施例中，为了简化工艺步骤，节省光罩成本，在同一步骤中，在所述第一下拉晶体管区31栅极结构102一侧的第二鳍部120内、以及所述第二下拉晶体管区32栅极结构102两侧的第三鳍部130内形成所述N区凹槽121。
所述第二鳍部120内的N区凹槽121为后续在所述第一下拉晶体管区31栅极结构102一侧的第二鳍部120内形成第一下拉掺杂区提供空间位置，所述第三鳍部130内的N区凹槽121为后续在所述第二下拉晶体管区32栅极结构102两侧的第三鳍部130内形成第三下拉掺杂区提供空间位置。
需要说明的是，在刻蚀所述N区掩膜层330之前，在所述上拉晶体管区I和第一下拉晶体管区31栅极结构102另一侧(如图5中区域C2所示)的第二鳍部120上形成第二图形层220，所述第二图形层220还覆盖所述上拉晶体管区I的栅极结构102、下拉晶体管区II的栅极结构102以及隔离结构101。
具体地，所述第二图形层220形成于所述上拉晶体管区I和第一下拉晶体管区31栅极结构102另一侧的N区掩膜侧墙320上，所述第二图形层220用于保护所述下拉晶体管区II中不期望被刻蚀的区域。
本实施例中，所述第二图形层220的材料为光刻胶材料。在形成所述N区凹槽121之后，采用湿法去胶或灰化工艺去除所述第二图形层220。
具体地，采用干法刻蚀工艺，去除位于所述第一下拉晶体管区31栅极结构102一侧第二鳍部120顶部上、以及所述第二下拉晶体管区32栅极结构102两侧第三鳍部130顶部上的N区掩膜层330；其中，在刻蚀所述N区掩膜层330的工艺过程中，还刻蚀位于所述第一下拉晶体管区31栅极结构102顶部上、第二下拉晶体管区32栅极结构102顶部上以及部分隔离结构101上的N区掩膜层330；在所述第一下拉晶体管区31栅极结构102一侧的第二鳍部120顶部、以及第二下拉晶体管区32栅极结构102两侧的第三鳍部130顶部被暴露出来后，继续刻蚀暴露出的所述第二鳍部120和第三鳍部130，以形成所述N区凹槽121。
需要说明的是，后续步骤还包括在所述第一下拉掺杂区和第三下拉掺杂区上形成金属硅化物，其中所述金属硅化物与所述第一下拉掺杂区、第三下拉掺杂区的接触电阻与所述第一下拉掺杂区、第三下拉掺杂区的顶部表面面积成反比，增大所述第一下拉掺杂区和第三下拉掺杂区的体积还有利于降低所述接触电阻。
因此本实施例中，为了增加后续在所述N区凹槽121内所形成第一下拉掺杂区和第三下拉掺杂区的体积，在刻蚀所述第二鳍部120和第三鳍部130的同时，还刻蚀位于所述第二鳍部120侧壁上的N区掩膜层330以及第三鳍部130侧壁上的N区掩膜层330，使得形成N区凹槽121后，位于所述第二鳍部120侧壁上的N区掩膜层330与所述第二鳍部120顶部齐平，位于所述第三鳍部130侧壁上的N区掩膜层330与所述第三鳍部130顶部齐平。
还需要说明的是，形成所述N区凹槽121后，所述形成方法还包括：对所述N区凹槽121进行清洗工艺。所述清洗工艺既用于去除所述N区凹槽121表面的杂质，还用于去除位于所述第二鳍部120和第三鳍部130表面的氧化层(图未示)，为后续在所述N区凹槽121内形成第一下拉掺杂区和第三下拉掺杂区提供良好的界面态。
所述清洗工艺采用的清洗溶液可以是氨水、双氧水和水的混合溶液(SC1溶液)以及稀释氢氟酸(DHF)的组合，也可以是臭氧水、SC1溶液和DHF的组合。
结合参考图13和图14，图13为立体图(未示出P区掩膜层和N区掩膜层)，图14是图13沿G1G2割线的剖面图，在所述下拉晶体管区II栅极结构一侧(如图5中区域C1所示)的鳍部内形成第一下拉掺杂区132(如图13所示)，所述第一下拉掺杂区132用于与相邻上拉掺杂外延层131相连。
具体地，在所述第一下拉晶体管区31的N区凹槽121(如图12所示)内形成所述第一下拉掺杂区132。本实施例中，所述下拉晶体管区II为NMOS区域，因此所述第一下拉掺杂区132的掺杂离子为N型离子。
需要说明的是，所述N区凹槽121还形成于所述第二下拉晶体管区32栅极结构102两侧的第三鳍部130内，因此形成所述第一下拉掺杂区132的步骤中，还在所述第二下拉晶体管区32的N区凹槽121内形成第三下拉掺杂区133，所述第三下拉掺杂区133的材料与所述第一下拉掺杂区132的材料相同。
形成所述第一下拉掺杂区132和第三下拉掺杂区133的工艺为原位掺杂的选择性外延工艺。具体地，形成所述第一下拉掺杂区132和第三下拉掺杂区133的步骤包括：在所述N区凹槽121内形成下拉外延层(图未示)，且在形成所述下拉外延层的工艺过程中原位自掺杂N型离子，以形成所述第一下拉掺杂区132和第三下拉掺杂区133。
所述第一下拉掺杂区132的材料为N型掺杂的Si或SiC。本实施例中，所述下拉外延层的材料为Si，所述N型离子为P离子，因此所述第一下拉掺杂区132为掺杂有P离子的Si，即所述第一下拉掺杂区132的材料为SiP，相应的，所述第三下拉掺杂区133的材料也为SiP。
所述第一下拉掺杂区132的P离子浓度根据实际工艺需求而定。本实施例中，所述第一下拉掺杂区132的P离子浓度为1E20atom/cm3至2E21atom/cm3。相应的，所述第三下拉掺杂区133的P离子浓度为1E20atom/cm3至2E21atom/cm3。
在其他实施例中，还可以在所述N区凹槽内形成下拉外延层后，对所述下拉外延层进行N型离子掺杂形成所述第一下拉掺杂区和第三下拉掺杂区。
需要说明的是，本实施例中，所述下拉外延层的顶部高于所述N区凹槽121的顶部，且由于选择性外延工艺的特性，高于所述第一下拉晶体管区31N区凹槽121的下拉外延层侧壁表面具有向远离所述第二鳍部120方向突出的顶角，高于所述第二下拉晶体管区32N区凹槽121的下拉外延层侧壁表面具有向远离所述第三鳍部130方向突出的顶角。在其他实施例中，所述下拉外延层顶部还可以与所述N区凹槽顶部齐平。
还需要说明的是，所述下拉外延层的体积较大，因此所述第一下拉掺杂区132和第三下拉掺杂区133的顶部表面面积相应也较大，从而使得后续在所述第一下拉掺杂区132、第三下拉掺杂区133上形成金属硅化物后，所述金属硅化物与所述第一下拉掺杂区132、第三下拉掺杂区133的接触电阻较小。
结合参考图15和图16，图15是基于图13的立体图(未示出P区掩膜层和N区掩膜层)，图16是图15沿I1I2割线的剖面图，在所述下拉晶体管区II栅极结构102另一侧(如图5中区域C2所示)的鳍部(未标示)内形成第二下拉掺杂区(如图15中区域H所示)，且所述第二下拉掺杂区采用对所述鳍部进行离子掺杂125的非外延层方式形成。
为了避免所述第二下拉掺杂区与相邻所述上拉掺杂外延层131发生桥接现象，本实施例中，所述第二下拉掺杂区采用对所述鳍部进行离子掺杂125的非外延层方式形成，也就是说，所述下拉晶体管区II栅极结构102另一侧的鳍部内未形成有外延层(EPI)，而是直接对所述鳍部进行离子掺杂125。
本实施例中，所述下拉晶体管区II为NMOS区域，因此所述第二下拉掺杂区的掺杂离子为N型离子。具体地，形成所述第二下拉掺杂区的步骤包括：对所述下拉晶体管区I栅极结构102另一侧(如图5中区域C2所示)的鳍部进行N型离子注入工艺。
需要说明的是，本实施例中，由于所述第一下拉晶体管区31与所述上拉晶体管区I相邻，因此形成所述第二下拉掺杂区的步骤中，对所述第一下拉晶体管区31栅极结构102另一侧的第二鳍部120进行N型离子注入工艺，在所述第一下拉晶体管区31栅极结构102另一侧的第二鳍部120内形成所述第二下拉掺杂区。
具体地，形成覆盖所述上拉晶体管区I和第一下拉掺杂区132的第三图形层230，所述第三图形层230暴露出所述第一下拉晶体管区31栅极结构102另一侧第二鳍部120顶部上的N区掩膜层330；以所述第三图形层为掩膜，对所述N区掩膜层330进行离子掺杂工艺125，在所述第一下拉晶体管区31栅极结构102另一侧的第二鳍部120内形成第二下拉掺杂区。
所述掺杂离子透过所述N区掩膜层330注入至所述第二鳍部120内，从而在所述第一下拉晶体管区31栅极结构102另一侧的第二鳍部120内形成所述第二下拉掺杂区。
由于本实施例中，仅所述第二下拉掺杂区采用离子掺杂的非外延层方式形成，因此所述第三图形层还覆盖所述第二下拉晶体管区32。
所述N型离子注入工艺所注入的离子为P离子或As离子。所述N型离子注入工艺的参数根据实际工艺需求而定。本实施例中，所述N型离子注入工艺的步骤包括：注入的离子为P离子，注入的离子能量为1KeV至4KeV，注入的离子剂量为1E15atom/cm2至2E15atom/cm2；或者，注入的离子为As离子，注入的离子能量为1KeV至4KeV，注入的离子剂量为1E15atom/cm2至4E15atom/cm2。
本实施例中，在下拉晶体管区栅极结构另一侧的鳍部内形成第二下拉掺杂区，且所述第二下拉掺杂区采用对所述鳍部进行离子掺杂的非外延层方式形成，也就是说，所述下拉晶体管区栅极结构另一侧的鳍部内未形成下拉外延层；由于所述下拉晶体管区与上拉晶体管区相邻，因此相比通过在下拉晶体管区栅极结构另一侧的鳍部内形成下拉外延层以形成第二下拉掺杂区的方案，本发明可以避免因所述下拉晶体管区鳍部和上拉晶体管区鳍部之间距离过近的原因，而出现所述第二下拉掺杂区与所述上拉掺杂外延层发生桥接的问题。
相应的，本发明还提供一种半导体结构。结合参考图17至图19，示出了本发明半导体结构一实施例的结构示意图，其中图17是俯视图(仅示意出衬底和鳍部)，图18是图17中区域K的立体图，图19是图18沿L1L2割线的剖面图，所述半导体结构包括：
基底，包括衬底400以及位于所述衬底400上分立的鳍部(未标示)，所述衬底400包括相邻的上拉晶体管区I和下拉晶体管区II；
横跨所述鳍部的栅极结构402(如图18所示)，且所述栅极结构402覆盖部分鳍部顶部表面和侧壁表面；
上拉掺杂外延层431，位于所述上拉晶体管区I栅极结构402两侧的鳍部内；
第一下拉掺杂区432，位于所述下拉晶体管区II栅极结构402一侧的鳍部内，所述第一下拉掺杂区432用于与相邻上拉掺杂外延层431相连；
第二下拉掺杂区(如图18中区域J所示)，位于所述下拉晶体管区II栅极结构402另一侧的鳍部内，且所述第二下拉掺杂区为非外延层掺杂区。
本实施例中，所述基底上的半导体结构为SRAM(静态随机随机存储器)，且所述SRAM器件为鳍式场效应管，所述上拉晶体管区I为PMOS区域，所述下拉晶体管区II为NMOS区域。
为了提高SRAM单元区的器件电流，所述下拉晶体管区II包括相邻的第一下拉晶体管区31和第二下拉晶体管区32，且所述第一下拉晶体管区31与所述上拉晶体管区I相邻。
位于所述第一下拉晶体管区31上的晶体管为第一下拉晶体管，位于所述第二下拉晶体管区32上的晶体管为第二下拉晶体管，所述第一下拉晶体管和第二下拉晶体管构成并联的下拉晶体管。相应的，所述第一下拉晶体管区31和第二下拉晶体管区32均为NMOS区域。因此，所述第一下拉晶体管区31的衬底400上具有鳍部，所述第二下拉晶体管区32的衬底400上也具有鳍部。
本实施例中，位于所述上拉晶体管区I衬底400上的鳍部为第一鳍部410，位于所述第一下拉晶体管区31衬底400上的鳍部为第二鳍部420，位于所述第二下拉晶体管区32衬底400上的鳍部为第三鳍部430。
本实施例中，所述衬底400为硅衬底。在其他实施例中，所述衬底的材料还可以为锗、锗化硅、碳化硅、砷化镓或镓化铟，所述衬底还能够为绝缘体上的硅衬底、绝缘体上的锗衬底、玻璃基底或III-V族化合物衬底(例如氮化镓基底或砷化镓衬底等)。
所述鳍部的材料与所述衬底400的材料相同。本实施例中，所述鳍部的材料为硅，即所述第一鳍部410、第二鳍部420和第三鳍部430的材料为硅。在其他实施例中，所述鳍部的材料还可以是锗、锗化硅、碳化硅、砷化镓或镓化铟。
需要说明的是，所述半导体结构还包括：位于相邻所述鳍部之间衬底400上的隔离结构401，所述隔离结构401覆盖所述鳍部的部分侧壁，且所述隔离结构401的顶部低于所述鳍部的顶部。
所述隔离结构401作为半导体结构的隔离结构，用于对相邻器件起到隔离作用。本实施例中，所述隔离结构401的材料为氧化硅。在其他实施例中，所述隔离结构的材料还可以为氮化硅或氮氧化硅。
本实施例中，所述上拉晶体管区I和下拉晶体管区II的鳍部上均具有所述栅极结构402。具体的，位于所述上拉晶体管区I的栅极结构402横跨所述第一鳍部410，且覆盖所述第一鳍部410的部分顶部表面和侧壁表面；位于所述第一下拉晶体管区31的栅极结构402横跨所述第二鳍部420，且覆盖所述第二鳍部420的部分顶部表面和侧壁表面；位于所述第二下拉晶体管区32的栅极结构402横跨所述第三鳍部430，且覆盖所述第三鳍部430的部分顶部表面和侧壁表面。
所述栅极结构402包括栅介质层以及位于栅介质层表面的栅电极层，其中，所述栅介质层的材料为氧化硅或高k栅介质材料，所述栅电极层的材料为多晶硅或金属材料，所述金属材料包括Ti、Ta、TiN、TaN、TiAl、TiAlN、Cu、Al、W、Ag或Au中的一种或多种。
本实施例中，所述上拉晶体管区I为PMOS区域，因此所述上拉掺杂外延层431内具有P型离子。
所述上拉掺杂外延层431的材料为P型掺杂的Si或SiGe。本实施例中，所述上拉掺杂外延层431内的P型离子为Ge离子，所述上拉掺杂外延层431的材料为SiGe。
所述上拉掺杂外延层431的Ge离子浓度根据实际工艺需求而定。本实施例中，所述上拉掺杂外延层431的Ge离子浓度为5.02E21atom/cm3至2.5E22atom/cm3。
需要说明的是，所述上拉掺杂外延层431的体积较大，因此所述上拉掺杂外延层431用于提高下拉晶体管的载流子迁移率的效果较好；且所述上拉掺杂外延层431的顶部表面面积相应也较大，从而使位于所述上拉掺杂外延层431上的金属硅化物与所述上拉掺杂外延层431的接触电阻较小。
本实施例中，所述下拉晶体管区II包括相邻的第一下拉晶体管区31和第二下拉晶体管区32，且所述第一下拉晶体管区31与所述上拉晶体管区I相邻，因此所述第一下拉掺杂区432位于所述第一下拉晶体管区31栅极结构402一侧的第二鳍部120内，所述第二下拉掺杂区(如图18中区域J所示)位于所述第一下拉晶体管区31栅极结构402另一侧的第二鳍部120内。
本实施例中，所述下拉晶体管区II为NMOS区域，因此所述第一下拉掺杂区432和第二下拉掺杂区内均具有N型离子。
需要说明的是，所述第一下拉掺杂区432用于与相邻所述上拉掺杂外延层431相连，因此本实施例中，仅所述第二下拉掺杂区为非外延层掺杂区，也就是说，仅所述第二下拉掺杂区所对应的第二鳍部420内不具有下拉外延层，从而可以避免因相邻鳍部之间距离过近或外延层体积过大的原因，而出现所述第二下拉掺杂区与相邻所述上拉掺杂外延层431发生桥接(bridge)的现象。
所述第二下拉掺杂区的掺杂离子为P离子或As离子。所述第二下拉掺杂区的离子浓度根据实际工艺需求而定。本实施例中，所述第二下拉掺杂区的掺杂离子为P离子，所述第二下拉掺杂区的P离子浓度为1E19atom/cm3至1E21atom/cm3；或者，所述第二下拉掺杂区的掺杂离子为As离子，所述第二下拉掺杂区的P离子浓度为1E21atom/cm3至1E22atom/cm3。
还需要说明的是，为了使位于所述第一下拉掺杂区432上的金属硅化物与所述第一下拉掺杂区432的接触电阻较小，本实施例中，所述第一下拉掺杂区432所对应的鳍部内具有下拉外延层(图未示)，所述第一下拉掺杂区432位于所述下拉外延层内，所述下拉外延层的材料为Si或SiC。
相应的，所述第一下拉掺杂区432的材料为N型掺杂的Si或SiC。本实施例中，所述第一下拉掺杂区432的材料为SiP。
所述第一下拉掺杂区432的离子浓度根据实际工艺需求而定。本实施例中，所述第一下拉掺杂区432的P离子浓度为1E20atom/cm3至2E21atom/cm3。
所述第一下拉掺杂区432的体积较大，因此所述第一下拉掺杂区432的顶部表面面积相应也较大，从而使位于所述第一下拉掺杂区432上的金属硅化物与所述第一下拉掺杂区432的接触电阻较小。
本实施例中，所述下拉晶体管区II还包括第二下拉晶体管区32，因此，所述半导体结构还包括：第三下拉掺杂区433，位于所述第二下拉晶体管区32栅极结构402两侧的第三鳍部130内，所述第三下拉掺杂区433的材料与所述第一下拉掺杂区432的材料相同。相应的，所述第三下拉掺杂区433的材料为SiP，所述第三下拉掺杂区433的P离子浓度为1E20atom/cm3至2E21atom/cm3。
本实施例中，所述半导体结构包括第二下拉掺杂区，所述第二下拉掺杂区位于所述下拉晶体管区栅极结构另一侧鳍部内，且所述第二下拉掺杂区为非外延层掺杂区，也就是说，所述下拉晶体管区栅极结构另一侧的鳍部内不具有下拉外延层；由于所述下拉晶体管区与上拉晶体管区相邻，因此相比所述下拉晶体管区栅极结构另一侧鳍部内具有下拉外延层的方案，本发明所述半导体结构可以避免因所述下拉晶体管区鳍部和上拉晶体管区鳍部之间距离过近的原因，而出现所述第二下拉掺杂区与所述上拉掺杂外延层发生桥接的问题。
继续参考图17至图19，相应的，本发明还提供一种SRAM(静态随机随机存储器)，所述SRAM包括前述实施例所述的半导体结构。
对所述半导体结构的具体描述请参考前述实施例中半导体结构的相应描述，在此不再赘述。
由于所述SRAM中，位于所述下拉晶体管区栅极结构另一侧鳍部内的第二下拉掺杂区为非外延层掺杂区，也就是说，所述下拉晶体管区栅极结构另一侧鳍部内不具有下拉外延层；由于所述下拉晶体管区与上拉晶体管区相邻，因此相比所述下拉晶体管区栅极结构另一侧鳍部内具有下拉外延层的方案，本发明所述半导体结构可以避免因所述下拉晶体管区鳍部和上拉晶体管区鳍部之间距离过近的原因，而出现所述第二下拉掺杂区与所述上拉掺杂外延层发生桥接的问题。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (12)

1.一种半导体结构的形成方法，其特征在于，包括：
提供基底，所述基底包括衬底以及位于所述衬底上分立的鳍部，所述衬底包括相邻的上拉晶体管区和下拉晶体管区；
形成横跨所述鳍部的栅极结构，且所述栅极结构覆盖部分鳍部顶部表面和侧壁表面；
在所述上拉晶体管区栅极结构两侧的鳍部内形成上拉掺杂外延层，形成所述上拉掺杂外延层的过程中包括：在所述下拉晶体管区的鳍部顶部和侧壁上形成P区掩膜层；
在所述下拉晶体管区栅极结构一侧的鳍部内形成第一下拉掺杂区，所述第一下拉掺杂区用于与相邻上拉掺杂外延层相连；
在所述下拉晶体管区栅极结构另一侧的鳍部内形成第二下拉掺杂区，且所述第二下拉掺杂区采用对所述鳍部进行离子掺杂的非外延层方式形成；
其中，形成所述第一下拉掺杂区和第二下拉掺杂区的步骤包括：
形成所述上拉掺杂外延层后，在所述下拉晶体管区的所述P区掩膜层上形成N区掩膜侧墙，其中，位于所述下拉晶体管区的P区掩膜层和N区掩膜侧墙作为N区掩膜层；
刻蚀位于所述下拉晶体管区栅极结构一侧鳍部顶部上的N区掩膜层，且还刻蚀部分厚度的下拉晶体管区鳍部，在所述下拉晶体管区栅极结构一侧的鳍部内形成N区凹槽，刻蚀后的下拉晶体管区鳍部与所述N区掩膜层顶部齐平；
在所述N区凹槽内形成下拉外延层，且在形成所述下拉外延层的工艺过程中原位自掺杂N型离子，形成第一下拉掺杂区；
形成覆盖所述上拉晶体管区和第一下拉掺杂区的图形层，所述图形层暴露出所述下拉晶体管区栅极结构另一侧鳍部顶部上的N区掩膜层；
以所述图形层为掩膜，对所述N区掩膜层进行离子掺杂工艺，在所述下拉晶体管区栅极结构另一侧的鳍部内形成第二下拉掺杂区。
2.如权利要求1所述的半导体结构的形成方法，其特征在于，所述上拉晶体管区为PMOS区域，所述下拉晶体管区为NMOS区域；
所述上拉掺杂外延层的掺杂离子为P型离子，所述第一下拉掺杂区和第二下拉掺杂区的掺杂离子为N型离子。
3.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述上拉掺杂外延层的工艺为原位掺杂的选择性外延工艺；
形成所述上拉掺杂外延层的步骤包括：在所述上拉晶体管区栅极结构两侧的鳍部内形成上拉外延层，且在形成所述上拉外延层的工艺过程中原位自掺杂P型离子。
4.如权利要求3所述的半导体结构的形成方法，其特征在于，所述上拉掺杂外延层为掺杂有Ge离子的Si，所述上拉掺杂外延层的Ge离子浓度为5.02E21atom/cm3至2.5E22atom/cm3。
5.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述第二下拉掺杂区的步骤包括：对所述下拉晶体管区栅极结构另一侧的鳍部进行N型离子注入工艺。
6.如权利要求5所述的半导体结构的形成方法，其特征在于，所述N型离子注入工艺的步骤包括：注入的离子为P离子，注入的离子能量为1KeV至4KeV，注入的离子剂量为1E15atom/cm2至2E15atom/cm2；
或者，
注入的离子为As离子，注入的离子能量为1KeV至4KeV，注入的离子剂量为1E15atom/cm2至4E15atom/cm2。
7.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述第一下拉掺杂区的工艺为原位掺杂的选择性外延工艺；
形成所述第一下拉掺杂区的步骤包括：在所述下拉晶体管区栅极结构一侧的鳍部内形成下拉外延层，且在形成所述下拉外延层的工艺过程中原位自掺杂N型离子。
8.如权利要求7所述的半导体结构的形成方法，其特征在于，所述第一下拉掺杂区为掺杂有P离子的Si，所述第一下拉掺杂区的P离子浓度为1E20atom/cm3至2E21atom/cm3。
9.如权利要求1所述的半导体结构的形成方法，其特征在于，形成所述上拉掺杂外延层的步骤包括：在所述上拉晶体管区的鳍部侧壁和顶部上形成P区掩膜层，所述P区掩膜层还位于所述下拉晶体管区的鳍部顶部和侧壁上；
刻蚀位于所述上拉晶体管区栅极结构两侧鳍部顶部上的P区掩膜层，且还刻蚀部分厚度的上拉晶体管区鳍部，在所述上拉晶体管区栅极结构两侧的鳍部内形成P区凹槽，刻蚀后的上拉晶体管区鳍部与所述P区掩膜层顶部齐平；
在所述P区凹槽内形成上拉掺杂外延层。
10.如权利要求1所述的半导体结构的形成方法，其特征在于，提供基底的步骤中，所述下拉晶体管区包括相邻的第一下拉晶体管区和第二下拉晶体管区，且所述第一下拉晶体管区与所述上拉晶体管区相邻；
形成所述栅极结构的步骤中，位于所述第一下拉晶体管区的栅极结构横跨所述第一下拉晶体管区的鳍部，位于所述第二下拉晶体管区的栅极结构横跨所述第二下拉晶体管区的鳍部；
在所述下拉晶体管区栅极结构一侧的鳍部内形成第一下拉掺杂区的步骤中，通过原位掺杂的选择性外延工艺，在所述第一下拉晶体管区栅极结构一侧的鳍部内形成第一下拉掺杂区；
采用对所述下拉晶体管区栅极结构另一侧的鳍部进行离子掺杂的非外延层方式形成第二下拉掺杂区的步骤中，在所述第一下拉晶体管区栅极结构另一侧的鳍部内形成所述第二下拉掺杂区；
所述形成方法还包括：通过原位掺杂的选择性外延工艺，在所述第二下拉晶体管区栅极结构两侧的鳍部内形成第三下拉掺杂区，所述第三下拉掺杂区的材料与所述第一下拉掺杂区的材料相同。
11.如权利要求1所述的半导体结构的形成方法，其特征在于，提供所述基底后，形成所述栅极结构之前，所述形成方法还包括：对所述第二下拉掺杂区所对应的基底进行下拉阈值调节掺杂处理。
12.如权利要求11所述的半导体结构的形成方法，其特征在于，所述下拉阈值调节掺杂处理的参数包括：掺杂离子为N型离子，注入的离子能量为1KeV至10KeV，注入的离子剂量为1E13atom/cm2至5E14atom/cm2。
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