TW201913914A - 積體扇出型封裝 - Google Patents

積體扇出型封裝 Download PDF

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Publication number
TW201913914A
TW201913914A TW107118421A TW107118421A TW201913914A TW 201913914 A TW201913914 A TW 201913914A TW 107118421 A TW107118421 A TW 107118421A TW 107118421 A TW107118421 A TW 107118421A TW 201913914 A TW201913914 A TW 201913914A
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Taiwan
Prior art keywords
conductive
layer
redistribution
redistribution structure
die
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TW107118421A
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English (en)
Inventor
鄭心圃
劉獻文
洪士庭
林儀柔
方子睿
莊博堯
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台灣積體電路製造股份有限公司
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Publication of TW201913914A publication Critical patent/TW201913914A/zh

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Abstract

一種積體扇出型封裝包括第一重佈線結構、晶粒、包封體、多個導電結構及第二重佈線結構。所述第一重佈線結構具有第一表面及與所述第一表面相對的第二表面。所述晶粒設置在所述第一重佈線結構的所述第一表面上且與所述第一重佈線結構電性連接。所述包封體包封所述晶粒。所述導電結構設置在所述第一重佈線結構的所述第一表面上且穿透所述包封體。所述導電結構環繞所述晶粒。所述第二重佈線結構設置在所述包封體上且通過所述導電結構與所述第一重佈線結構電性連接。所述第二重佈線結構包括實體接觸所述包封體的至少一個導電圖案層。

Description

積體扇出型封裝
本發明實施例是有關於一種積體扇出型封裝，且特別是有關於一種具有重佈線結構的導電圖案層與包封體實體接觸的積體扇出型封裝。
由於各種電子元件（即，電晶體、二極體、電阻器、電容器等）的積體密度的持續提高，半導體行業已經歷快速增長。在很大程度上，積體密度的提高來自於最小特徵大小（minimum feature size）的重複減小，此使得更多較小的元件能夠整合到給定區域中。這些較小的電子元件也需要使用與先前的封裝相比佔用較小面積的較小的封裝。
當前，積體扇出型封裝因其緊湊性（compactness）而正變得日益流行。在積體扇出型封裝中，形成重佈線結構的步驟在封裝製程期間扮演著重要的角色。
一種積體扇出型封裝包括第一重佈線結構、晶粒、包封體、多個導電結構及第二重佈線結構。所述第一重佈線結構具有第一表面及與所述第一表面相對的第二表面。所述晶粒設置在所述第一重佈線結構的所述第一表面上且與所述第一重佈線結構電性連接。所述包封體包封所述晶粒。所述導電結構設置在所述第一重佈線結構的所述第一表面上且穿透所述包封體。所述導電結構環繞所述晶粒。所述第二重佈線結構設置在所述包封體上且通過所述導電結構與所述第一重佈線結構電性連接。所述第二重佈線結構包括實體接觸（physical contact）所述包封體的至少一個導電圖案層。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及排列的具體實例以簡化本公開。當然，這些僅為實例而不旨在進行限制。例如，以下說明中將第一特徵形成在第二特徵“之上”或第二特徵“上”可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且也可包括其中第一特徵與第二特徵之間可形成有附加特徵、以使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本公開可在各種實例中重複使用參考標號及/或字母。這種重複使用是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如“在...之下（beneath）”、“在...下面（below）”、“下部的（lower）”、“上方（above）”、“上部的（upper）”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外還囊括裝置在使用或操作中的不同取向。裝置可具有其他取向（旋轉90度或其他取向），且本文中所用的空間相對性用語可同樣相應地進行解釋。
本公開也可包括其他特徵及製程。舉例來說，可包括測試結構，以説明對三維（three-dimensional；3D）封裝或三維積體電路（three-dimensional integrated circuit；3DIC）裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基板上形成的測試墊（test pad），以便能夠對三維封裝或三維積體電路進行測試、對探針及/或探針卡（probe card）進行使用等。可對中間結構以及最終結構執行驗證測試。另外，可將本文中所公開的結構及方法與包括對已知良好晶粒（known good die）進行中間驗證的測試方法結合使用，以提高良率並降低成本。
圖1A至圖1J是根據本公開一些實施例的製造疊層封裝（package-on-package，PoP）結構10的製造流程的示意性剖面圖。參照圖1A，提供上面形成有剝離層102的載板100。在一些實施例中，載板100是玻璃基板。然而，其他材料也可作為載板100的材料，只要所述材料能夠在承載形成在其上的封裝結構的同時承受後續製程即可。在一些實施例中，剝離層102是形成在玻璃基板上的光熱轉換（light-to-heat conversion；LTHC）釋放層。剝離層102可使在後續製程中形成在載板100上的結構能夠被從載板100剝除。
在載板100及剝離層102上形成第一重佈線結構200。第一重佈線結構200具有第一表面200a及與第一表面200a相對的第二表面200b。在一些實施例中，第二表面200b面對載板100。在一些實施例中，第二表面200b貼附到剝離層102。第一重佈線結構200也包括晶粒貼合區DR及環繞晶粒貼合區DR的周邊區PR。在一些實施例中，第一重佈線結構200包括交替堆疊的多個重佈線導電層202與多個介電層204。重佈線導電層202通過嵌置在介電層204中的導電通孔206而彼此互連。在一些實施例中，介電層204的最底部的層（最底部介電層DI）接觸剝離層102。在一些實施例中，重佈線導電層202的最頂部的層被介電層204的最頂部的層暴露出。換句話說，重佈線導電層202被暴露出的最頂部的層可包括多個接墊以用於與隨後形成的其他元件進行電性連接。在一些實施例中，上述接墊包括重佈線接墊（佈線接墊）及/或凸塊接墊（bump pad）。在一些實施例中，重佈線導電層202及導電通孔206的材料包括鋁、鈦、銅、鎳、鎢及/或其合金。重佈線導電層202可通過例如電鍍、沉積及/或微影及蝕刻形成。在一些實施例中，介電層204的材料包括聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、苯並環丁烯（benzocyclobutene；BCB）、聚苯并噁唑（polybenzooxazole；PBO）或任何其他合適的聚合物系介電材料。除了以上列出的材料之外，最底部介電層DI也可包含週期性介孔有機矽（periodic mesoporous organosilica；PMO）、低溫聚醯亞胺（low temperature polyimide；LTPI）等。介電層204可通過例如旋轉塗布（spin-on coating）、化學氣相沉積（chemical vapor deposition；CVD）、電漿增強型化學氣相沉積（plasma-enhanced chemical vapor deposition；PECVD）等合適的製作技術來形成。
應注意的是，儘管在圖1A中繪示了四層重佈線導電層202及五層介電層204，然而這些層的數目在本公開中並非僅限於此。在一些替代實施例中，第一重佈線結構200可根據電路設計而由更多或更少層的重佈線導電層202及介電層204構成。類似地，重佈線導電層202中最頂部的層中的接墊的數目也不受本文所公開的實施例限制。
參照圖1B，在第一重佈線結構200的第一表面200a上形成多個導電結構400。導電結構400位於第一重佈線結構200的周邊區PR內。在一些實施例中，導電結構400是通過微影、鍍覆、光阻剝離製程或任何其他合適的方法形成的導電柱。在一些實施例中，導電結構400可通過以下步驟來形成。首先，形成罩幕圖案（未繪示）以覆蓋第一重佈線結構200的第一表面200a。罩幕圖案具有暴露出位於周邊區PR中的最頂部的重佈線導電層202的開口。之後，通過電鍍或沉積將金屬材料填充到所述開口中。接著，移除罩幕圖案以獲得導電結構400。然而，本公開並非僅限於此。也可利用其他合適的方法來形成導電結構400。在一些實施例中，導電結構400的材料可包含金屬材料，例如銅、銅合金等。在一些實施例中，導電結構400形成在最頂部的重佈線導電層202上且接觸最頂部的重佈線導電層202以實現與第一重佈線結構200的電性連接。應注意的是，出於例示目的在圖1C中僅呈現出兩個導電結構400。然而，在一些替代實施例中可形成多於兩個導電結構400。可根據需求來選擇導電結構400的數目。
參照圖1C，在第一重佈線結構200的第一表面200a上設置晶粒300。晶粒300被放置在第一重佈線結構200的晶粒貼合區DR內。由於周邊區PR環繞晶粒貼合區DR，因此導電結構400可被排列成環繞晶粒300。在一些實施例中，通過覆晶（flip chip）結合將晶粒300耦合至第一重佈線結構200的第一表面200a。舉例來說，晶粒300具有面對第一重佈線結構200的第一表面200a的主動表面300a及與主動表面300a相對的後表面300b。在一些實施例中，可通過位於晶粒300的主動表面300a與重佈線導電層202的最頂部的層（最頂部的重佈線導電層202）之間的多個導電凸塊302將晶粒300與第一重佈線結構200電性連接。在一些實施例中，導電凸塊302是焊料凸塊、銀球、銅球或任何其他合適的金屬球。在一些實施例中，可在導電凸塊302上塗抹助焊劑（soldering flux；未繪示）以實現更好的黏合。在一些實施例中，可利用底部填充層304填充晶粒300、第一重佈線結構200及導電凸塊302之間的間隙以增強可靠性。在一些替代實施例中，可省略底部填充層304。在一些替代實施例中，不在晶粒300與第一重佈線結構200之間提供底部填充。儘管圖1B及圖1C繪示在形成晶粒300之前形成導電結構400，然而本公開並非僅限於此。在一些替代實施例中，可在形成晶粒300之後提供導電結構400。參照圖1A及圖1C，由於第一重佈線結構200是在放置晶粒300之前形成，因此在一些實施例中，可將上述製程視為「先重佈線層方法（RDL first method）」。此外，由於晶粒300是通過覆晶接合而耦合到第一重佈線結構200的第一表面200a，因此可省略在傳統的封裝結構中用於對晶粒進行黏合的晶粒貼合膜（die attach film；DAF）或導線上膜（film on wire；FOW）。因此，隨後形成的封裝結構的總厚度可明顯減小。
參照圖1D，在第一重佈線結構200上形成包封體500。包封體500覆蓋且包封晶粒300及導電結構400。在一些實施例中，包封體500是通過包覆模塑（over-molding）製程形成的模塑化合物。在一些替代實施例中，包封體500的材料包括環氧樹脂或其他合適的樹脂。在這一階段期間，晶粒300及導電結構400不會露出且會受到包封體500的良好保護。
參照圖1E，將包封體500平坦化直到暴露出導電結構400的頂表面400a為止。在一些實施例中，在暴露出導電結構400的頂表面400a之後，進一步對包封體500及導電結構400進行研磨以減小封裝結構的總厚度。然而，包封體500及導電結構400是採用使得晶粒300的後表面300b仍受到包封體500的良好保護而不會被包封體500露出的方式來進行研磨。參照圖1E，在平坦化製程之後，包封體500的頂表面500a與導電結構400的頂表面400a實質上共面。由於導電結構400穿透過包封體500，因此在一些實施例中，導電結構400可被稱為層間穿孔（through interlayer via；TIV）或積體扇出型（integrated fan-out；InFO）穿孔。包封體500可通過例如研磨製程或化學機械拋光（chemical mechanical polishing；CMP）製程進行平坦化。在平坦化或研磨製程之後，可以可選地執行清潔步驟以移除所產生的殘渣。然而，本公開並非僅限於此，且可通過任何其他合適的方法來執行平坦化製程。
參照圖1F，在將包封體500平坦化以暴露出導電結構400之後，在包封體500及導電結構400上形成第二重佈線結構600。在一些實施例中，導電結構400與第二重佈線結構600相連。第二重佈線結構600通過導電結構400與第一重佈線結構200進行電性連接。在一些實施例中，第二重佈線結構600包括至少一個導電圖案層602，且導電圖案層602實體接觸（physical contact）包封體500。換句話說，導電結構400直接接觸導電圖案層602且在所述導電圖案層602與包封體500之間未夾置有介電層。舉例來說，參照圖1F，在一些實施例中，第二重佈線結構600是由單層導電圖案層602形成的結構，且所述單層導電圖案層602直接接觸包封體500。導電圖案層602還可包括佈線圖案（routing pattern）6024以及用於與其他電子元件電性連接的多個球接墊（ball pad）6022。在一些實施例中，球接墊6022對應於位於球接墊6022下面的導電結構400設置。舉例來說，每一個球接墊6022可對應於一個導電結構400。在一些實施例中，導電圖案層602從周邊區PR延伸到晶粒貼合區DR中。在一些實施例中，球接墊6022位於周邊區PR中，而佈線圖案6024位於晶粒貼合區DR中。在一些替代實施例中，球接墊6022同時位於周邊區PR與晶粒貼合區DR二者中，以使得位於晶粒300上方的空間可有效地被用於電性連接。在一些實施例中，第二重佈線結構600（導電圖案層602）被形成為具有1 μm到30 μm的厚度t1。應注意的是，圖1F中所呈現的單層式第二重佈線結構600僅為第二重佈線結構600的例示性實例，且本公開並非僅限於此。在一些替代實施例中，第二重佈線結構600可為多層式結構。隨後將與圖2一同更詳細地論述所述多層式重佈線結構。
再次參照圖1F，導電圖案層602的材料包括例如鋁、鈦、銅、鎳、鎢及/或其合金。在一些實施例中，第二重佈線結構600的導電圖案層602可通過以下步驟來形成。首先，在包封體500及導電結構400上濺鍍晶種層（未繪示）。晶種層可包括鈦層、銅層、鈦/銅複合層或任何其他合適的導電材料層。接著，可在晶種層上設置具有開口的圖案化光阻層（未繪示）以形成第二重佈線結構600的導電圖案層602的輪廓。之後，可執行鍍覆製程以將導電圖案層602沉積到被圖案化光阻層的開口暴露出的晶種層上。最後，將圖案化光阻層以及被圖案化光阻層遮蔽的晶種層一同移除以形成圖1F所示的第二重佈線結構600。
在一些實施例中，由於製程步驟的順序，在形成第一重佈線結構200之後，在包封體500上直接形成第二重佈線結構600的導電圖案層602而不在包封體500上形成一個或多個介電層。在某些實施例中，由於第二重佈線結構600的導電圖案層602直接實體接觸導電結構400且在導電圖案層602與導電結構400之間不存在有介電層，因此可省略用於移除介電層並暴露出導電結構的雷射鑽孔步驟。因此，可降低總生產成本。另外，由於在包封體500與導電圖案層602之間未形成介電層且在晶粒300與導電圖案層602之間未形成晶粒貼合膜層/導線上膜層，因此可消除在傳統的介電層及傳統的黏合層中所見的空隙問題（void issue），從而進一步改善封裝結構的平整性（planarity）。因此，可充分消除重佈線結構中導電跡線/佈線圖案的破裂，從而增強封裝結構的可靠性。此外，在一些實施例中，由於第二重佈線結構600的導電圖案層602直接形成在包封體500上而在導電圖案層602與包封體500之間不存在有介電層，因此第二重佈線結構600的厚度t1可有效地減小到1 μm到30 μm。此外，如上所述，由於晶粒300是通過覆晶接合而耦合到第一重佈線結構200，因此可省略在傳統的封裝結構中用於對晶粒進行黏合的晶粒貼合膜或導線上膜。由於省略了各個層（例如，第二重佈線結構600中的某些介電層以及晶粒貼合膜/導線上膜），因此可有效地減小後續形成的封裝結構的總厚度以滿足輕薄及緊湊（compact）要求。
參照圖1G，將第一重佈線結構200從載板100分離以使第一重佈線結構200的第二表面200b被暴露出。舉例來說，可暴露出最底部介電層DI。在一些實施例中，剝離層102是光熱轉換釋放層。在利用紫外（ultraviolet；UV）雷射進行照射時，可剝除並移除剝離層102及載板100。應注意的是，剝離製程並非僅限於此。在一些替代實施例中可使用其他合適的方法。在一些實施例中，圖1G所示結構具有為100 μm到550 μm的厚度t2。
參照圖1H，在移除剝離層102及載板100之後，將最底部介電層DI圖案化以形成多個接觸開口OP來局部地暴露出重佈線導電層202的最底部的層（最底部的重佈線導電層202）以用作電性連接。在一些實施例中，通過雷射鑽孔製程、機械鑽孔製程、微影製程或其他合適的製程形成最底部介電層DI的接觸開口OP。在一些實施例中，在最底部的重佈線導電層202上及第一重佈線結構200的第二表面200b上形成多個導電端子700，以形成第一封裝結構10a。在一些實施例中，第一封裝結構10a被形成為具有介於150 μm與600 μm之間的厚度t3。如上所述，第二重佈線結構600具有為1 μm到30 μm的厚度t1。因此，在一些實施例中，第二重佈線結構600的厚度t1對第一封裝結構10a的厚度t3的比率介於1:5與1:600之間。換句話說，第二重佈線結構600就厚度而言是第一封裝結構10a的0.17%到20%。在某些實施例中，最底部的重佈線導電層202從最底部介電層DI暴露出，且被暴露出的最底部的重佈線導電層202包括用於安裝球的球下金屬（under-ball metallurgy；UBM）圖案。導電端子700形成在相應的球下金屬圖案上。在一些實施例中，導電端子700的一部分通過第一重佈線結構200以及位於晶粒300下面的導電凸塊302與晶粒300電性連接。另一方面，導電端子700的另一部分通過第一重佈線結構200及導電結構400與第二重佈線結構600電性連接。在一些實施例中，導電端子700通過助焊劑（未繪示）貼合到球下金屬圖案。在一些實施例中，導電端子700是例如焊料球或球柵陣列（ball grid array；BGA）球。在一些實施例中，導電端子700可通過植球製程或回焊製程設置在球下金屬圖案上。
參照圖1I，在第一封裝結構10a上堆疊第二封裝結構10b。在一些實施例中，第二封裝結構10b包括封裝本體（package body）800a以及貼合到封裝本體800a的多個連接端子800b。在一些實施例中，第二封裝結構10b的封裝本體800a包括例如至少記憶體裝置。然而，本公開並非僅限於此。基於疊層封裝結構的功能需求，可採用其他封裝結構作為第二封裝結構10b。第二封裝結構10b的連接端子800b可類似於第一封裝結構10a的導電端子700。舉例來說，連接端子800b是焊料球或球柵陣列（BGA）球。在一些實施例中，連接端子800b可通過植球製程或回焊製程貼合到封裝本體800a。在一些實施例中，連接端子800b設置在位於周邊區PR中的球接墊6022上。在一些替代實施例中，連接端子800b設置在同時位於周邊區PR及晶粒貼合區DR二者中的球接墊6022上。在一些實施例中，第二封裝結構10b的封裝本體800a通過連接端子800b與第一封裝結構10a電性連接。換句話說，可利用位於晶粒300上方的空間進行球安裝，從而實現電路設計的靈活性。
參照圖1J，在第一封裝結構10a上堆疊第二封裝結構10b之後，形成底部填充層900來獲得疊層封裝結構10。在一些實施例中，底部填充層900填充到第一封裝結構10a、封裝本體800a及連接端子800b之間的間隙中。在一些替代實施例中，底部填充層900是可選地形成的且可被省略。在一些實施例中，底部填充層900可類似於第一封裝結構10a的底部填充層304以增強貼合製程的可靠性。在一些實施例中，疊層封裝結構10的厚度t4介於730 μm到1000 μm的範圍內。
如上所述，由於省略了各個層（例如，第二重佈線結構600中的某些介電層以及晶粒貼合膜/導線上膜），因此與傳統的封裝結構相比，可有效地減小第一封裝結構10a的總厚度。由於疊層封裝結構10是通過在第一封裝結構10a上堆疊第二封裝結構10b來形成，藉由第一封裝結構10a的輕薄特徵，疊層封裝結構10的總厚度t4也可得到充分減小。舉例來說，與傳統的封裝結構或傳統的疊層封裝結構相比，在厚度上可取得10%到35%的減小。
圖2是根據本公開一些替代實施例的疊層封裝結構20的示意性剖面圖。參照圖2，圖2的疊層封裝結構20類似於圖1J所繪示的疊層封裝結構10，而不同之處在於在圖2所示的疊層封裝結構20中，第一封裝結構10a’的第二重佈線結構600’是多層式結構。在一些實施例中，第二重佈線結構600’包括交替堆疊的多個導電圖案層602a、602b、602c及多個介電層604a、604b。介電層604a、604b分別夾置在兩相鄰的導電圖案層602a、602b、602c之間。舉例來說，介電層604a夾置在導電圖案層602a與導電圖案層602b之間。另一方面，介電層604b夾置在導電圖案層602b與導電圖案層602c之間。導電圖案層602a、602b、602c通過穿透過介電層604a、604b/嵌置在介電層604a、604b中的導電通孔606a、606b電性互連。在一些實施例中，第二重佈線結構600’被形成為具有1 μm到30 μm的厚度t1’。
在一些實施例中，最頂部的導電圖案層（導電圖案層602c）的至少一部分及最底部的導電圖案層（導電圖案層602a）的至少一部分分別被最頂部的介電層（介電層604b）及最底部的介電層（介電層604a）暴露出。最底部的導電圖案層（導電圖案層602a）實體接觸包封體500及導電結構400。另一方面，最頂部的導電圖案層（導電圖案層602c）可包括多個球接墊且可用於與隨後形成的其他元件進行電性連接。在一些實施例中，上述接墊被稱為用於安裝球的球下金屬（UBM）圖案。在一些實施例中，導電圖案層602a、602b、602c的材料及導電通孔606a、606b的材料包括鋁、鈦、銅、鎳、鎢及/或其合金。導電圖案層602a、602b、602c可通過例如電鍍、沉積及/或微影及蝕刻形成。在一些實施例中，介電層604a、604b的材料包括聚醯亞胺、環氧樹脂、丙烯酸樹脂、酚醛樹脂、苯並環丁烯（BCB）、聚苯并噁唑（PBO）或任何其他合適的聚合物系介電材料。介電層604a、604b可通過例如旋轉塗布、化學氣相沉積（CVD）、電漿增強型化學氣相沉積（PECVD）等合適的製作技術來形成。應注意的是，圖2所呈現的導電圖案層及介電層的數目僅用作示例性例示且不旨在限制本公開。在一些替代實施例中，基於電路設計要求，導電圖案層及介電層的數目與圖2所提供的例示相比可更多或更少。
在一些實施例中，由於製程步驟的順序，在形成第一重佈線結構200之後，在包封體500上直接形成第二重佈線結構600’的導電圖案層602a而不在導電圖案層602a與包封體500之間形成一個或多個介電層。在某些實施例中，由於第二重佈線結構600’的導電圖案層602a直接實體接觸導電結構400且在導電圖案層602a與導電結構400之間不存在有介電層，因此可省略用於移除介電層並暴露出導電結構的雷射鑽孔步驟。因此，可降低總生產成本。另外，由於在包封體500與導電圖案層602a之間未形成介電層且在晶粒300與導電圖案層602a之間未形成晶粒貼合膜層/導線上膜層，因此可消除在傳統的介電層及傳統的黏合層中所見的空隙問題，從而進一步改善封裝結構的平整性。因此，可充分消除重佈線結構中導電跡線/佈線圖案的破裂，從而增強封裝結構的可靠性。此外，在一些實施例中，由於第二重佈線結構600的導電圖案層602a直接形成在包封體500上而在導電圖案層602a與包封體500之間不存在有介電層，因此第二重佈線結構600’的厚度t1’可有效地減小到1 μm到30 μm。此外，如上所述，由於晶粒300是通過覆晶接合而耦合到第一重佈線結構200，因此可省略在傳統的封裝結構中用於對晶粒進行黏合的晶粒貼合膜或導線上膜。由於省略了各個層（例如，第二重佈線結構600’中的某些介電層以及晶粒貼合膜/導線上膜），因此可有效地減小疊層封裝結構20的總厚度以滿足輕薄及緊湊要求。
根據本公開的一些實施例，一種積體扇出型封裝包括第一重佈線結構、晶粒、包封體、多個導電結構及第二重佈線結構。所述第一重佈線結構具有第一表面及與所述第一表面相對的第二表面。所述晶粒設置在所述第一重佈線結構的所述第一表面上且與所述第一重佈線結構電性連接。所述包封體包封所述晶粒。所述導電結構設置在所述第一重佈線結構的所述第一表面上且穿透所述包封體。所述導電結構環繞所述晶粒。所述第二重佈線結構設置在所述包封體上且通過所述導電結構與所述第一重佈線結構電性連接。所述第二重佈線結構包括實體接觸（physical contact）所述包封體的至少一個導電圖案層。
根據本公開的一些實施例，所述積體扇出型封裝還包括設置在所述第一重佈線結構的所述第二表面上的多個導電端子。
根據本公開的一些實施例，所述晶粒通過多個導電凸塊與所述第一重佈線結構電性連接。
根據本公開的一些實施例，所述第二重佈線結構的厚度對所述積體扇出型封裝的厚度的比率介於1:5到1:600的範圍內。
根據本公開的一些實施例，所述第二重佈線結構包括多個導電圖案層及夾置在兩相鄰的導電圖案層之間的多個介電層，且所述多個導電圖案層中的最底部的導電圖案層實體接觸所述包封體。
根據本公開的一些實施例，所述多個導電結構包括層間穿孔（through interlayer via）且所述最底部的導電圖案層實體接觸所述多個導電結構。
根據本公開的一些實施例，所述多個導電圖案層中的最頂部的導電圖案層包括多個球接墊（ball pad）及多個佈線圖案（routing patterns）。
根據本公開的一些替代實施例，一種疊層封裝（package-on-package；PoP）結構包括第一封裝結構以及堆疊在所述第一封裝結構上的第二封裝結構。所述第一封裝結構包括第一重佈線結構、晶粒、多個導電結構、包封體及導電圖案層。所述第一重佈線結構具有晶粒貼合區及環繞所述晶粒貼合區的周邊區。所述晶粒設置在所述第一重佈線結構的所述晶粒貼合區上。所述導電結構設置在所述第一重佈線結構的所述周邊區上。所述包封體包封所述晶粒及所述導電結構。導電圖案層設置在所述包封體上且實體接觸所述包封體。所述導電圖案層通過所述導電結構與所述第一重佈線結構電性連接，且包括多個球接墊及多個佈線圖案。
根據本公開的一些替代實施例，所述疊層封裝結構還包括設置在所述第一重佈線結構上的多個導電端子。
根據本公開的一些替代實施例，所述第二封裝結構包括封裝本體（package body）及貼合到所述封裝本體的多個連接端子，且所述封裝本體通過所述多個連接端子與所述第一封裝結構電性連接。
根據本公開的一些替代實施例，所述疊層封裝結構還包括底部填充層，所述底部填充層填充所述第一封裝結構、所述封裝本體及所述多個連接端子之間的間隙。
根據本公開的一些替代實施例，所述連接端子設置在位於所述周邊區及所述晶粒貼合區二者中的所述多個球接墊上。
根據本公開的一些替代實施例，所述晶粒通過多個導電凸塊與所述第一重佈線結構電性連接。
根據本公開的一些替代實施例，所述導電圖案層的厚度對所述第一封裝結構的厚度的比率介於1:5到1:600的範圍內。
根據本公開的一些實施例，一種製造疊層封裝結構的方法包括至少以下步驟。首先提供載板。接著，形成第一封裝結構。之後，將第二封裝結構堆疊在所述第一封裝結構上。所述第一封裝結構是通過至少以下步驟形成。首先，在載板上形成第一重佈線結構。所述第一重佈線結構具有第一表面及與所述第一表面相對的第二表面，且所述第二表面面對所述載板。接著，在所述重佈線結構的所述第一表面上提供/形成晶粒及多個導電結構。所述導電結構環繞所述晶粒。使用包封體包封所述晶粒及所述導電結構。之後，在包封體上形成第二重佈線結構。所述第二重佈線結構通過所述導電結構與所述第一重佈線結構電性連接。所述第二重佈線結構包括實體接觸所述包封體的至少一個導電圖案層。然後，將所述載板從所述第一重佈線結構分離及移除。
根據本公開的一些實施例，製造疊層封裝結構的方法還包括在將所述載板從所述第一重佈線結構移除後，在所述第一重佈線結構的所述第二表面上形成多個導電端子。
根據本公開的一些實施例，形成所述第二重佈線結構包括形成多個導電圖案層及形成夾置在兩相鄰的導電圖案層之間的多個介電層，且所述多個導電圖案層中的最底部的導電圖案層實體接觸所述包封體。
根據本公開的一些實施例，所述多個導電圖案層中的最頂部的導電圖案層包括多個球接墊及多個佈線圖案。
根據本公開的一些實施例，所述第二封裝結構包括封裝本體及貼合到所述封裝本體的多個連接端子，且所述多個連接端子設置在所述多個球接墊上以使所述封裝本體通過所述多個連接端子與所述第一封裝結構電性連接。
根據本公開的一些實施例，製造疊層封裝結構的方法還包括形成底部填充層，以填充所述第一封裝結構、所述封裝本體及所述多個連接端子之間的間隙。
以上概述了若干實施例的特徵，以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應知，他們可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員還應認識到，這些等效構造並不背離本公開的精神及範圍，而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、代替及變更。
10、20‧‧‧疊層封裝結構
10a、10a’‧‧‧第一封裝結構
10b‧‧‧第二封裝結構
100‧‧‧載板
102‧‧‧剝離層
200‧‧‧第一重佈線結構
200a‧‧‧第一表面
200b‧‧‧第二表面
202‧‧‧重佈線導電層
204、604a、604b‧‧‧介電層
206、606a、606b‧‧‧導電通孔
300‧‧‧晶粒
300a‧‧‧主動表面
300b‧‧‧後表面
302‧‧‧導電凸塊
304、900‧‧‧底部填充層
400‧‧‧導電結構
400a、500a‧‧‧頂表面
500‧‧‧包封體
600、600’‧‧‧第二重佈線結構
602、602a、602b、602c‧‧‧導電圖案層
700‧‧‧導電端子
800a‧‧‧封裝本體
800b‧‧‧連接端子
6022‧‧‧球接墊
6024‧‧‧佈線圖案
DI‧‧‧最底部介電層
DR‧‧‧晶粒貼合區
OP‧‧‧接觸開口
PR‧‧‧周邊區
t1、t1’、t2、t3、t4‧‧‧厚度
圖1A至圖1J是根據本公開一些實施例的製造疊層封裝（package-on-package，PoP）結構的製造流程的示意性剖面圖。 圖2是根據本公開一些替代實施例的疊層封裝結構的示意性剖面圖。

Claims (1)

  1. 一種積體扇出型封裝，包括： 第一重佈線結構，具有第一表面及與所述第一表面相對的第二表面； 晶粒，設置在所述第一重佈線結構的所述第一表面上，其中所述晶粒與所述第一重佈線結構電性連接； 包封體，包封所述晶粒； 多個導電結構，設置在所述第一重佈線結構的所述第一表面上且穿透所述包封體，其中所述多個導電結構環繞所述晶粒；以及 第二重佈線結構，設置在所述包封體上，其中所述第二重佈線結構通過所述多個導電結構與所述第一重佈線結構電性連接，所述第二重佈線結構包括實體接觸所述包封體的至少一個導電圖案層。
TW107118421A 2017-08-29 2018-05-30 積體扇出型封裝 TW201913914A (zh)

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US11107769B2 (en) 2019-08-02 2021-08-31 Samsung Electronics Co., Ltd. Semiconductor package and a method of fabricating the same
CN112582366A (zh) * 2020-12-11 2021-03-30 矽磐微电子(重庆)有限公司 半导体封装结构及其制备方法
US20230140738A1 (en) * 2021-10-30 2023-05-04 Raymond Won Bae Microelectronic test and package interface substrates, devices, and methods of manufacture thereof alignment improvement of interconnect on buildup redistribution layers

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