TW201919190A - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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Publication number
TW201919190A
TW201919190A TW107100269A TW107100269A TW201919190A TW 201919190 A TW201919190 A TW 201919190A TW 107100269 A TW107100269 A TW 107100269A TW 107100269 A TW107100269 A TW 107100269A TW 201919190 A TW201919190 A TW 201919190A
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Taiwan
Prior art keywords
layer
die
protective layer
hole
encapsulation body
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TW107100269A
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English (en)
Inventor
許峯誠
陳碩懋
鄭心圃
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台灣積體電路製造股份有限公司
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Publication of TW201919190A publication Critical patent/TW201919190A/zh

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract

提供一種封裝結構及其製造方法。所述封裝結構包括晶粒、包封體、重佈線層結構及保護層。晶粒包括彼此相對的第一表面與第二表面。包封體位於晶粒側邊。重佈線層結構藉由多個導電凸塊與晶粒電性連接。重佈線層結構位於晶粒的述第二表面及包封體下方。保護層位於晶粒的第一表面及包封體之上。保護層用於控制封裝結構的翹曲。

Description

封裝結構及其製造方法
本揭露涉及一種封裝結構及其製造方法。
隨著各種電子元件（例如，電晶體、二極體、電阻器、電容器等）的積集度的持續提高，半導體行業已經歷快速發展。在很大程度上，積集度的此種提高來自於最小特徵尺寸（minimum feature size）的持續減小，此使得更多較小的元件能夠整合到給定區域中。這些較小的電子元件也需要與先前的封裝相比利用較小區域的較小封裝。用於半導體元件的一些較小類型的封裝包括四面扁平封裝（quad flat package，QFP）、引腳陣列（pin grid array，PGA）封裝、球陣列（ball grid array，BGA）封裝、倒裝晶片（flip chip，FC）、三維積體電路（three-dimensional integrated circuit，3DIC）、晶片級封裝（wafer level package，WLP）及疊層封裝（package on package，PoP）裝置等。
當前，積體扇出型封裝因其緊密度而正變得日漸流行。
根據本揭露的一些實施例，提供一種封裝結構，所述封裝結構包括晶粒、包封體、重佈線層結構及保護層。晶粒包括彼此相對的第一表面與第二表面。包封體位於晶粒側邊。重佈線層結構藉由多個導電凸塊與晶粒電性連接。重佈線層結構位於晶粒的第二表面及包封體下方。保護層位於晶粒的第一表面及包封體之上。保護層用於控制封裝結構的翹曲。
根據本揭露的一些實施例，提供一種封裝結構，所述封裝結構包括晶粒、積體扇出型通孔、包封體、重佈線層結構、保護層及頂蓋。積體扇出型通孔位於晶粒側邊。包封體包封積體扇出型通孔的側壁及晶粒的側壁。重佈線層結構藉由多個導電凸塊與晶粒電性連接。保護層位於包封體、積體扇出型通孔及晶粒之上。頂蓋位於積體扇出型通孔上，覆蓋積體扇出型通孔的部分頂表面。保護層用於控制封裝結構的翹曲。
根據本揭露的一些實施例，提供一種製造封裝結構的方法。將晶粒藉由多個導電凸塊連接至重佈線層結構。形成包封體以至少包封晶粒的側壁。在包封體及晶粒之上形成保護層，以控制封裝結構的翹曲。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下公開內容提供用於實現所提供主題的不同特徵的許多不同的實施例或實例。以下闡述元件及配置的具體實例以簡化本揭露。當然，這些僅為實例而非用以限制。舉例來說，以下說明中將第二特徵形成於第一特徵“之上”或第一特徵“上”可包括第二特徵及第一特徵被形成為直接接觸的實施例，且也可包括第二特徵與第一特徵之間可形成有附加特徵而使得所述第二特徵與所述第一特徵可能不直接接觸的實施例。另外，本公開內容可能在各種實例中重複使用元件符號及/或字母。這種重複是出於簡潔及清楚的目的，而不表示所論述的各種實施例及/或配置本身之間的關係。
此外，為易於說明，本文中可能使用例如“之下（beneath）”、“下面（below）”、“下部的（lower）”、“位於……上（on）”、“上方（above）”、“上部的（upper）”等空間相對性用語來闡述圖中所示的一個元件或特徵與另一（其他）元件或特徵的關係。除了附圖中所繪示的定向之外，所述空間相對性用語意欲涵蓋元件在使用或操作中的不同定向。設備可具有其他定向（旋轉90度或其他定向），且本文中所使用的空間相對性描述語可同樣相應地進行解釋。
以下揭露也可包括其他特徵及製程。舉例來說，可包括測試結構，以對三維封裝（3D packaging）或三維積體電路裝置進行驗證測試。所述測試結構可包括例如在重佈線層中或在基底上形成的測試接墊（test pad），所述測試接墊能夠測試三維封裝或三維積體電路、使用探針及/或探針卡（probe card）等。可對中間結構以及最終結構進行驗證測試。另外，本文中所公開的結構及方法可與包括對已知良好晶粒（known good die）進行中間驗證的測試方法結合使用，以提高良率（yield）並降低成本。
圖1A至圖1F是示出根據本揭露第一實施例的製造封裝結構的方法的示意性剖視圖。
參照圖1A，提供載板10。載板10可為玻璃載板、陶瓷載板或類似載板。以例如是旋轉塗布方法（spin coating method）在載板10上形成剝離層（de-bonding layer）11。在一些實施例中，剝離層11可由例如紫外（Ultra-Violet，UV）膠、光熱轉換（Light-to-Heat Conversion，LTHC）膠等黏合劑或者其他類型的黏合劑形成。剝離層11能夠在光熱作用下分解，以使載板10從將在後續步驟中形成的上覆結構脫離。
在載板10及剝離層11之上形成重佈線層（redistribution layer，RDL）結構12。在一些實施例中，重佈線層結構12包括交替堆疊的多個聚合物層PM1、PM2、PM3及PM4與多個重佈線層RDL1、RDL2、RDL3及RDL4。聚合物層或重佈線層的數目在本揭露中不受限制。在一些實施例中，重佈線層結構12包括至少三層重佈線層。在一些實施例中，重佈線層結構12不含有基底。
在一些實施例中，重佈線層RDL1穿透聚合物層PM1，且重佈線層RDL1的底表面與聚合物層PM1的底表面彼此實質上齊平，且與剝離層11接觸。重佈線層RDL2穿透聚合物層PM2，與重佈線層RDL1電性連接。重佈線層RDL3穿透聚合物層PM3，與重佈線層RDL2電性連接。重佈線層RDL4穿透聚合物層PM4，與重佈線層RDL3電性連接。
在一些實施例中，重佈線層RDL4也被稱作接墊（pad），且重佈線層RDL4位於用於在後續製程中與晶粒連接的區域中。在一些實施例中，重佈線層RDL4從聚合物層PM4的頂表面突出而暴露出來，也就是說，重佈線層RDL4的頂表面高於聚合物層PM4的頂表面，但本揭露並非僅限於此。在另一些實施例中，重佈線層RDL4的頂表面可與聚合物層PM4的頂表面實質上齊平。
在一些實施例中，重佈線層RDL1、RDL2、RDL3及RDL4分別包括彼此連接的多個通孔V與多條跡線（trace）T。通孔V穿透聚合物層PM1、PM2、PM3及PM4，以連接重佈線層RDL1、RDL2、RDL3及RDL4的跡線T。跡線T分別位於聚合物層PM1、PM2、PM3及PM4上，且分別在聚合物層PM1、PM2、PM3及PM4的頂表面上延伸。
參照圖1A中的通孔V及跡線T的放大圖，在一些實施例中，通孔V的橫截面形狀為倒梯形，但本揭露並非僅限於此。在一些實施例中，通孔V的底角θ為鈍角，且通孔V的頂表面的寬度W20大於通孔V的底表面的寬度W10。在一些實施例中，通孔V的頂表面的面積大於通孔V的底表面的面積。在另一些實施例中，通孔V的橫截面形狀可為正方形或矩形，且通孔V的底角θ為直角。
在一些實施例中，聚合物層PM1、PM2、PM3及PM4分別包含感光性材料。感光性材料例如是聚苯並惡唑（polybenzoxazole，PBO）、聚醯亞胺（polyimide，PI）、苯並環丁烯（benzocyclobutene，BCB）、其組合或其類似物。聚合物層PM1、PM2、PM3及PM4的形成方法例如是包括旋轉塗佈、化學氣相沉積（chemical vapor deposition，CVD）、等離子體增強型化學氣相沉積（plasma-enhanced chemical vapor deposition，PECVD）、疊層（lamination）或類似的適合的製作技術。在一些實施例中，重佈線層RDL1、RDL2、RDL3及RDL4分別包含導電材料。所述導電材料包括金屬，例如是銅、鎳、鈦、其組合或其類似物，且是藉由電鍍製程（electroplating process）形成。在一些實施例中，重佈線層RDL1、RDL2、RDL3及RDL4分別包括晶種層（圖中未示出）及形成於所述晶種層上的金屬層（圖中未示出）。晶種層可為金屬晶種層，例如銅晶種層。在一些實施例中，晶種層包括第一金屬層（例如鈦層）及位於所述第一金屬層之上的第二金屬層（例如銅層）。金屬層可為銅或其他適合的金屬。
參照圖1B，在重佈線層結構12之上放置晶粒17，晶粒17與重佈線層結構12電性連接。具體來說，晶粒17藉由多個導電凸塊18與重佈線層結構12的重佈線層RDL4連接。晶粒17可為特定應用積體電路（application-specific integrated circuit，ASIC）晶片、類比晶片（analog chip）、感測器晶片（sensor chip）、無線射頻晶片（wireless and radio frequency chip）、電壓調節器晶片（voltage regulator chip）或記憶體晶片（memory chip）。圖1B中所示晶粒17的數目僅用於示例說明，且本揭露並非僅限於此。在一些實施例中，可將兩個或更多個晶粒17安裝到重佈線層結構12上，且所述兩個或更多個晶粒17可為相同類型的晶粒或不同類型的晶粒。
在一些實施例中，晶粒17包括基底13、多個接墊14、鈍化層（passivation layer）15及多個連接件16。接墊14可為內連線結構（圖中未示出）的一部份，且電性連接到晶粒17的積體電路裝置（圖中未示出）。鈍化層15覆蓋接墊14的一部分。鈍化層15包含絕緣材料，例如氧化矽、氮化矽、聚合物或其組合。接墊14的一部分被鈍化層15暴露出來，且用做晶粒17的外部連接（external connection）。連接件16與未被鈍化層15覆蓋的接墊14接觸並電性連接。連接件16包括銲料凸塊、金凸塊、銅凸塊、銅杆（copper post）、銅柱（copper pillar）或其類似物。
晶粒17具有彼此相對的第一表面17a（即，頂表面）與第二表面17b（即，底表面）。在一些實施例中，第一表面17a為基底13的遠離連接件16的表面。第二表面17b為晶粒17的主動表面17b，其面對重佈線層結構12的頂表面。在一些實施例中，第二表面17b包括連接件16的部分表面及鈍化層15的部分表面。也就是說，重佈線層結構12位於晶粒17的前側（靠近連接件16的一側）。在一些實施例中，重佈線層結構12的通孔V的頂表面比通孔V的底表面相對更靠近晶粒17的第二表面17b，重佈線層結構12的通孔V的底表面比通孔V的頂表面相對更遠離晶粒17的第二表面17b。換句話說，在一些實施例中，通孔V的具有較大面積的頂表面比通孔V的底表面相對更靠近晶粒17的主動表面17b。
仍然參照圖1B，導電凸塊18位於晶粒17的連接件16與重佈線層結構12的重佈線層RDL4之間。在一些實施例中，導電凸塊18還覆蓋連接件16的部分側壁及重佈線層RDL4的部分側壁。在一些實施例中，導電凸塊18為銲料凸塊、銀球、銅球或任何其他適合的金屬球。在一些實施例中，可將助銲劑（soldering flux）（圖中未示出）塗覆到導電凸塊18上以得到更好的黏合。在一些實施例中，在將晶粒17連接到重佈線層結構12之後，形成底部填充膠層（underfill layer）19，填充於晶粒17與重佈線層結構12之間，進而覆蓋晶粒17的主動表面17b以及聚合物層PM4的部分頂表面，且底部填充膠層19環繞連接件16、導電凸塊18及重佈線層RDL4。在一些實施例中，底部填充膠層19還覆蓋晶粒17的部分側壁。在一些實施例中，底部填充膠層19包含聚合物，例如環氧樹脂（epoxy）。
參照圖1C，接著在重佈線層結構12上形成包封體（encapsulant）20，以包封晶粒17的側壁、晶粒17的第一表面17a及底部填充膠層19的側壁。在一些實施例中，包封體20包含模塑化合物、模塑底部填充膠、樹脂（例如環氧樹脂）、其組合或其類似物。在另一些實施例中，包封體20包含可輕易地藉由曝光及顯影製程（exposure and development process）或雷射鑽孔製程（laser drilling process）來圖案化的感光性材料，例如聚苯並惡唑、聚醯亞胺、苯並環丁烯、其組合或其類似物。在替代性實施例中，包封體20包含：氮化物（例如氮化矽）、氧化物（例如氧化矽）、磷矽酸鹽玻璃（phosphosilicate glass，PSG）、硼矽酸鹽玻璃（borosilicate glass，BSG）、摻雜硼的磷矽酸鹽玻璃（boron-doped phosphosilicate glass，BPSG）、其組合或其類似物。包封體20例如是藉由旋轉塗佈、疊層、沉積、或相似的製程等適合的製作技術形成。在一些實施例中，包封體20的頂表面高於晶粒17的第一表面17a或位於晶粒17的第一表面17a之上，使得晶粒17的第一表面17a被包封體20包封。然而，本揭露並非僅限於此。
參照圖1D，在一些實施例中，接著在晶粒17及包封體20之上形成保護層（protection layer）21。換句話說，保護層21是形成在晶粒17背側（與前側相對）的背側膜。在一些實施例中，保護層21完全覆蓋包封體20的頂表面。在一些實施例中，保護層21被稱作翹曲控制層（warpage control layer），且優選地向其下伏結構（即，位於其下方的結構）提供足夠程度的剛性（rigidity）以控制其下伏結構的翹曲。保護層21可包括單層結構或多層結構。在一些實施例中，保護層21包含無機材料、有機材料或其組合。無機材料包括氮化矽、低溫氮化物（例如氮化鋁、氮化鎵、氮化鋁鎵（aluminum gallium nitride））或其組合。有機材料包括聚合物，例如聚苯並惡唑、聚醯亞胺、苯並環丁烯、味之素堆積膜（ajinomoto buildup film，ABF）、阻銲膜（solder resist film，SR）、其類似物或其組合。然而，本揭露並非僅限於此，保護層21可包含任意種類的材料，只要所述材料向其下伏結構提供抵抗翹曲及扭曲（twisting）的足夠程度的剛性即可。保護層21例如是藉由適合的製作技術形成，例如旋轉塗佈、疊層、化學氣相沉積（CVD）、等離子體增強型化學氣相沉積（PECVD）或類似製程。在一些實施例中，保護層21的厚度T1的範圍為5微米（μm）至100 μm。
參照圖1E，將剝離層11在光熱作用下分解，且接著將載板10從其上覆結構脫離。在一些實施例中，在載板10脫離之前，將框架膠帶（frame tape）（圖中未示出）貼合到保護層21，且在載板10脫離之後移除所述框架膠帶。之後，重佈線層RDL1暴露出來，以在後續製程中用於電性連接。在一些實施例中，重佈線層RDL1包括重佈線層RDL1a及重佈線層RDL1b。重佈線層RDL1a也被稱作球下金屬（under-ball metallurgy，UBM）層，所述球下金屬層用於植球。重佈線層RDL1b可為在後續製程中用以與積體被動裝置（integrated passive device，IPD）24連接的微凸塊（micro bump）。
參照圖1E及圖1F，在重佈線層結構12的重佈線層RDL1a上形成多個連接件23，所述多個連接件23與重佈線層結構12的重佈線層RDL1a電性連接。在一些實施例中，連接件23被稱作導電端子。在一些實施例中，連接件23例如是銲料球（solder ball）或球陣列（BGA）球。在一些實施例中，連接件23的材料包括銅、鋁、無鉛合金（例如，金合金、錫合金、銀合金、鋁合金或銅合金）或鉛合金（例如，鉛-錫合金）。在一些實施例中，連接件23藉由植球製程放置在重佈線層RDL1a上。
仍然參照圖1F，在一些實施例中，將包括多個接墊25的積體被動裝置（IPD）24藉由位於積體被動裝置24與重佈線層RDL1b之間的多個導電凸塊26電性連接至重佈線層RDL1b。積體被動裝置24可為電容器、電阻器、電感器、其類似物或其組合。積體被動裝置24可被選擇性地連接到重佈線層結構12，且積體被動裝置24的數目並非僅限於圖1F中所示的數目，而是可根據產品的設計來進行調整。形成底部填充膠層27，填充於積體被動裝置24與重佈線層結構12之間。底部填充膠層27覆蓋積體被動裝置24的部分表面及重佈線層結構12的部分底表面，且環繞積體被動裝置24的接墊25以及導電凸塊26。底部填充膠層27的材料與底部填充膠層19的材料相似，在此不再贅述。
仍然參照圖1F，至此，封裝結構50a即已完成。封裝結構50a包括晶粒17、包封體20、重佈線層結構12、連接件23、積體被動裝置24及保護層21。連接件23及積體被動裝置24藉由重佈線層結構12與晶粒17電性連接。保護層21被形成用於控制封裝結構50a的翹曲，也就是說，保護層21向封裝結構50a提供抵抗翹曲及扭曲的足夠程度的剛性。此後，封裝結構50a可藉由連接件23連接到其他封裝元件，例如印刷電路板（printed circuit board，PCB）、軟性印刷電路板（flex PCB）或其類似物。
在封裝結構50a中，包封體20包封晶粒17的側壁及第一表面17a。然而，本揭露並非僅限於此。
參照圖2A，進行與圖1A至圖1C所示製程相似的製程，在一些實施例中，在如圖1C中所示形成包封體20之後，進行研磨或拋光製程（例如化學機械拋光（chemical mechanical polishing，CMP）製程），以移除部分包封體20，使得晶粒17的第一表面17a暴露出來，並形成包封晶粒17的側壁的包封體20a。在一些實施例中，包封體20a的頂表面與晶粒17的第一表面17a實質上共面。
參照圖2B，在形成包封體20a之後，隨後進行與圖1D至圖1F所示製程相似的製程，以形成封裝結構50b。封裝結構50b與封裝結構50a的不同之處在於包封體20a的頂表面與晶粒17的第一表面17a實質上齊平，且保護層21與包封體20a的頂表面及晶粒17的第一表面17a接觸。在一些實施例中，保護層21完全覆蓋包封體20a的頂表面及晶粒17的第一表面17a。封裝結構50b的其他結構特性與封裝結構50a的結構特性相似，於此不再贅述。
圖3A至圖3H是示出根據本揭露第二實施例的製造封裝結構的方法的示意性剖視圖。第二實施例與第一實施例的不同之處在於在晶粒17側邊形成多個積體扇出型通孔（through integrated fan-out via，TIV）28。
參照圖3A，與圖2A及圖2B所示製程相似，在載板10之上形成包括聚合物層PM1、PM2、PM3、PM4及重佈線層RDL1、RDL2、RDL3、RDL4的重佈線層結構12。在一些實施例中，重佈線層RDL4包括重佈線層RDL4a及重佈線層RDL4b。重佈線層RDL4b位於重佈線層RDL4a側邊，環繞重佈線層RDL4a。在重佈線層RDL4a上放置晶粒17，晶粒17藉由多個導電凸塊18與重佈線層RDL4a電性連接。形成底部填充膠層19，填充於晶粒17與重佈線層結構12之間。晶粒17、重佈線層結構12、導電凸塊18及底部填充膠層19的結構特性與第一實施例中的結構特性相似，於此不再贅述。
在重佈線層RDL4b上形成多個積體扇出型通孔28，所述多個積體扇出型通孔28與重佈線層RDL4b電性連接。在一些實施例中，積體扇出型通孔28包含銅、鎳、銲料、其合金或其類似物。在一些實施例中，積體扇出型通孔28包括晶種層及形成在所述晶種層上的導電層（圖中未示出）。所述晶種層例如為鈦或/及銅複合層。所述導電層例如為銅層。積體扇出型通孔28的示例性形成方法包括在載板10之上形成光阻層（photoresist layer）（例如乾膜光阻（dry film resist））。之後，在光阻層中形成開口，所述開口暴露出重佈線層RDL4b的部分頂表面，接著藉由電鍍在所述開口中形成積體扇出型通孔（via）28。在另一些實施例中，積體扇出型通孔28更包括位於晶種層下方的阻擋層（barrier layer）（圖中未示出），以防止金屬擴散。舉例來說，阻擋層的材料包括金屬氮化物，例如氮化鈦、氮化鉭或其組合。
仍然參照圖3A，晶粒17位於積體扇出型通孔28之間，被積體扇出型通孔28環繞，也就是說，積體扇出型通孔28位於晶粒17側邊或環繞晶粒17。在一些實施例中，積體扇出型通孔28的頂表面高於晶粒17的第一表面17a，但本揭露並非僅限於此。在另一些實施例中，積體扇出型通孔28的頂表面與晶粒17的第一表面17a實質上齊平。
參照圖3B，在重佈線層結構12之上形成包封體20，以包封積體扇出型通孔28的側壁、重佈線層RDL4b的側壁以及部分表面、底部填充膠層19的側壁、晶粒17的側壁及第一表面17a。包封體20的材料與第一實施例中包封體20的材料相似。包封體20可藉由以下方式形成：在載板10之上形成包封材料層，包封材料層包封晶粒17的頂表面及側壁以及積體扇出型通孔28的頂表面及側壁。之後，進行研磨或拋光製程，以移除部分包封材料層，使得積體扇出型通孔28的頂表面暴露出來。在一些實施例中，積體扇出型通孔28的頂表面與包封體20的頂表面實質上共面，且高於晶粒17的第一表面17a或位於晶粒17的第一表面17a之上，但本揭露並非僅限於此。
參照圖3B及圖3C，接著在晶粒17、包封體20及積體扇出型通孔28之上形成保護層21。在一些實施例中，保護層21被稱作翹曲控制層。保護層21的材料及形成方法與第一實施例中保護層21的材料及形成方法相似。
參照圖3C及圖3D，移除部分保護層21，以形成多個開口29。移除方法包括曝光及顯影製程、雷射鑽孔製程、微影及蝕刻製程或其組合。開口29穿透保護層21，以暴露出積體扇出型通孔28的部分頂表面。開口29也被稱作凹槽（recess）。
仍然參照圖3D，之後，在開口29中及積體扇出型通孔28上形成多個頂蓋（cap）30。在一些實施例中，頂蓋30被形成以用於保護積體扇出型通孔28免受氧化或污染。頂蓋30包含金屬、有機材料或其組合。在一些實施例中，頂蓋30包含銲料、銲料膏黏合劑（solder paste adhesive）或其組合，頂蓋30可藉由在開口29中滴入銲料球並接著進行回銲製程（reflow process）來形成。在另一些實施例中，頂蓋30包含有機材料，例如有機可銲性保護劑（organic solderability preservative，OSP），且頂蓋30被稱作有機可銲性保護劑層，例如銅有機可銲性保護劑層。在一些實施例中，有機可銲性保護劑層包含苯並三唑、苯並咪唑、其組合或其衍生物。在一些實施例中，有機可銲性保護劑層是藉由塗佈（coating）形成，且有機可銲性保護劑塗層是藉由以下方式來塗覆：將開口29中暴露出的積體扇出型通孔28的表面浸沒在有機可銲性保護劑溶液中，或者將有機可銲性保護劑溶液噴塗在開口29中暴露出的積體扇出型通孔28的表面上。有機可銲性保護劑溶液可含有烷基咪唑（alkylimidazole）、苯並三唑、松香（rosin）、松香酯或苯並咪唑化合物。或者，有機可銲性保護劑塗層是由苯基咪唑（phenylimidazole）或包含2-芳基咪唑（2-arylimidazole）作為活性成分的其他咪唑化合物製成。
在一些實施例中，頂蓋30被形成在開口29內，且頂蓋30的頂表面低於保護層21的頂表面，但本揭露並非僅限於此。在另一些實施例中，頂蓋30可填滿開口29並從保護層21的頂表面突出。頂蓋30的橫截面形狀可為倒梯形、具有弧形底邊（arced base）的倒梯形、正方形、矩形、半圓形或任何其他形狀，只要頂蓋30覆蓋積體扇出型通孔28以保護積體扇出型通孔28免受氧化即可。
參照圖3E及圖3F，進行與圖1E及圖1F相似的製程，以形成封裝結構50c。使剝離層11在光熱作用下分解，且接著將載板10從其上覆結構脫離。之後，在重佈線層結構12的重佈線層RDL1a上形成多個連接件23，所述多個連接件23與重佈線層結構12的重佈線層RDL1a電性連接。積體被動裝置24藉由多個導電凸塊26與重佈線層RDL1b電性連接。
參照圖3F，至此，封裝結構50c即已完成。封裝結構50c包括晶粒17、包封體20、積體扇出型通孔28、重佈線層結構12、連接件23、積體被動裝置24及保護層21。保護層21覆蓋並接觸包封體20的頂表面及積體扇出型通孔28的部分頂表面。保護層21具有暴露出積體扇出型通孔28的多個開口29，且在開口29中具有多個頂蓋30，以保護積體扇出型通孔28免受氧化或污染。也就是說，積體扇出型通孔28的部分頂表面被保護層21覆蓋，積體扇出型通孔28的另一部分頂表面被頂蓋30覆蓋。
參照圖3G及圖3H，在一些實施例中，封裝結構50c進一步連接至封裝結構60，以形成疊層封裝（PoP）裝置70a。
參照圖3G，提供封裝結構60。根據疊層封裝裝置70a的功能性需求，封裝結構60可為任意種類的封裝結構。在一些實施例中，封裝結構60包括封裝本體61及與封裝本體61連接的多個連接件62。在一些實施例中，連接件62被稱作導電端子。連接件62的材料及形成方法與封裝結構50c的連接件23的材料及形成方法相似。在一些實施例中，連接件62位於與封裝結構50c的開口29的位置對應的位置處。
參照圖3G及圖3H，至少對連接件62進行回銲製程，進而形成連接件62a，以連接封裝結構50c與封裝結構60。連接件62a與積體扇出型通孔28電性接觸。在一些頂蓋30是由銲料、銲料膏黏合劑或其組合形成的實施例中，在回銲製程期間頂蓋30熔化並與連接件62熔融在一起，也就是說，連接件62a是由連接件62及頂蓋30形成。在一些頂蓋30為有機可銲性保護劑層的實施例中，在進行回銲製程之前，進行清潔製程（cleaning process）以移除頂蓋30，也就是說，連接件62a是由連接件62形成。
參照圖3H，在一些實施例中，形成底部填充膠層63，填充於封裝結構50c與封裝結構60之間，並環繞連接件62a。至此，包含封裝結構50c及封裝結構60的疊層封裝裝置70a即已完成，封裝結構50c與封裝結構60藉由連接件62a進行連接。如圖3H中所示的疊層封裝裝置70a僅用於示例說明，且本揭露並非僅限於此。
參照圖3B、圖4A及圖4B，在另一些實施例中，在如圖3B所示形成包封體20之後，進行研磨或拋光製程，使得積體扇出型通孔28的頂表面及晶粒17的第一表面17a暴露出來，並形成包封體20a。在一些積體扇出型通孔28被形成為具有比晶粒17的第一表面17a高的頂表面的實施例中，部分包封體20及部分積體扇出型通孔28在研磨或拋光製程中被移除。在一些積體扇出型通孔28被形成為具有與晶粒17的第一表面17a實質上齊平的頂表面的實施例中，部分包封體20在研磨或拋光製程期間被移除。在一些實施例中，積體扇出型通孔28的頂表面、包封體20a的頂表面及晶粒17的第一表面17a彼此實質上共面。換句話說，保護層21與晶粒17的第一表面17a、積體扇出型通孔28的頂表面及包封體20a的頂表面接觸。在一些實施例中，保護層21完全覆蓋晶粒17的第一表面17a、積體扇出型通孔28的頂表面及包封體20a的頂表面。
參照圖4B，接著進行與圖3C至圖3F所示製程相似的製程，以形成封裝結構50d。
參照圖3F及圖4B，封裝結構50d與封裝結構50c的不同之處在於積體扇出型通孔28的頂表面、包封體20a的頂表面及晶粒17的第一表面17a彼此共面，且保護層21與晶粒17的第一表面17a接觸。封裝結構50d的其他結構特性與封裝結構50c的結構特性相似。類似地，封裝結構50d可進一步連接至其他封裝結構以形成疊層封裝裝置。
參照圖4B及圖4C，進行與圖3G至圖3H所示製程相似的製程，使得封裝結構50d與封裝結構60連接，以形成疊層封裝裝置70b。
圖5A至圖5B是示出根據本揭露第三實施例的製造封裝結構的方法的示意性剖視圖。第三實施例與前述實施例的不同之處在於在晶粒17的背側形成保護層121。在一些實施例中，保護層121充當翹曲控制層及散熱體（heat spreader）。
參照圖2A及圖5A，在一些實施例中，在晶粒17側邊形成包封體20a之後，包封體20a的頂表面與晶粒17的第一表面17a形成表面31。將保護層121藉由黏合層32貼合到表面31。黏合層32與晶粒17及包封體20a接觸。在一些實施例中，保護層121為板材（plate）或片材（sheet），做為用於防止或減少下伏結構翹曲的翹曲控制層，以及做為將熱量從晶粒17傳導出的散熱體。在一些實施例中，黏合層32也可有助於將熱量從晶粒17傳導出。
保護層121可包含單一材料或複合材料，且可為單層結構或多層結構。在一些實施例中，保護層121包含導熱材料，且導熱率（thermal conductivity）大於晶粒17及包封體20a的導熱率。在一些實施例中，保護層121包含導電材料且是浮置（floating）的，也就是說，保護層121不與任何其他層電性連接。在一些實施例中，保護層121包含剛性金屬（例如，銅、鋼或其組合）、陶瓷材料、含矽材料、金剛石或其組合。在一些實施例中，保護層121為銅層、鋼層或金剛石膜。在另一些實施例中，保護層121包含由基質材料（matrix material）及填料（filler）構成的複合材料。在一些實施例中，基質材料包括石墨、石墨烯、聚合物或其組合。填料包括金剛石、氧化物（例如氧化鋁或氧化矽）、碳化物（例如碳化矽）或其組合。然而，保護層121的材料並不僅限於上述材料，保護層121可包含任何材料，只要保護層121優選地提供足夠程度的剛性以防止或減少其下伏結構的翹曲，且可有效地將熱量從晶粒17傳導出即可。
在一些實施例中，黏合層32包括晶粒貼合膜（die attach film，DAF）、熱介面材料（thermal interface material，TIM）或其組合。在一些實施例中，黏合層32的材料也為導熱的，且其導熱率大於晶粒17及包封體20a的導熱率。在一些實施例中，黏合層32的導熱率與保護層121的導熱率可相同或不同。在一些實施例中，黏合層32的導熱率可大於或小於保護層121的導熱率。
仍然參照圖5A，在一些實施例中，保護層121的厚度T2的範圍為30 μm至400 μm。保護層121的厚度T2取決於保護層121的材料。在一些保護層121為金剛石膜的實施例中，保護層121的厚度T2可小於30 μm。在一些實施例中，保護層121的寬度W1實質上與表面31的寬度W2相同。晶粒17的第一表面17a及包封體20a的頂表面被保護層121覆蓋。在一些實施例中，晶粒17的第一表面17a及包封體20a的頂表面被保護層121完全覆蓋。在另一些實施例中，保護層121的寬度W1小於表面31的寬度W2，且大於晶粒17的寬度W3。也就是說，晶粒17的第一表面17a以及包封體20a的部分頂表面被保護層121覆蓋。在又一替代性實施例中，保護層121的寬度W1可實質上相同於或略小於晶粒17的第一表面17a的寬度W3，以使晶粒17的第一表面17a被保護層121覆蓋或部分覆蓋。也就是說，可調整保護層121的厚度T2及寬度W1，只要保護層121提供實現本揭露的目的所必需的性質即可。
參照圖5A及圖5B，之後，進行與圖1E至圖1F所示製程相似的製程，以使剝離層11在光熱作用下分解，進而使載板10脫離。之後，將多個連接件23電性連接至重佈線層結構12的重佈線層RDL1a。積體被動裝置24藉由多個導電凸塊26電性連接至重佈線層RDL1b。
參照圖5B，至此，封裝結構50e即已完成。封裝結構50e包括晶粒17、包封體20a、重佈線層結構12、連接件23、積體被動裝置24及保護層121。在一些實施例中，保護層121用於控制封裝結構50e的翹曲且用於對晶粒17進行散熱。封裝結構50e的其他結構特性與封裝結構50b的結構特性相似。
圖6A至圖6D是示出根據本揭露第四實施例的製造封裝結構的方法的示意性剖視圖。第四實施例與第三實施例的不同之處在於在晶粒17側邊形成多個積體扇出型通孔28。
參照圖6A，在晶粒17側邊形成積體扇出型通孔28及包封體20a（如圖4A中所示）之後，將保護層121藉由黏合層32貼合至晶粒17及包封體20a。在一些實施例中，保護層121覆蓋晶粒17的第一表面17a以及包封體20a的部分頂表面。積體扇出型通孔28不被保護層121覆蓋，而暴露出來。在另一些實施例中，保護層121僅覆蓋或部分覆蓋晶粒17的第一表面17a，且不覆蓋包封體20a的頂表面及積體扇出型通孔28。保護層121的材料及黏合層32的材料與第三實施例中的保護層的材料及黏合層的材料實質上相同。
參照圖6A及圖6B，在積體扇出型通孔28上形成多個頂蓋30，以至少覆蓋積體扇出型通孔28的頂表面。在一些實施例中，積體扇出型通孔28的頂表面被頂蓋30完全覆蓋。在一些實施例中，積體扇出型通孔28的頂表面以及包封體20a的部分頂表面被頂蓋30覆蓋。頂蓋30的材料、形成方法及性質與第二實施例的頂蓋的材料、形成方法及性質相似。在一些實施例中，頂蓋30的橫截面形狀可為半圓形、弧形、正方形、矩形、梯形或其組合。頂蓋30可為任何形狀，只要積體扇出型通孔28被覆蓋保護，而免受氧化或污染即可。
仍然參照圖6A及圖6B，藉由使剝離層11在光熱作用下分解而將載板10脫離。之後，將多個連接件23電性連接至重佈線層結構12的重佈線層RDL1a。將積體被動裝置24藉由多個導電凸塊26電性連接至重佈線層RDL1b。
參照圖6B，至此，封裝結構50f即已完成。封裝結構50f包括晶粒17、包封體20a、積體扇出型通孔28、重佈線層結構12、連接件23、積體被動裝置24及保護層121。積體扇出型通孔28被頂蓋30覆蓋。在一些實施例中，積體扇出型通孔28被覆蓋保護，以防止氧化或污染。在一些實施例中，保護層121用於控制封裝結構50f的翹曲以及對晶粒17進行散熱。封裝結構50f可進一步耦合至其他封裝結構，以形成疊層封裝裝置。
參照圖6C及圖6D，在一些實施例中，提供封裝結構60，其包括封裝本體61及多個連接件62，接著進行回銲製程，以形成連接件62a，連接封裝結構50f與封裝結構60。與第二實施例相似，連接件62a可由連接件62形成或由連接件62及頂蓋30形成，連接件62a的形成方法與如圖3G至圖3H中所示第二實施例的連接件的形成方法相似。
之後，形成底部填充膠層63，填充於封裝結構50f與封裝結構60之間。至此，疊層封裝裝置70c即已完成。
在第二實施例及第四實施例中，如圖3H、圖4C及圖6D中所示，封裝結構50c、50d、50f與封裝結構60連接，以形成疊層封裝裝置70a、70b、70c，然而，可耦合至封裝結構50c、50d、50f的封裝結構的數目並非僅限於此。在另一些實施例中，有多於一個的封裝結構連接至封裝結構50c、50d、50f，且積體被動裝置也可耦合至封裝結構50c、50d、50f。為簡明起見，以封裝結構50c為例。
參照圖7，在一些實施例中，形成包括封裝結構50c、封裝結構60及封裝結構64的疊層封裝裝置70d。封裝結構50c包括多個積體扇出型通孔28。積體扇出型通孔28包括多個積體扇出型通孔28a及多個積體扇出型通孔28b。積體扇出型通孔28a位於晶粒17側邊及周圍。積體扇出型通孔28b位於積體扇出型通孔28a側邊，且與積體扇出型通孔28a相比相對更遠離晶粒17，也就是說，沒有晶粒被積體扇出型通孔28b環繞，但本揭露並非僅限於此。
仍然參照圖7，封裝結構60藉由連接件62a電性耦合至封裝結構50c。藉由與如圖3G至圖3H所述方法相似的方法，將封裝結構64藉由連接件65電性耦合至封裝結構50c。封裝結構60及封裝結構64可為相同類型或不同類型的封裝結構。封裝結構60連接至封裝結構50c的積體扇出型通孔28a，封裝結構64連接至封裝結構50c的積體扇出型通孔28b。
參照圖8，在一些實施例中，除封裝結構60及封裝結構64耦合至封裝結構50c以外，還有積體被動裝置66藉由多個連接件67電性耦合至封裝結構50c，至此，疊層封裝裝置70e即已完成。積體被動裝置66可為電容器、電阻器、電感器、其類似物或其組合。在一些實施例中，積體扇出型通孔28包括位於積體扇出型通孔28a與積體扇出型通孔28b之間的多個積體扇出型通孔28c。封裝結構60連接至積體扇出型通孔28a。在一些實施例中，封裝結構64連接至積體扇出型通孔28b。積體被動裝置66連接至積體扇出型通孔28c。積體被動裝置66位於封裝結構60與封裝結構64之間，但本揭露並非僅限於此。
在本揭露中，在晶粒的背側形成保護層。在一些實施例中，保護層充當翹曲控制層以控制封裝結構的翹曲。在一些實施例中，保護層還充當晶粒的散熱體。
根據本揭露的一些實施例，提供一種封裝結構，所述封裝結構包括晶粒、包封體、重佈線層結構及保護層。晶粒包括彼此相對的第一表面與第二表面。包封體位於晶粒側邊。重佈線層結構藉由多個導電凸塊與晶粒電性連接。重佈線層結構位於晶粒的第二表面及包封體下方。保護層位於晶粒的第一表面及包封體之上。保護層用於控制封裝結構的翹曲。
在上述封裝結構中，晶粒的第二表面是面對重佈線層結構的主動表面。
在上述封裝結構中，包封體的頂表面位於晶粒的第一表面之上，且包封體包封晶粒的側壁。
在上述封裝結構中，包封體的頂表面與晶粒的第一表面實質上共面。
在上述封裝結構中，保護層包含氮化矽、聚合物或其組合。
在上述封裝結構中，更包括位於保護層與晶粒之間的黏合層。
在上述封裝結構中，保護層及黏合層至少覆蓋晶粒的部分第一表面，且黏合層與晶粒的第一表面接觸。
在上述封裝結構中，保護層用作散熱體。
在上述封裝結構中，保護層包含銅、鋼或包含基質材料及填料的複合材料。
根據本揭露的一些實施例，提供一種封裝結構，所述封裝結構包括晶粒、積體扇出型通孔、包封體、重佈線層結構、保護層及頂蓋。積體扇出型通孔位於晶粒側邊。包封體包封積體扇出型通孔的側壁及晶粒的側壁。重佈線層結構藉由多個導電凸塊與晶粒電性連接。保護層位於包封體、積體扇出型通孔及晶粒之上。頂蓋位於積體扇出型通孔上，覆蓋積體扇出型通孔的部分頂表面。保護層用於控制封裝結構的翹曲。
在上述封裝結構中，頂蓋位於保護層的凹槽中，以覆蓋在凹槽中暴露出的積體扇出型通孔的頂表面。
在上述封裝結構中，包封體的頂表面、積體扇出型通孔的頂表面及晶粒的頂表面彼此實質上共面。
在上述封裝結構中，包封體更包封晶粒的頂表面，且積體扇出型通孔的頂表面及包封體的頂表面位於晶粒的頂表面之上。
在上述封裝結構中，更包括位於保護層與晶粒之間的黏合層，其中保護層至少覆蓋晶粒的部分第一表面，且保護層用做晶粒的散熱體。
在上述封裝結構中，重佈線層結構電性連接至另一封裝結構，以形成疊層封裝（PoP）裝置，其中重佈線層結構包括至少三個重佈線層且不含有基底。
根據本揭露的一些實施例，提供一種製造封裝結構的方法。將晶粒藉由多個導電凸塊連接至重佈線層結構。形成包封體以至少包封晶粒的側壁。在包封體及晶粒之上形成保護層，以控制封裝結構的翹曲。
在上述製造封裝結構的方法中，更包括在形成包封體之前，在晶粒側邊形成積體扇出型通孔，其中包封體更包封積體扇出型通孔的側壁。
在上述製造封裝結構的方法中，更包括在積體扇出型通孔上形成頂蓋，其中頂蓋覆蓋積體扇出型通孔的部分頂表面。
在上述製造封裝結構的方法中，在形成頂蓋之前，移除部分保護層，以形成凹槽，所述凹槽暴露出積體扇出型通孔的部分頂表面，且頂蓋形成在凹槽中。
在上述製造封裝結構的方法中，更包括將保護層藉由黏合層貼合至晶粒，其中積體扇出型通孔的頂表面及包封體的部分頂表面不被保護層覆蓋。
以上概述了數個實施例的特徵，使本領域具有通常知識者可更佳瞭解本揭露的態樣。本領域具有通常知識者應理解，其可輕易地使用本揭露做為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本揭露的精神與範疇，且本領域具有通常知識者在不悖離本揭露的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
10‧‧‧載板
11‧‧‧剝離層
12‧‧‧重佈線層結構
13‧‧‧基底
14、25‧‧‧接墊
15‧‧‧鈍化層
16、23、62、62a、65、67‧‧‧連接件
17‧‧‧晶粒
17a‧‧‧第一表面
17b‧‧‧第二表面/主動表面
18、26‧‧‧導電凸塊
19、27、63‧‧‧底部填充膠層
20、20a‧‧‧包封體
21、121‧‧‧保護層
24、66‧‧‧積體被動裝置
28、28a、28b、28c‧‧‧積體扇出型通孔
29‧‧‧開口
30‧‧‧頂蓋
31‧‧‧表面
32‧‧‧黏合層
50a、50b、50c、50d、50e、50f、60、64‧‧‧封裝結構
61‧‧‧封裝本體
70a、70b、70c、70d、70e‧‧‧疊層封裝裝置
PM1、PM2、PM3、PM4‧‧‧聚合物層
RDL1、RDL1a、RDL1b、RDL2、RDL3、RDL4、RDL4a、RDL4b‧‧‧重佈線層
T‧‧‧跡線
T1、T2‧‧‧厚度
V‧‧‧通孔
W1、W2、W3、W10、W20‧‧‧寬度
θ‧‧‧底角
圖1A至圖1F是示出根據本揭露第一實施例的製造封裝結構的方法的示意性剖視圖。 圖2A至圖2B是示出根據本揭露一些實施例的製造封裝結構的方法的示意性剖視圖。 圖3A至圖3H是示出根據本揭露第二實施例的製造封裝結構的方法的示意性剖視圖。 圖4A至圖4C是示出根據本揭露一些實施例的製造封裝結構的方法的示意性剖視圖。 圖5A至圖5B是示出根據本揭露第三實施例的製造封裝結構的方法的示意性剖視圖。 圖6A至圖6D是示出根據本揭露第四實施例的製造封裝結構的方法的示意性剖視圖。 圖7及圖8分別示出根據本揭露一些實施例的疊層封裝裝置。

Claims (1)

  1. 一種封裝結構，包括： 晶粒，其中所述晶粒包括彼此相對的第一表面與第二表面； 包封體，位於所述晶粒側邊； 重佈線層結構，藉由多個導電凸塊與所述晶粒電性連接，其中所述重佈線層結構位於所述晶粒的所述第二表面及所述包封體下方；以及 保護層，位於所述晶粒的所述第一表面及所述包封體之上， 其中所述保護層用於控制所述封裝結構的翹曲。
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US20200343096A1 (en) 2020-10-29
US11295957B2 (en) 2022-04-05

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