TWI541966B - 封裝堆疊結構及其製法 - Google Patents

封裝堆疊結構及其製法 Download PDF

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Publication number
TWI541966B
TWI541966B TW103107386A TW103107386A TWI541966B TW I541966 B TWI541966 B TW I541966B TW 103107386 A TW103107386 A TW 103107386A TW 103107386 A TW103107386 A TW 103107386A TW I541966 B TWI541966 B TW I541966B
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Taiwan
Prior art keywords
package
stack structure
conductive
package substrate
electronic component
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TW103107386A
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English (en)
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TW201535644A (zh
Inventor
徐逐崎
王隆源
江政嘉
施嘉凱
黃淑惠
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矽品精密工業股份有限公司
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Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW103107386A priority Critical patent/TWI541966B/zh
Priority to CN201410089037.6A priority patent/CN104900596B/zh
Priority to US14/452,871 priority patent/US9343387B2/en
Publication of TW201535644A publication Critical patent/TW201535644A/zh
Application granted granted Critical
Publication of TWI541966B publication Critical patent/TWI541966B/zh

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Description

封裝堆疊結構及其製法
本發明係有關一種封裝結構，尤指一種封裝堆疊結構及其製法。
隨著近年來可攜式電子產品的蓬勃發展，各類相關產品逐漸朝向高密度、高性能以及輕、薄、短、小之趨勢而走，各式樣封裝層疊(package on package，PoP)也因而配合推陳出新，以期能符合輕薄短小與高密度的要求。
如第1圖所示，係為習知封裝堆疊裝置1的剖視示意圖。如第1圖所示，該封裝堆疊裝置1包括兩相疊之封裝結構1a與另一封裝結構1b。
封裝結構1a係包含具有相對之第一及第二表面11a,11b之第一基板11、覆晶結合該第一基板11之第一電子元件10、設於該第一表面11a上之電性接觸墊111、形成於該第一基板11上以包覆該第一電子元件10之第一封裝膠體13、形成於該第一封裝膠體13之開孔130中之電性接觸墊111上之銲錫材114、以及設於該第二表面11b上用於結合銲球14之植球墊112。
另一封裝結構1b係包含第二基板12、以打線方式結合於該 第二基板12上之第二電子元件15a,15b、及形成於該第二基板12上以包覆該第二電子元件15a,15b之第二封裝膠體16，令該第二基板12藉由銲錫材114疊設且電性連接於該第一基板11之電性接觸墊111上。
惟，習知封裝堆疊裝置1中，由於該第一與第二基板11,12間係以銲錫材114作為支撐與電性連接之元件，而隨著電子產品的接點(即I/O)數量愈來愈多，在封裝件的尺寸大小不變的情況下，各該銲錫材114間的間距需縮小，致使容易發生橋接(bridge)的現象，因而造成產品良率過低及可靠度不佳等問題，致使無法用於更精密之細間距產品。
再者，因該銲錫材114於回銲後之體積及高度之公差大，即尺寸變異不易控制，致使不僅接點容易產生缺陷(例如，於回銲時，該銲錫材114會先變成軟塌狀態，同時於承受上方第二基板12的重量後，該銲錫材114容易塌扁變形，繼而與鄰近該銲錫材114橋接)，導致電性連接品質不良，且該銲錫材114所排列成之柵狀陣列(grid array)容易產生共面性(coplanarity)不良，導致接點應力(stress)不平衡而容易造成該兩封裝結構之間呈傾斜接置，甚至產生接點偏移之問題。
另外，該兩封裝結構之間僅藉由該銲錫材114作支撐，將因該兩封裝結構之間的空隙d過多，導致該第一與第二基板11,12容易發生翹曲(warpage)。
因此，如何克服習知技術中之種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之種種缺失，本發明係提供一種封裝堆疊結構，係包括：封裝基板，係具有複數導電凸塊，該導電凸塊係具有金屬球與包覆該金屬球之銲錫材；以及電子元件，係具有複數金屬柱，且該些金屬柱對應結合該些導電凸塊，使該電子元件堆疊於該封裝基板上，並令該金屬柱與該導電凸塊形成導電元件。
本發明復提供一種封裝堆疊結構之製法，係包括：提供一封裝基板與一具有複數金屬柱之電子元件，該封裝基板上具有複數導電凸塊，該導電凸塊係具有金屬球與包覆該金屬球之銲錫材；以及對應結合該金屬柱與該導電凸塊，使該電子元件堆疊於該封裝基板上，令該金屬柱與該導電凸塊形成導電元件。
前述之封裝堆疊結構及其製法中，該導電凸塊復具有位於該金屬球中之絕緣體。
前述之封裝堆疊結構及其製法中，該電子元件係為另一封裝基板或半導體元件。
前述之封裝堆疊結構及其製法中，形成該導電元件後，該金屬柱係接觸該金屬球。
前述之封裝堆疊結構及其製法中，復包括設置半導體元件於該封裝基板上，且該半導體元件位於該電子元件與該封裝基板之間。又包括形成底膠於該封裝基板與該半導體元件之間。
前述之封裝堆疊結構及其製法中，復包括於對應結合該金屬柱與該導電凸塊之後，形成封裝材於該電子元件與該封裝基板之間，以包覆該些導電元件。
另外，前述之封裝堆疊結構及其製法中，復包括於對應結合該金屬柱與該導電凸塊之前，形成封裝材於該封裝基板上，以包 覆該些導電凸塊，再形成複數開口於該封裝材上，以令該些導電凸塊對應外露於該些開口。
由上可知，本發明之封裝堆疊結構及其製法，係藉由該金屬球與該金屬柱之對接，以利於堆疊作業，且藉由該金屬球與該金屬柱之尺寸變異易於控制，使其可克服堆疊結構間傾斜接置及接點偏移之問題。
再者，該電子元件與該封裝基板之間不僅藉由該導電元件作支撐，且藉由該封裝膠體填滿該電子元件與該封裝基板之間的空隙，故可避免該電子元件與該封裝基板發生翹曲。
1‧‧‧封裝堆疊裝置
1a、1b‧‧‧封裝結構
10‧‧‧第一電子元件
101、36‧‧‧底膠
11‧‧‧第一基板
11a、21a‧‧‧第一表面
11b、21b‧‧‧第二表面
111、211b、221b‧‧‧電性接觸墊
112、212‧‧‧植球墊
114、211‧‧‧銲錫材
12‧‧‧第二基板
13‧‧‧第一封裝膠體
130、213a、223a‧‧‧開孔
14、24‧‧‧銲球
15a、15b‧‧‧第二電子元件
16‧‧‧第二封裝膠體
2、3、3’‧‧‧封裝堆疊結構
20‧‧‧半導體元件
200、320‧‧‧電極墊
200a‧‧‧銲錫凸塊
21‧‧‧封裝基板
210a、210a’‧‧‧導電凸塊
210‧‧‧金屬球
210’‧‧‧絕緣體
211a、221a‧‧‧銲墊
213、223‧‧‧絕緣保護層
22、32‧‧‧電子元件
22a‧‧‧第三表面
22b‧‧‧第四表面
22c‧‧‧基材
220‧‧‧金屬柱
23‧‧‧導電元件
25、35‧‧‧封裝材
32a‧‧‧作用面
32b‧‧‧非作用面
350‧‧‧開口
d‧‧‧空隙
第1圖係為習知封裝堆疊裝置之製法的剖視示意圖；第2A至2E圖係為係為本發明之封裝堆疊結構之製法之第一實施例的剖視示意圖；其中，第2A’圖係為第2A圖之其它態樣；以及第3A至3B圖係為本發明之封裝堆疊結構3之製法之第二實施例的剖視示意圖；其中，第3A’及3B’圖係為第3A及3B圖之其它態樣。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上 之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“下”、“第一”、“第二”、“第三”、“第四”、及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2E圖係為本發明之封裝堆疊結構2之製法之第一實施例的剖視示意圖。
如第2A圖所示，提供一封裝基板21，其上具有複數導電凸塊210a，該導電凸塊210a係具有金屬球210與包覆該金屬球210之銲錫材211，該銲錫材211利於後續之堆疊製程。
於本實施例中，該金屬球210之材質係為銅、錫鉛或錫銀，且於該金屬球210之材質係為銅時，該銲錫材211係為鎳錫，而於金屬球210之材質係為錫鉛或錫銀時，該銲錫材211係為與該金屬球210不同混合比例之錫鉛或錫銀。
再者，該封裝基板21具有相對之第一表面21a及第二表面21b，該第一表面21a上具有複數銲墊211a與複數電性接觸墊211b，且該第二表面21b上具有複數植球墊212，並於該封裝基板21之第一及第二表面21a,21b上具有例如防銲層之絕緣保護層213，該絕緣保護層213形成有複數開孔213a，以藉由該些開孔213a外露該些銲墊211a、電性接觸墊211b及植球墊212。
又，於該電性接觸墊211b之外露表面上形成該導電凸塊210a，且於該銲墊211a之外露表面上藉由銲錫凸塊200a設置一半 導體元件20，即該半導體元件20之電極墊200以覆晶方式電性連接該封裝基板21。其中，該半導體元件20係為主動元件或被動元件，並可使用複數個半導體元件20，且可選自主動元件、被動元件或其組合，該主動元件係例如：晶片，而該被動元件係例如：電阻、電容及電感。
另外，如第2A’圖所示，該導電凸塊210a’復具有埋於該金屬球210中之絕緣體210’，如塑膠球。
如第2B圖所示，提供一具有複數金屬柱220之電子元件22，且該金屬柱220之材質係為銅。
於本實施例中，該電子元件22係為封裝基板構形。具體地，提供一具有相對之第三表面22a及第四表面22b之基材22c，該第三表面22a上具有複數銲墊221a，且該第四表面22b上具有複數電性接觸墊221b，又該基材22c之第三及第四表面22a,22b上具有例如防銲層之絕緣保護層223，且該絕緣保護層223形成有複數開孔223a，以藉該些開孔223a外露該些銲墊221a及電性接觸墊221b。
再者，於該基材22c之電性接觸墊221b之外露表面上電鍍形成例如銅柱之金屬柱220。
如第2C圖所示，對應結合該金屬柱220與該導電凸塊210a，使該電子元件22堆疊於該封裝基板21上，且該半導體元件20位於該電子元件22與該封裝基板21之間，並經由回銲該銲錫材211，令該金屬柱220與該導電凸塊210a形成導電元件23。
於本實施例中，該電子元件22藉由該些導電元件23電性連接該封裝基板21，且該金屬柱220係接觸該金屬球210。
如第2D圖所示，於該封裝基板21之第一表面21a(即其上之絕緣保護層213)及該電子元件22之第四表面22b(即其上之絕緣保護層223)之間形成封裝材25，並包覆該些導電元件23與該半導體元件20。
如第2E圖所示，於該封裝基板21之植球墊212之外露表面上結合銲球24。
本發明之製法中，藉由該金屬柱220與多層表皮金屬球210之對接，使回銲時之融接處僅發生於該金屬柱220之底端，以減少融接處，故能避免發生橋接現象，俾提升產品之良率，且能滿足細間距(fine pitch)之需求。
再者，因該金屬柱220與該金屬球210於回銲時之體積及高度之公差小，即尺寸變異容易控制，使接點不易產生缺陷，而有效提升電性連接品質，且該導電元件23所排列成之柵狀陣列(grid array)之共面性(coplanarity)良好，以易於控制產品高度，且該封裝基板21與該電子元件22之間不會呈傾斜接置。
另外，該封裝基板21與該電子元件22之間不僅藉由該導電元件23作支撐，且藉由例如封模方式(molding)使該封裝材25填滿該封裝基板21與該電子元件22之間的空隙，故可避免該封裝基板21與該電子元件22發生翹曲(warpage)。
第3A至3B圖係為本發明之封裝堆疊結構3之製法之第二實施例的剖視示意圖。本實施例與第一實施例之主要差異在於形成封裝材之步驟。
如第3A圖所示，於堆疊製程前，形成封裝材35於該封裝基板21上，以包覆該些導電凸塊210a與該半導體元件20，且該封 裝材35復形成於該封裝基板21與該半導體元件20之間。接著，形成複數開口350於該封裝材35上，以令該些導電凸塊210a對應外露於該些開口350。
於本實施例中，亦可先形成底膠36於該封裝基板21與該半導體元件20之間，再形成該封裝材35，如第3A’圖所示。
再者，該電子元件32係為半導體元件，例如晶片之主動元件、或者例如電阻、電容及電感等之被動元件，故該電子元件32具有相對之作用面32a與非作用面32b，於該作用面32a上具有複數電極墊320，使該些金屬柱220係對應形成於該電極墊320上。
如第3B圖所示，對應結合該金屬柱220與該導電凸塊210a，使該電子元件32堆疊於該封裝基板21上，並經由回銲製程，使該金屬柱220與該導電凸塊210a形成導電元件23。
再者，可不設置該半導體元件20於該封裝基板21上，如第3B’圖所示之封裝堆疊結構3’。
本發明之製法係藉由先形成封裝材25以包覆該些導電凸塊210a，再形成該些開孔350以對應外露各該導電凸塊210a之頂面，因而於之後該金屬柱220結合該導電凸塊210a時，該封裝材35能隔離各該導電元件23，即增加隔離各該導電元件23之效果。
本發明復提供一種封裝堆疊結構2,3,3’，係包括：相堆疊之一封裝基板21以及一電子元件22,32。
所述之封裝基板21係具有複數導電凸塊210a，該導電凸塊210a係具有金屬球210與包覆該金屬球210之銲錫材211。
所述之電子元件22,32係為另一封裝基板或半導體元件，其具有複數金屬柱220，且該些金屬柱220對應結合該些導電凸塊 210a，使該電子元件22,32堆疊於該封裝基板21上，並令該些金屬柱220接觸該些金屬球210，使該金屬柱220與該導電凸塊210a形成導電元件23，以藉由該些導電元件23電性連接該封裝基板21與該電子元件22,32。
於一實施例中，該導電凸塊210a’復具有位於該金屬球210中之絕緣體210’。
於一實施例中，所述之封裝堆疊結構2,3復包括設於該封裝基板21上之半導體元件20，且該半導體元件20位於該電子元件22,32與該封裝基板21之間。又包括形成於該封裝基板21與該半導體元件20之間的底膠36。
於一實施例中，所述之封裝堆疊結構2復包括形成於該電子元件22與該封裝基板21之間的封裝材25，其包覆該些導電元件23。
於一實施例中，所述之封裝堆疊結構3,3’復包括形成於該封裝基板21上且包覆該些導電凸塊210a之封裝材35，其具有複數開口350，以令該些導電凸塊210a對應外露於該些開口350，俾供結合該金屬柱220。
綜上所述，本發明之封裝堆疊結構及其製法，主要係藉由金屬柱與金屬球之對接，以利於堆疊作業，且因尺寸變異容易控制，故容易呈垂直接置，並有利於固定接點，而不會產生橋接現象，俾提升產品之良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保 護範圍，應如後述之申請專利範圍所列。
2‧‧‧封裝堆疊結構
20‧‧‧半導體元件
21‧‧‧封裝基板
210a‧‧‧導電凸塊
210‧‧‧金屬球
211‧‧‧銲錫材
212‧‧‧植球墊
22‧‧‧電子元件
22a‧‧‧第三表面
22b‧‧‧第四表面
220‧‧‧金屬柱
23‧‧‧導電元件
24‧‧‧銲球
25‧‧‧封裝材

Claims (16)

  1. 一種封裝堆疊結構，係包括：封裝基板，係具有複數導電凸塊，各該導電凸塊係由金屬球與包覆該金屬球之銲錫材所構成；以及電子元件，係具有複數金屬柱，且該些金屬柱對應結合該些導電凸塊，使該電子元件堆疊於該封裝基板上，並令該金屬柱與該導電凸塊形成導電元件。
  2. 如申請專利範圍第1項所述之封裝堆疊結構，其中，該導電凸塊復具有位於該金屬球中之絕緣體。
  3. 如申請專利範圍第1項所述之封裝堆疊結構，其中，該電子元件係為另一封裝基板或半導體元件。
  4. 如申請專利範圍第1項所述之封裝堆疊結構，復包括設於該封裝基板上之半導體元件。
  5. 如申請專利範圍第4項所述之封裝堆疊結構，其中，該半導體元件位於該電子元件與該封裝基板之間。
  6. 如申請專利範圍第4項所述之封裝堆疊結構，復包括形成於該封裝基板與該半導體元件之間的底膠。
  7. 如申請專利範圍第1項所述之封裝堆疊結構，復包括形成於該電子元件與該封裝基板之間的封裝材，其包覆該些導電元件。
  8. 如申請專利範圍第1項所述之封裝堆疊結構，復包括形成於該封裝基板上且包覆該些導電凸塊之封裝材，其具有複數開口，以令該些導電凸塊對應外露於該些開口，俾供結合該金屬柱。
  9. 一種封裝堆疊結構之製法，係包括：提供一封裝基板與一具有複數金屬柱之電子元件，該封裝 基板上具有複數導電凸塊，各該導電凸塊係由金屬球與包覆該金屬球之銲錫材所構成；以及對應結合該金屬柱與該導電凸塊，使該電子元件堆疊於該封裝基板上，令該金屬柱與該導電凸塊形成導電元件。
  10. 如申請專利範圍第9項所述之封裝堆疊結構之製法，其中，該導電凸塊復具有位於該金屬球中之絕緣體。
  11. 如申請專利範圍第9項所述之封裝堆疊結構之製法，其中，該電子元件係為另一封裝基板或半導體元件。
  12. 如申請專利範圍第9項所述之封裝堆疊結構之製法，復包括設置半導體元件於該封裝基板上。
  13. 如申請專利範圍第12項所述之封裝堆疊結構之製法，其中，該半導體元件位於該電子元件與該封裝基板之間。
  14. 如申請專利範圍第12項所述之封裝堆疊結構之製法，復包括形成底膠於該封裝基板與該半導體元件之間。
  15. 如申請專利範圍第9項所述之封裝堆疊結構之製法，復包括於對應結合該金屬柱與該導電凸塊之後，形成封裝材於該電子元件與該封裝基板之間，以包覆該些導電元件。
  16. 如申請專利範圍第9項所述之封裝堆疊結構之製法，復包括於對應結合該金屬柱與該導電凸塊之前，形成封裝材於該封裝基板上，以包覆該些導電凸塊，再形成複數開口於該封裝材上，以令該些導電凸塊對應外露於該些開口。
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