TW201543628A - 封裝堆疊結構及其製法暨無核心層式封裝基板及其製法 - Google Patents

封裝堆疊結構及其製法暨無核心層式封裝基板及其製法 Download PDF

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TW201543628A
TW201543628A TW103116497A TW103116497A TW201543628A TW 201543628 A TW201543628 A TW 201543628A TW 103116497 A TW103116497 A TW 103116497A TW 103116497 A TW103116497 A TW 103116497A TW 201543628 A TW201543628 A TW 201543628A
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package
conductive
insulating layer
stack structure
layer
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TWI529883B (zh
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林俊賢
邱士超
白裕呈
沈子傑
孫銘成
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矽品精密工業股份有限公司
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Priority to CN201410219093.7A priority patent/CN105097759A/zh
Priority to US14/464,051 priority patent/US20150325516A1/en
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Abstract

一種無核心層式封裝基板之製法，係先形成一絕緣層於一具有複數外接墊之導電板體上；形成線路層於該絕緣層上，且形成複數導電盲孔於該絕緣層中，以電性連接該線路層與該些外接墊；以及移除部分該導電板體，使該導電板體成為複數導電元件，故可減少核心層的材料及製程，以降低製作成本。本發明復提供該封裝基板及其應用至封裝堆疊結構之製作。

Description

封裝堆疊結構及其製法暨無核心層式封裝基板及其製法
本發明係有關一種封裝堆疊結構，尤指一種得提升產品可靠度之封裝堆疊結構及其製法。
隨著半導體封裝技術的演進，半導體裝置(Semiconductor device)已開發出不同的封裝型態，而為提升電性功能及節省封裝空間，遂堆加複數封裝結構以形成封裝堆疊結構(Package on Package，POP)，此種封裝方式能發揮系統封裝(SiP)異質整合特性，可將不同功用之電子元件，例如：記憶體、中央處理器、繪圖處理器、影像應用處理器等，藉由堆疊設計達到系統的整合，適合應用於輕薄型各種電子產品。
第1A及1B圖係為習知封裝堆疊結構1,1’之不同態樣之剖面示意圖。
如第1A圖所示，該封裝堆疊結構1係包含第一封裝基板11及第二封裝基板12，該第一封裝基板11具有複數 線路層110，且該第二封裝基板12具有核心層120與複數線路層121。第一半導體元件10以覆晶方式設於該第一封裝基板11上，再藉由底膠14充填於該第一半導體元件10與第一封裝基板11之間，且第二半導體元件15以打線方式結合於該第二封裝基板12上，再藉由封裝膠體16包覆該第二半導體元件15，並以複數銲球13疊設且電性連接該第一封裝基板11與該第二封裝基板12。
如第1B圖所示，該封裝堆疊結構1’係包含第一封裝基板11及第二封裝基板12，該第一封裝基板11具有複數線路層110，且該第二封裝基板12具有核心層120與複數線路層121。第一半導體元件10以覆晶方式設於該第一封裝基板11上，再藉由底膠14充填於該第一半導體元件10與第一封裝基板11之間，之後以複數銲球13疊設且電性連接該第一封裝基板11與該第二封裝基板12，再藉由封裝膠體16’包覆該些銲球13與第一半導體元件10，後續將第二半導體元件15’以覆晶方式設於該第二封裝基板12上。
惟，習知封裝堆疊結構1,1’中，其第二封裝基板12皆具有核心層120，導致其製作成本高，且不易符合薄化之需求。
再者，由於第一封裝基板11與第二封裝基板12間係以銲球13作為支撐與電性連接之元件，而隨著電子產品的接點(即I/O)數量愈來愈多，在封裝件的尺寸大小不變的情況下，各該銲球13間的間距需縮小，致使容易發生橋 接(bridge)的現象而發生短路(short)問題，因而造成產品良率過低及可靠度不佳等問題。
又，因該銲球13於回銲後之體積及高度之公差大，即尺寸變異不易控制，致使不僅接點容易產生缺陷(例如，於回銲時，該銲球13會先變成軟塌狀態，同時於承受上方第二封裝基板12的重量後，該銲球13容易塌扁變形，繼而與鄰近之銲球13橋接)，導致電性連接品質不良，且該銲球13所排列成之柵狀陣列(grid array)容易產生共面性(coplanarity)不良，導致接點應力(stress)不平衡而容易造成該第一與第二封裝基板11,12之間呈傾斜接置，甚至產生接點偏移之問題。
因此，如何克服習知技術中之種種問題，實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失，本發明提供一種無核心層式封裝基板，係包括：一絕緣層，係具有相對之第一表面與第二表面；複數外接墊，係嵌埋於該絕緣層中，且外露出該第一表面；複數導電元件，係接觸該些外接墊並立設於該絕緣層之第一表面上，且形成該導電元件之材質係為非銲錫材料；線路層，係設於該絕緣層之第二表面上；以及複數導電盲孔，係形成於該絕緣層中並電性連接該線路層與該些外接墊。
本發明復提供一種封裝堆疊結構，係包括：前述之無核心層式封裝基板；以及至少一板體，係堆疊於該無核心 層式封裝基板之絕緣層之第一表面上，供該板體接置於該些導電元件上。
本發明亦提供一種無核心層式封裝基板之製法，係包括：提供一形成有複數外接墊之導電板體；形成一絕緣層於該導電板體上，該絕緣層係具有相對之第一表面與第二表面，且該絕緣層藉其第一表面結合至該導電板體上；形成線路層於該絕緣層之第二表面上，且形成複數導電盲孔於該絕緣層中，以令各該導電盲孔電性連接該線路層與該些外接墊；以及移除部分該導電板體，使該導電板體成為複數導電元件，且該些導電元件接觸該些外接墊並立設於該絕緣層之第一表面上。
本發明另提供一種封裝堆疊結構之製法，係接續前述之無核心層式封裝基板之製程，再堆疊至少一板體於該無核心層式封裝基板之絕緣層之第一表面上，且該板體接置於該些導電元件上。
前述之封裝堆疊結構及其製法中，該導電板體係為金屬板材，且形成該導電元件之材質係為非銲錫材料，例如金屬柱。
前述之封裝堆疊結構及其製法中，該絕緣層係以壓合方式形成於該導電板體上。
前述之封裝堆疊結構及其製法中，該外接墊之表面係齊平於該絕緣層之第一表面。
前述之封裝堆疊結構及其製法中，該板體係為具有核心層之線路板、或無核心層之線路板。
前述之封裝堆疊結構及其製法中，該板體係藉由複數支撐件接置於該些導電元件上。例如，形成該支撐件之材質係為銅或銲錫材料，且以封裝材包覆該些支撐件與該電子元件。因此，可於堆疊該板體於該無核心層式封裝基板上後，形成封裝材包覆該些支撐件與該電子元件。或先形成封裝材於該板體上，且各該支撐件外露於該封裝材，再將該無核心層式封裝基板以其導電元件接置該些支撐件。
前述之封裝堆疊結構及其製法中，該板體上設有至少一電子元件。
前述之封裝堆疊結構及其製法中，復包括形成封裝材於該無核心層式封裝基板與該板體之間。
另外，前述之封裝堆疊結構及其製法中，復包括設置至少一電子元件於該線路層上。
由上可知，本發明封裝堆疊結構及其製法，係藉由形成無核心層之線路結構於該導電板體上，再將該導電板體製作成導電元件，故相較於習知技術，可減少核心層的材料及製程，以降低製作成本。
再者，本發明藉由該導電元件做為該封裝基板與該板體之堆疊元件，以減少銲錫材之使用量，故於回銲時能減少融接處，以避免發生橋接現象，俾提升產品之良率，且能滿足細間距(fine pitch)之需求，而避免發生短路(short)之問題，進而提高產品良率。
1,1’,3,3’,3”,4‧‧‧封裝堆疊結構
10‧‧‧第一半導體元件
11‧‧‧第一封裝基板
110,121‧‧‧線路層
12‧‧‧第二封裝基板
120,300‧‧‧核心層
13‧‧‧銲球
14‧‧‧底膠
15,15’‧‧‧第二半導體元件
16,16’‧‧‧封裝膠體
2‧‧‧封裝基板
20‧‧‧承載件
200‧‧‧基材
201‧‧‧離型層
202‧‧‧導電板體
202’‧‧‧導電元件
21‧‧‧外接墊
21a‧‧‧表面
22‧‧‧線路
23‧‧‧絕緣層
23a‧‧‧第一表面
23b‧‧‧第二表面
230‧‧‧穿孔
24‧‧‧導電層
25‧‧‧線路層
250‧‧‧導電盲孔
26‧‧‧絕緣保護層
27‧‧‧表面處理層
30,30’‧‧‧板體
31,31’‧‧‧支撐件
310‧‧‧銅柱
311‧‧‧銲錫材料
32,33‧‧‧電子元件
34‧‧‧封裝材
340‧‧‧開口
第1A及1B圖係為習知封裝堆疊結構之不同態樣之剖 視示意圖；第2A至2H圖係為本發明之無核心層式封裝基板之製法之剖視示意圖；以及第3A至3C圖係為本發明封裝堆疊結構之不同實施例之剖視示意圖；其中，第3A圖係為第3A’圖之其它態樣。
以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時，本說明書中所引用之如“上”、“第一”、“第二”及“一”等之用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。
第2A至2H圖係為本發明之無核心層式封裝基板2之製法之剖視示意圖。
如第2A圖所示，提供一承載件20，其具有一基材200、設於該基材200上之一離型層201、與設於該離型層201 上之一導電板體202。
於本實施例中，該導電板體202係為金屬板材，例如銅。
如第2B圖所示，形成複數外接墊21與複數線路22於該導電板體202上。
如第2C圖所示，形成一絕緣層23於該導電板體202上。
於本實施例中，該絕緣層23係具有相對之第一表面23a與第二表面23b，令該第一表面23a結合至該導電板體202上，且該第二表面23b上係接合一如銅材之導電層(seed layer)24。
再者，該絕緣層23之材質係為預浸材(prepreg,PP)，故該絕緣層23係可以壓合方式形成於該導電板體202上。
如第2D圖所示，以雷射鑽孔方式於對應各該外接墊21的位置上形成貫穿該絕緣層23與該導電層24之複數穿孔230。
如第2E圖所示，於該絕緣層23上利用該導電層24電鍍製作一線路層25，且於該些穿孔230中形成導電材料以作為導電盲孔250，並藉由該些導電盲孔250電性連接該線路層25與該些外接墊21。
如第2F圖所示，形成一絕緣保護層26於該絕緣層23與該線路層25上，且該絕緣保護層26係外露出該線路層25，供後續製程中接置其它外部元件。
於本實施例中，形成一表面處理層27於該線路層25 之外露表面上。
如第2G圖所示，藉由該離型層201以移除該基材200。
如第2H圖所示，圖案化蝕刻移除部分該導電板體202，使該導電板體202成為複數導電元件202’，以完成無核心層式封裝基板2之製作，且該些導電元件202’接觸該些外接墊21之表面21a，以令該些導電元件202’立設於該絕緣層23之第一表面23a上。
於本實施例中，該外接墊21之表面21a係齊平於該絕緣層23之第一表面23a，且該線路22係外露於該絕緣層23之第一表面23a。
再者，由於該導電板體202係為非銲錫材料之板材，故該導電元件202’之材質係為非銲錫材料，例如，金屬柱，較佳為銅柱。
又，該導電元件202’之形狀係為鈍面錐柱體，即體積由底端朝頂端漸縮。
如第3A圖所示，於後續製程中，可將該無核心層式封裝基板2以其導電元件202’堆疊於一板體30上，以形成一封裝堆疊結構3。
於本實施例中，該板體30係為具有核心層300之線路板；或者，該板體30’亦可為無核心層(coreless)之線路板，如第3A’圖所示。
再者，該板體30,30’係藉由複數支撐件31接置於該些導電元件202’上，且該支撐件31之材質係為銲錫材料。於其它實施例中，如第3B圖所示，該支撐件31’係由銅柱 310與銲錫材料311構成。
又，可設置至少一電子元件32於該無核心層式封裝基板2之線路層25上，且該板體30上亦可選擇性設置電子元件33。具體地，該電子元件32,33係為主動元件或被動元件，該主動元件係例如：晶片，而該被動元件係例如：電阻、電容及電感。
另外，復可於堆疊製程後，形成封裝材34於該無核心層式封裝基板2與該板體30’之間，如第3A’及3B圖所示，以包覆該些導電元件202’、支撐件31,31’與該電子元件33。於另一方式，如第3C圖所示，亦可先形成封裝材34於該板體30上，且形成複數開口340，使各該支撐件31對應外露於該些開口340，之後再將該無核心層式封裝基板2以其導電元件202’接置於該些開口340中之支撐件31上。
本發明之製法係藉由形成無核心層(coreless)之線路結構於該導電板體202上，再蝕刻該導電板體202以形成導電元件202’，故相較於習知技術，可減少核心層的材料及製程，以降低製作成本。
再者，本發明藉由該導電元件202’做為電性連接，以減少銲錫材之使用量，故於回銲時能減少融接處，以避免發生橋接現象，俾提升產品之良率，且能滿足細間距(fine pitch)之需求，而避免發生短路(short)之問題，進而提高產品良率。
又，因該導電元件202’於回銲時之體積及高度之公差 小，即尺寸變異容易控制，使接點不易產生缺陷，而有效提升電性連接品質，且該導電元件202’所排列成之柵狀陣列(grid array)之共面性(coplanarity)良好，以易於控制產品高度，使該封裝基板2與該板體30之間不會呈傾斜接置。
本發明復提供一種無核心層式封裝基板2，係包括：一絕緣層23、複數外接墊21、複數導電元件202’、一線路層25、以及複數導電盲孔250。
所述之絕緣層23係具有相對之第一表面23a與第二表面23b。
所述之外接墊21係嵌埋於該絕緣層23中，且外露出該第一表面23a，且該外接墊21之表面21a係齊平於該絕緣層23之第一表面23a。
所述之導電元件202’係接觸該些外接墊21以立設於該絕緣層23之第一表面23a上，且該導電元件202’之材質係為非銲錫材料，例如金屬柱。
所述之線路層25係設於該絕緣層23之第二表面23b上。
所述之導電盲孔250係設於該絕緣層23中並電性連接該線路層25與該些外接墊21。
本發明復提供一種封裝堆疊結構3,3’,3”,4，係包括：該無核心層式封裝基板2、以及藉由複數支撐件31,31’接置於該些導電元件202’上之一板體30,30’。
所述之板體30,30’係堆疊於該無核心層式封裝基板2 之絕緣層23之第一表面23a上，且該板體30,30’係為具有核心層300之線路板、或無核心層之線路板。
所述之支撐件31,31’之材質係為銅或銲錫材料。
於一實施例中，該板體30,30’上設有至少一電子元件33。復包括封裝材34，係包覆該些支撐件31,31’與該電子元件33。
於一實施例中，該封裝堆疊結構3,4復包括設於該線路層25上之至少一電子元件32。
綜上所述，本發明封裝堆疊結構及其製法，係藉由形成無核心層式封裝基板，以減少核心層的材料及製程，而降低製作成本。
再者，藉由該導電元件之設計，以減少銲錫材之使用量，故能滿足細間距之需求，且能提高產品良率。
上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。
2‧‧‧封裝基板
202’‧‧‧導電元件
21‧‧‧外接墊
21a‧‧‧表面
22‧‧‧線路
23‧‧‧絕緣層
23a‧‧‧第一表面
23b‧‧‧第二表面
24‧‧‧導電層
25‧‧‧線路層
26‧‧‧絕緣保護層
27‧‧‧表面處理層

Claims (30)

  1. 一種無核心層式封裝基板，係包括：一絕緣層，係具有相對之第一表面與第二表面；複數外接墊，係嵌埋於該絕緣層中，且外露出該第一表面；複數導電元件，係接觸該些外接墊並立設於該絕緣層之第一表面上，且形成該導電元件之材質係為非銲錫材料；線路層，係設於該絕緣層之第二表面上；以及複數導電盲孔，係形成於該絕緣層中並電性連接該線路層與該些外接墊。
  2. 如申請專利範圍第1項所述之封裝基板，其中，該導電元件係為金屬柱。
  3. 如申請專利範圍第1項所述之封裝基板，其中，該外接墊之表面係齊平於該絕緣層之第一表面。
  4. 一種封裝堆疊結構，係包括：一無核心層式封裝基板，係包含：一絕緣層，係具有相對之第一表面與第二表面；複數外接墊，係嵌埋於該絕緣層中，且外露出該第一表面；複數導電元件，係接觸該些外接墊並立設於該絕緣層之第一表面上，且形成該導電元件之材質係為非銲錫材料； 線路層，係設於該絕緣層之第二表面上；及複數導電盲孔，係形成於該絕緣層中並電性連接該線路層與該些外接墊；以及至少一板體，係堆疊於該無核心層式封裝基板之絕緣層之第一表面上，且該板體接置於該些導電元件上。
  5. 如申請專利範圍第4項所述之封裝堆疊結構，其中，該導電元件係為金屬柱。
  6. 如申請專利範圍第4項所述之封裝堆疊結構，其中，該外接墊之表面係齊平於該絕緣層之第一表面。
  7. 如申請專利範圍第4項所述之封裝堆疊結構，其中，該板體係為具有核心層之線路板、或無核心層之線路板。
  8. 如申請專利範圍第4項所述之封裝堆疊結構，其中，該板體係藉由複數支撐件接置於該些導電元件上。
  9. 如申請專利範圍第8項所述之封裝堆疊結構，其中，形成該支撐件之材質係為銅或銲錫材料。
  10. 如申請專利範圍第8項所述之封裝堆疊結構，復包括封裝材，係包覆該些支撐件與該電子元件。
  11. 如申請專利範圍第4項所述之封裝堆疊結構，其中，該板體上設有至少一電子元件。
  12. 如申請專利範圍第4項所述之封裝堆疊結構，復包括封裝材，係形成於該無核心層式封裝基板與該板體之間。
  13. 如申請專利範圍第4項所述之封裝堆疊結構，復包括設於該線路層上之至少一電子元件。
  14. 一種無核心層式封裝基板之製法，係包括：提供一形成有複數外接墊之導電板體；形成一絕緣層於該導電板體上，該絕緣層係具有相對之第一表面與第二表面，且該絕緣層藉其第一表面結合至該導電板體上；形成線路層於該絕緣層之第二表面上，且形成複數導電盲孔於該絕緣層中，以令各該導電盲孔電性連接該線路層與該些外接墊；以及移除部分該導電板體，使該導電板體成為複數導電元件，且該些導電元件接觸該些外接墊並立設於該絕緣層之第一表面上。
  15. 如申請專利範圍第14項所述之封裝基板之製法，其中，該導電板體係為金屬板材。
  16. 如申請專利範圍第14項所述之封裝基板之製法，其中，形成該導電元件之材質係為非銲錫材料。
  17. 如申請專利範圍第14項所述之封裝基板之製法，其中，該絕緣層係以壓合方式形成於該導電板體上。
  18. 一種封裝堆疊結構之製法，係包括：提供一具有複數導電元件之無核心層式封裝基板；以及堆疊至少一板體於該無核心層式封裝基板上，且該板體接置於該些導電元件上。
  19. 如申請專利範圍第18項所述之封裝堆疊結構之製法，其中，形成該導電元件之材質係為非銲錫材料。
  20. 如申請專利範圍第18項所述之封裝堆疊結構之製法，其中，該無核心層式封裝基板之製程係包括：提供一形成有複數外接墊之導電板體；形成一絕緣層於該導電板體上，該絕緣層係具有相對之第一表面與第二表面，供該絕緣層藉其第一表面結合至該導電板體上；形成線路層於該絕緣層之第二表面上，且形成複數導電盲孔於該絕緣層中，以令各該導電盲孔電性連接該線路層與該些外接墊；以及移除部分該導電板體，使該導電板體成為複數導電元件，以完成無核心層式封裝基板之製作，且該些導電元件接觸該些外接墊並立設於該絕緣層之第一表面上。
  21. 如申請專利範圍第20項所述之封裝堆疊結構之製法，其中，該導電板體係為金屬板材。
  22. 如申請專利範圍第20項所述之封裝堆疊結構之製法，其中，該外接墊之表面係齊平於該絕緣層之第一表面。
  23. 如申請專利範圍第20項所述之封裝堆疊結構之製法，復包括設置至少一電子元件於該線路層上。
  24. 如申請專利範圍第18項所述之封裝堆疊結構之製法，其中，該板體係為具有核心層之線路板、或無核心層之線路板。
  25. 如申請專利範圍第18項所述之封裝堆疊結構之製法，其中，該板體係藉由複數支撐件接置於該些導電元件上。
  26. 如申請專利範圍第25項所述之封裝堆疊結構之製法，其中，形成該支撐件之材質係為銅或銲錫材料。
  27. 如申請專利範圍第25項所述之封裝堆疊結構之製法，復包括於堆疊該板體於該無核心層式封裝基板上後，形成封裝材包覆該些支撐件與該電子元件。
  28. 如申請專利範圍第25項所述之封裝堆疊結構之製法，復包括形成封裝材於該板體上，且各該支撐件外露於該封裝材，再將該無核心層式封裝基板以其導電元件接置該些支撐件。
  29. 如申請專利範圍第18項所述之封裝堆疊結構之製法，其中，該板體上設有至少一電子元件。
  30. 如申請專利範圍第18項所述之封裝堆疊結構之製法，復包括形成封裝材於該無核心層式封裝基板與該板體之間。
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