TWI705549B - 電子封裝件 - Google Patents

電子封裝件 Download PDF

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TWI705549B
TWI705549B TW108148637A TW108148637A TWI705549B TW I705549 B TWI705549 B TW I705549B TW 108148637 A TW108148637 A TW 108148637A TW 108148637 A TW108148637 A TW 108148637A TW I705549 B TWI705549 B TW I705549B
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substrate
electronic package
frame
support
package described
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TW202127623A (zh
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林榮政
陳漢宏
周世民
余國華
林長甫
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矽品精密工業股份有限公司
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Priority to US16/859,009 priority patent/US11289794B2/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/36Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • HELECTRICITY
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894Materials of the insulating layers or coatings
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    • H01ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00Details of, or arrangements associated with, antennas
    • H01Q1/12Supports; Mounting means
    • H01Q1/22Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q23/00Antennas with active circuits or circuit elements integrated within them or attached to them
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01QANTENNAS, i.e. RADIO AERIALS
    • H01Q9/00Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
    • H01Q9/04Resonant antennas
    • H01Q9/0407Substantially flat resonant element parallel to ground plane, e.g. patch antenna
    • H01Q9/0414Substantially flat resonant element parallel to ground plane, e.g. patch antenna in a stacked or folded configuration
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    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6661High-frequency adaptations for passive devices
    • H01L2223/6677High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

Abstract

一種電子封裝件,係將天線板堆疊於線路板上,並於該線路板上形成框體,使位於該天線板與線路板之間之支撐體卡固於該框體中,以於封裝製程中,藉由該框體,使該天線板與線路板之間的距離符合需求,確保該天線板之天線功能正常運件。

Description

電子封裝件
本發明係關於一種電子封裝件,特別是關於一種具有天線結構之電子封裝件。
目前無線通訊技術已廣泛應用於各式各樣的消費性電子產品以利接收或發送各種無線訊號,而為滿足消費性電子產品的外觀設計需求,無線通訊模組之製造與設計係朝輕、薄、短、小之需求作開發,其中,平面天線(Patch Antenna)因具有體積小、重量輕與製造容易等特性而廣泛利用在如手機(cell phone)之電子產品之無線通訊模組中。
如第1圖所示,係為習知無線通訊模組1之剖面示意圖。該無線通訊模組1係於一下側設有半導體晶片11之線路板10之上側藉由複數銲錫凸塊18堆疊一具有天線(圖略)之基板12,且該線路板10具有接地片(圖略)及天線回饋線路(antenna feed lines)(圖略),並於該線路板10下方形成複數銲球19,其中,該線路板10與該基板12之間需於特定區域定義為空曠區A(即該些銲錫凸塊18環繞之區域,其內部不可有點膠或模壓填入物),且需控制該線路板10與該基板12之間的距離L,以確保該天線與該半導體晶片11之間的傳接訊號品質。
惟,習知無線通訊模組1中,當該線路板10與該基板12堆疊後,會翻轉整體結構(可將第1圖上下顛倒視之)以回銲該些銲球19,此時該些銲錫凸塊18會呈熔融狀態,導致該線路板10與該基板12之間的距離L改變,因而影響該天線的功能,甚至造成產品之良率下降。
因此,如何克服上述習知技術的問題,實已成目前亟欲解決的課題。
鑑於上述習知技術之缺失,本發明係提供一種電子封裝件,係包括:第一基板,係具有相對之第一表面與第二表面以及線路層;框體,係形成於該第一基板之第一表面上;以及第二基板,係具有天線結構並藉由支撐體堆疊於該第一基板之第一表面上,且該支撐體係對應位於該框體中。
前述之電子封裝件中,該第一基板與第二基板之間所包圍的區域由中心向外依序定義有空曠區及支撐區,該框體位於該支撐區。
前述之電子封裝件中,該框體內係形成有結合材,以固接該支撐體。例如,該結合材係為熱固性膠材。
前述之電子封裝件中,該框體未接觸該第二基板。
前述之電子封裝件中,形成該框體之材質係為絕緣材。
前述之電子封裝件中,該支撐體未電性連接該第一基板。
前述之電子封裝件中,該支撐體與該第一基板之間係間隔有結合材。
前述之電子封裝件中,復包括電子元件,係設於該第一基板上。
前述之電子封裝件中,復包括導電元件,係設於該第一基板之第二表面上。
由上可知,本發明之電子封裝件中,主要藉由該框體框住該支撐體,以穩定堆疊該第一基板與第二基板,使該第一基板與第二基板之間的距離符合需求,故於封裝製程(如進行回銲製程)中,即使該第一基板與第二基板改變相對位置,該框體之高度因維持不變而使該第二基板之位移幅度有限,致使該第一基板與該第二基板之間的距離符合需求。因此,相較於習知技術,本發明之電子封裝件不會因該第一基板與第二基板之間的距離變化而影響該天線結構的功能,因而避免產品良率下降之問題。
1‧‧‧無線通訊模組
10‧‧‧線路板
11‧‧‧半導體晶片
12‧‧‧基板
18‧‧‧銲錫凸塊
19‧‧‧銲球
2‧‧‧電子封裝件
20‧‧‧電子元件
200‧‧‧導電凸塊
21‧‧‧第一基板
21’‧‧‧絕緣保護層
21a‧‧‧第一表面
21b‧‧‧第二表面
210‧‧‧接地片
211‧‧‧線路層
212‧‧‧電性接點
213‧‧‧植球墊
214‧‧‧天線體
22‧‧‧第二基板
222‧‧‧外接墊
224‧‧‧天線結構
25,25’,25”,35‧‧‧框體
251‧‧‧結合材
28‧‧‧支撐體
29‧‧‧導電元件
A‧‧‧空曠區
C‧‧‧支撐區
H,L‧‧‧距離
h‧‧‧高度
t‧‧‧高度差
第1圖係為習知無線通訊模組之剖面示意圖;
第2A至2D圖係為本發明之電子封裝件之製法之剖面示意圖;
第3A圖係為第2C圖之第一基板之上視示意圖;
第3A’及3A”圖係為第3A圖之框體之其它態樣之局部放大上視示意圖;以及
第3B圖係為第3A圖之另一實施例之示意圖。
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“第一”、“第二”、及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。
第2A至2D圖係為本發明之電子封裝件2之製法之剖面示意圖。
如第2A圖所示,提供一具有線路層之第一基板21,其中,該第一基板21係具有相對之第一表面21a與第二表面21b,且於該第一基板21之第一表面21a上形成有至少一或複數個框體25。
於本實施例中,該第一基板21係為線路板,其最外側表面係為絕緣保護層21’,如綠漆。具體地,該第一基板21具有天線體214、接地片210及電性連接該接地片210之線路層211,其中,該天線體214係為線路型天線,其與該線路層211(或該接地片210)係電性隔絕。例 如,該線路層211包含複數電性接點212與複數植球墊213。應可理解地,該第一基板21亦可為其它承載晶片之承載件,並不限於上述。
再者,該框體25係為絕緣體,如綠漆。例如,該框體25與該絕緣保護層21’為相同材質,較佳為一體成形。具體地,該複數框體25係環繞該第一基板21之第一表面21a之邊緣,如第3A圖所示。
又,該框體25係為擋壩結構,以容納凸塊。請參閱第3A、3A’及3A”圖,各該框體25,25’,25”可為環形(如第3A圖所示)、缺口環(如第3A’圖所示)、條狀(如第3A”圖所示),亦或如第3B圖所示,僅在該第一基板21之第一表面21a上形成單一之框體35,且該框體35為溝槽狀。應可理解地,有關該框體之形狀種類繁多,並無特別限制。
另外,該第一基板21之第二表面21b上可設置至少一電子元件20。例如,該電子元件20係為主動元件、被動元件或其二者組合等,其中,該主動元件係例如半導體晶片,且該被動元件係例如電阻、電容及電感。具體地,該電子元件20係藉由複數如銲錫材料之導電凸塊200以覆晶方式電性連接該電性接點212;或者,該電子元件20可藉由複數銲線(圖略)以打線方式電性連接該線路層211;亦或,該電子元件20可直接接觸該電性接點212以電性連接該線路層211。然而,有關該電子元件20電性連接該第一基板21之方式不限於上述。應可理解地,有關該電子元件20之配置方式繁多(如設於該第一基板21之第一表面21a),並不限於上述。
如第2B圖所示,提供一具有天線結構224之第二基板22,且於該框體25中形成結合材251。
於本實施例中,該第二基板22係為天線板,其設有天線結構224及複數外接墊222,且該天線結構224係為線路型天線,其與該外接墊222係電性隔絕。例如,該外接墊222上係設有支撐體28。具體地,該支撐體28係為銲錫材料、金屬柱或其它金屬構造。應可理解地,該第二基板22亦可為其它類型之天線板,並不限於上述。
再者,該結合材251係為熱固性膠材。例如,該結合材251之製程係以點膠針將熱固性膠材填入該框體25中。
如第2C圖所示,將該第二基板22藉由該些支撐體28堆疊於該第一基板21之第一表面21a上,且各該支撐體28係對應位於各該框體25中。亦或如第3B圖所示,該複數該支撐體28係位於單一框體35中。
於本實施例中,該支撐體28係插入該框體25內以嵌埋於該結合材251中。例如,當該支撐體28插入該框體25內後,加熱該結合材251,使該熱固性膠材固化,以固定該支撐體28。具體地,該支撐體28未接觸且未電性連接該第一基板21。應可理解地,該支撐體28亦可依需求碰觸該第一基板21之絕緣保護層21’。
再者,該天線結構224係感應該天線體214,以訊號傳輸於兩者之間。
又,該第一基板21與該第二基板22之間所包圍的區域由中心向外依序可定義有空曠區A及支撐區C,其中,該空曠區A內不可有點膠、模壓填入物或其它物體,以確保該天線結構224之傳接訊號品質,且該支撐區C係用以佈設該些支撐體28(或該框體25)。
如第2D圖所示,於該植球墊213上形成複數如銲球之導電元件29,並回銲該些導電元件29以接置如電路板或另一線路板之電子結構,進而製得電子封裝件2。
本發明之電子封裝件之製法主要藉由該框體25,25’,25”,35之設計,以框住該支撐體28,使該第一基板21與該第二基板22之間的距離H符合需求,約270±45微米(μm)。具體地,於回銲該些支撐體28或導電元件29及後續高溫烘烤製程時,即使因該些熔融狀態之支撐體28或其它因素造成該第一基板21與第二基板22相對位置改變(該距離H與該框體25,25’,25”,35之高度h之間的高度差t),該框體25,25’,25”,35之高度h因維持不變而使該第二基板22之下降幅度有限,即控制該高度差t(約至多90μm之間),以令該第一基板21與該第二基板22之間的距離仍可符合需求。
進一步,若該支撐體28嵌埋於該結合材251中,則於回銲該些導電元件29及後續高溫烘烤製程時,該第二基板22不會重力下降(該結合材251已固定該支撐體28),因而該第一基板21與該第二基板22之間的距離H不會改變。
因此,相較於習知技術,本發明之電子封裝件2不會因該第一基板21與該第二基板22之間的距離H改變而影響該天線結構224與天線體214的功能,因而能有效控制天線品質,進而能提高產品良率。
再者,於該第一基板21之第一表面21a上無需佈設用以結合該支撐體28之金屬墊,故不僅可減少製程以縮短時程及降低成本,且可增加該第一基板21之佈線空間。
又,該第二基板22亦無需形成用以結合該支撐體28之容置空間,故不僅可減少製程以縮短時程及降低成本,且可避免破壞該天線結構224,如應力集中而使該天線結構224破裂。進一步,該框體25,25’,25”,35可避免接觸該第二基板22,以避免熱製程的翹曲(warpage)變化對該第二基板22產生推擠應力而使該天線結構224破裂之問題。
另外,該框體25,25’,25”,35可限制該結合材251之佈設範圍,尤其是溝槽狀框體35之設計,更可避免該結合材251隨時間擴散溢開之問題,故該結合材251之選用種類不受膠材黏度之限制,因而能選用之膠材種類更多。
本發明復提供一種電子封裝件2,其包括:一具有線路層211之第一基板21、一具有天線結構224之第二基板22以及至少一框體25,25’,25”,35。
所述之第一基板21係具有相對之第一表面21a與第二表面21b。
所述之框體25,25’,25”,35係形成於該第一基板21之第一表面21a上。
所述之第二基板22係藉由至少一支撐體28堆疊於該第一基板21之第一表面21a上,且該支撐體28係對應位於該框體25,25’,25”,35中。
於一實施例中,該第一基板21與第二基板22之間所包圍的區域由中心向外依序定義有空曠區A及支撐區C,該框體25位於該支撐區C。
於一實施例中,該框體25,25’,25”,35內係形成有結合材251,以固接該支撐體28。例如,該結合材251係為熱固性膠材。
於一實施例中,該框體25,25’,25”,35未接觸該第二基板22。
於一實施例中,形成該框體25,25’,25”,35之材質係為絕緣材。
於一實施例中,該支撐體28未電性連接該第一基板21。
於一實施例中,該支撐體28與該第一基板21之間係間隔有結合材251。
於一實施例中,所述之電子封裝件2復包括至少一電子元件20,係設於該第一基板21上。
於一實施例中,所述之電子封裝件2復包括複數導電元件29,係設於該第一基板21之第二表面21b上。
綜上所述,本發明之電子封裝件,係藉由該框體之設計,使該第一基板與第二基板之間的距離於高溫製程後仍可符合需求,故本發明之電子封裝件能確保該天線結構的功能正常,因而能確保產品良率符合預期。
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。
2‧‧‧電子封裝件
20‧‧‧電子元件
200‧‧‧導電凸塊
21‧‧‧第一基板
21a‧‧‧第一表面
21b‧‧‧第二表面
211‧‧‧線路層
212‧‧‧電性接點
213‧‧‧植球墊
214‧‧‧天線體
22‧‧‧第二基板
222‧‧‧外接墊
224‧‧‧天線結構
25‧‧‧框體
251‧‧‧結合材
28‧‧‧支撐體
29‧‧‧導電元件
A‧‧‧空曠區
C‧‧‧支撐區

Claims (10)

  1. 一種電子封裝件,係包括:
    第一基板,係具有相對之第一表面與第二表面以及線路層;
    框體,係形成於該第一基板之第一表面上;以及
    第二基板,係具有天線結構並藉由支撐體堆疊於該第一基板之第一表面上,且該支撐體係對應位於該框體中。
  2. 如申請專利範圍第1項所述之電子封裝件,其中,該第一基板與第二基板之間所包圍的區域由中心向外依序定義有空曠區及支撐區,且該框體位於該支撐區。
  3. 如申請專利範圍第1項所述之電子封裝件,其中,該框體內係形成有結合材,以固接該支撐體。
  4. 如申請專利範圍第3項所述之電子封裝件,其中,該結合材係為熱固性膠材。
  5. 如申請專利範圍第1項所述之電子封裝件,其中,該框體未接觸該第二基板。
  6. 如申請專利範圍第1項所述之電子封裝件,其中,形成該框體之材質係為絕緣材。
  7. 如申請專利範圍第1項所述之電子封裝件,其中,該支撐體未電性連接該第一基板。
  8. 如申請專利範圍第1項所述之電子封裝件,其中,該支撐體與該第一基板之間係間隔有結合材。
  9. 如申請專利範圍第1項所述之電子封裝件,復包括設於該第一基板上之電子元件。
  10. 如申請專利範圍第1項所述之電子封裝件,復包括設於該第一基板之第二表面上之導電元件。
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