CN104900596A - 封装堆栈结构及其制法 - Google Patents

封装堆栈结构及其制法 Download PDF

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Publication number
CN104900596A
CN104900596A CN201410089037.6A CN201410089037A CN104900596A CN 104900596 A CN104900596 A CN 104900596A CN 201410089037 A CN201410089037 A CN 201410089037A CN 104900596 A CN104900596 A CN 104900596A
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China
Prior art keywords
packaging
base plate
stack
making
electronic building
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CN201410089037.6A
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CN104900596B (zh
Inventor
徐逐崎
王隆源
江政嘉
施嘉凯
黄淑惠
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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Abstract

一种封装堆栈结构及其制法，该封装堆栈结构包括：具有多个导电凸块的封装基板、以及具有多个金属柱的电子组件，该导电凸块具有金属球与包覆该金属球的焊锡材，且该些金属柱对应结合该些导电凸块，使该电子组件堆栈于该封装基板上，并令该金属柱与该导电凸块形成导电组件，以藉由该金属球与该金属柱的对接，以利于堆栈作业。

Description

封装堆栈结构及其制法
技术领域
本发明涉及一种封装结构，尤指一种封装堆栈结构及其制法。
背景技术
随着近年來可携式电子产品的蓬勃发展，各類相关产品逐渐朝向高密度、高性能以及轻、薄、短、小的趋势而走，各式样封装层叠(package on package，PoP)也因而配合推陈出新，以期能符合轻薄短小与高密度的要求。
如图1所示，其为现有封装堆栈装置1的剖视示意图。如图1所示，该封装堆栈装置1包括两相叠的封装结构1a与另一封装结构1b。
封装结构1a包含具有相对的第一及第二表面11a,11b的第一基板11、覆晶结合该第一基板11的第一电子组件10、设于该第一表面11a上的电性接触垫111、形成于该第一基板11上以包覆该第一电子组件10的第一封装胶体13、形成于该第一封装胶体13的开孔130中的电性接触垫111上的焊锡材114、以及设于该第二表面11b上用于结合焊球14的植球垫112。
另一封装结构1b包含第二基板12、以打线方式结合于该第二基板12上的第二电子组件15a,15b、及形成于该第二基板12上以包覆该第二电子组件15a,15b的第二封装胶体16，令该第二基板12藉由焊锡材114叠设且电性连接于该第一基板11的电性接触垫111上。
然而，现有封装堆栈装置1中，由于该第一与第二基板11,12间是以焊锡材114作为支撑与电性连接的组件，而随着电子产品的接点（即I/O）数量愈来愈多，在封装件的尺寸大小不变的情况下，各该焊锡材114间的间距需缩小，致使容易发生桥接（bridge）的现象，因而造成产品良率过低及可靠度不佳等问题，致使无法用于更精密的细间距产品。
此外，因该焊锡材114于回焊后的体积及高度的公差大，即尺寸变异不易控制，致使不仅接点容易产生缺陷（例如，于回焊时，该焊锡材114会先变成软塌状态，同时于承受上方第二基板12的重量后，该焊锡材114容易塌扁变形，继而与邻近该焊锡材114桥接），导致电性连接品质不良，且该焊锡材114所排列成的栅状数组(grid array)容易产生共面性(coplanarity)不良，导致接点应力(stress)不平衡而容易造成该两封装结构之间呈倾斜接置，甚至产生接点偏移的问题。
另外，该两封装结构之间仅藉由该焊锡材114作支撑，将因该两封装结构之间的空隙d过多，导致该第一与第二基板11,12容易发生翘曲(warpage)。
因此，如何克服现有技术中的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明的主要目的为提供一种封装堆栈结构及其制法，以利于堆栈作业。
该封装堆栈结构包括：封装基板，其具有多个导电凸块，该导电凸块具有金属球与包覆该金属球的焊锡材；以及电子组件，其具有多个金属柱，且该些金属柱对应结合该些导电凸块，使该电子组件堆栈于该封装基板上，并令该金属柱与该导电凸块形成导电组件。
本发明还提供一种封装堆栈结构的制法，其包括：提供一封装基板与一具有多个金属柱的电子组件，该封装基板上具有多个导电凸块，该导电凸块具有金属球与包覆该金属球的焊锡材；以及对应结合该金属柱与该导电凸块，使该电子组件堆栈于该封装基板上，令该金属柱与该导电凸块形成导电组件。
前述的封装堆栈结构及其制法中，该导电凸块还具有位于该金属球中的绝缘体。
前述的封装堆栈结构及其制法中，该电子组件为另一封装基板或半导体组件。
前述的封装堆栈结构及其制法中，形成该导电组件后，该金属柱接触该金属球。
前述的封装堆栈结构及其制法中，还包括设置半导体组件于该封装基板上，且该半导体组件位于该电子组件与该封装基板之间。又包括形成底胶于该封装基板与该半导体组件之间。
前述的封装堆栈结构及其制法中，还包括于对应结合该金属柱与该导电凸块之后，形成封装材于该电子组件与该封装基板之间，以包覆该些导电组件。
另外，前述的封装堆栈结构及其制法中，还包括于对应结合该金属柱与该导电凸块之前，形成封装材于该封装基板上，以包覆该些导电凸块，再形成多个开口于该封装材上，以令该些导电凸块对应外露于该些开口。
由上可知，本发明的封装堆栈结构及其制法，藉由该金属球与该金属柱的对接，以利于堆栈作业，且藉由该金属球与该金属柱的尺寸变异易于控制，使其可克服堆栈结构间倾斜接置及接点偏移的问题。
此外，该电子组件与该封装基板之间不仅藉由该导电组件作支撑，且藉由该封装胶体填满该电子组件与该封装基板之间的空隙，所以可避免该电子组件与该封装基板发生翘曲。
附图说明
图1为现有封装堆栈装置的制法的剖视示意图；
图2A至图2E为本发明的封装堆栈结构的制法的第一实施例的剖视示意图；其中，图2A’为图2A的其它实施例；以及
图3A至图3B为本发明的封装堆栈结构3的制法的第二实施例的剖视示意图；其中，图3A’及图3B’为图3A及图3B的其它实施例。
主要组件符号说明
1            封装堆栈装置
1a、1b       封装结构
2、3、3’    封装堆栈结构
10           第一电子组件
11           第一基板
11a、21a     第一表面
11b、21b     第二表面
12           第二基板
13           第一封装胶体
14、24       焊球
15a、15b     第二电子组件
16           第二封装胶体
20           半导体组件
21           封装基板
22、32       电子组件
22a          第三表面
22b          第四表面
22c          基材
23           导电组件
25、35       封装材
32a          作用面
32b          非作用面
101、36      底胶
111、211b、221b  电性接触垫
112、212     植球垫
114、211     焊锡材
130、213a、223a 开孔
200、320     电极垫
200a         焊锡凸块
210a、210a’ 导电凸块
210          金属球
210’        绝缘体
211a、221a   焊垫
213、223     绝缘保护层
220          金属柱
350          开口
d            空隙。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其它优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“下”、“第一”、“第二”、“第三”、“第四”、及“一”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本发明可实施的范畴。
图2A至图2E为本发明的封装堆栈结构2的制法的第一实施例的剖视示意图。
如图2A所示，提供一封装基板21，其上具有多个导电凸块210a，该导电凸块210a具有金属球210与包覆该金属球210的焊锡材211，该焊锡材211利于后续的堆栈制程。
于本实施例中，该金属球210的材质为铜、锡铅或锡银，且于该金属球210的材质为铜时，该焊锡材211为镍锡，而于金属球210的材质为锡铅或锡银时，该焊锡材211为与该金属球210不同混合比例的锡铅或锡银。
此外，该封装基板21具有相对的第一表面21a及第二表面21b，该第一表面21a上具有多个焊垫211a与多个电性接触垫211b，且该第二表面21b上具有多个植球垫212，并于该封装基板21的第一及第二表面21a,21b上具有例如防焊层的绝缘保护层213，该绝缘保护层213形成有多个开孔213a，以藉由该些开孔213a外露该些焊垫211a、电性接触垫211b及植球垫212。
又，于该电性接触垫211b的外露表面上形成该导电凸块210a，且于该焊垫211a的外露表面上藉由焊锡凸块200a设置一半导体组件20，即该半导体组件20的电极垫200以覆晶方式电性连接该封装基板21。其中，该半导体组件20为主动组件或被动组件，并可使用多个个半导体组件20，且可选自主动组件、被动组件或其组合，该主动组件例如：芯片，而该被动组件例如：电阻、电容及电感。
另外，如图2A’所示，该导电凸块210a’还具有埋于该金属球210中的绝缘体210’，如塑料球。
如图2B所示，提供一具有多个金属柱220的电子组件22，且该金属柱220的材质为铜。
于本实施例中，该电子组件22为封装基板构形。具体地，提供一具有相对的第三表面22a及第四表面22b的基材22c，该第三表面22a上具有多个焊垫221a，且该第四表面22b上具有多个电性接触垫221b，又该基材22c的第三及第四表面22a,22b上具有例如防焊层的绝缘保护层223，且该绝缘保护层223形成有多个开孔223a，以藉该些开孔223a外露该些焊垫221a及电性接触垫221b。
此外，于该基材22c的电性接触垫221b的外露表面上电镀形成例如铜柱的金属柱220。
如图2C所示，对应结合该金属柱220与该导电凸块210a，使该电子组件22堆栈于该封装基板21上，且该半导体组件20位于该电子组件22与该封装基板21之间，并经由回焊该焊锡材211，令该金属柱220与该导电凸块210a形成导电组件23。
于本实施例中，该电子组件22藉由该些导电组件23电性连接该封装基板21，且该金属柱220接触该金属球210。
如图2D所示，于该封装基板21的第一表面21a（即其上的绝缘保护层213）及该电子组件22的第四表面22b（即其上的绝缘保护层223）之间形成封装材25，并包覆该些导电组件23与该半导体组件20。
如图2E所示，于该封装基板21的植球垫212的外露表面上结合焊球24。
本发明的制法中，藉由该金属柱220与多层表皮金属球210的对接，使回焊时的融接处仅发生于该金属柱220的底端，以减少融接处，所以能避免发生桥接现象，以提升产品的良率，且能满足细间距（finepitch）的需求。
此外，因该金属柱220与该金属球210于回焊时的体积及高度的公差小，即尺寸变异容易控制，使接点不易产生缺陷，而有效提升电性连接品质，且该导电组件23所排列成的栅状数组(grid array)的共面性(coplanarity)良好，以易于控制产品高度，且该封装基板21与该电子组件22之间不会呈倾斜接置。
另外，该封装基板21与该电子组件22之间不仅藉由该导电组件23作支撑，且藉由例如封模方式（molding）使该封装材25填满该封装基板21与该电子组件22之间的空隙，所以可避免该封装基板21与该电子组件22发生翘曲(warpage)。
图3A至图3B为本发明的封装堆栈结构3的制法的第二实施例的剖视示意图。本实施例与第一实施例的主要差异在于形成封装材的步骤。
如图3A所示，于堆栈制程前，形成封装材35于该封装基板21上，以包覆该些导电凸块210a与该半导体组件20，且该封装材35还形成于该封装基板21与该半导体组件20之间。接着，形成多个开口350于该封装材35上，以令该些导电凸块210a对应外露于该些开口350。
于本实施例中，也可先形成底胶36于该封装基板21与该半导体组件20之间，再形成该封装材35，如图3A’所示。
此外，该电子组件32为半导体组件，例如芯片的主动组件、或者例如电阻、电容及电感等的被动组件，所以该电子组件32具有相对的作用面32a与非作用面32b，于该作用面32a上具有多个电极垫320，使该些金属柱220对应形成于该电极垫320上。
如图3B所示，对应结合该金属柱220与该导电组件210a，使该电子组件32堆栈于该封装基板21上，并经由回焊制程，使该金属柱220与该导电凸块210a形成导电组件23。
此外，可不设置该半导体组件20于该封装基板21上，如图3B’所示的封装堆栈结构3’。
本发明的制法藉由先形成封装材25以包覆该些导电凸块210a，再形成该些开孔350以对应外露各该导电凸块210a的顶面，因而于之后该金属柱220结合该导电凸块210a时，该封装材35能隔离各该导电组件23，即增加隔离各该导电组件23的效果。
本发明还提供一种封装堆栈结构2,3,3’，包括：相堆栈的一封装基板21以及一电子组件22,32。
所述的封装基板21具有多个导电凸块210a，该导电凸块210a具有金属球210与包覆该金属球210的焊锡材211。
所述的电子组件22,32为另一封装基板或半导体组件，其具有多个金属柱220，且该些金属柱220对应结合该些导电凸块210a，使该电子组件22,32堆栈于该封装基板21上，并令该些金属柱220接触该些金属球210，使该金属柱220与该导电凸块210a形成导电组件23，以藉由该些导电组件23电性连接该封装基板21与该电子组件22,32。
于一实施例中，该导电凸块210a’还具有位于该金属球210中的绝缘体210’。
于一实施例中，所述的封装堆栈结构2,3还包括设于该封装基板21上的半导体组件20，且该半导体组件20位于该电子组件22,32与该封装基板21之间。又包括形成于该封装基板21与该半导体组件20之间的底胶36。
于一实施例中，所述的封装堆栈结构2还包括形成于该电子组件22与该封装基板21之间的封装材25，其包覆该些导电组件23。
于一实施例中，所述的封装堆栈结构3,3’还包括形成于该封装基板21上且包覆该些导电凸块210a的封装材35，其具有多个开口350，以令该些导电凸块210a对应外露于该些开口350，以供结合该金属柱220。
综上所述，本发明的封装堆栈结构及其制法，主要藉由金属柱与金属球的对接，以利于堆栈作业，且因尺寸变异容易控制，所以容易呈垂直接置，并有利于固定接点，而不会产生桥接现象，以提升产品的良率。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (16)

1.一种封装堆栈结构，其包括：
封装基板，其具有多个导电凸块，各该导电凸块由金属球与包覆该金属球的焊锡材所构成；以及
电子组件，其具有多个金属柱，且该些金属柱对应结合该些导电凸块，使该电子组件堆栈于该封装基板上，并令该金属柱与该导电凸块形成导电组件。
2.如权利要求1所述的封装堆栈结构，其特征在于，该导电凸块还具有位于该金属球中的绝缘体。
3.如权利要求1所述的封装堆栈结构，其特征在于，该电子组件为另一封装基板或半导体组件。
4.如权利要求1所述的封装堆栈结构，其特征在于，该结构还包括设于该封装基板上的半导体组件。
5.如权利要求4所述的封装堆栈结构，其特征在于，该半导体组件位于该电子组件与该封装基板之间。
6.如权利要求4所述的封装堆栈结构，其特征在于，该结构还包括形成于该封装基板与该半导体组件之间的底胶。
7.如权利要求1所述的封装堆栈结构，其特征在于，该结构还包括形成于该电子组件与该封装基板之间的封装材，其包覆该些导电组件。
8.如权利要求1所述的封装堆栈结构，其特征在于，该结构还包括形成于该封装基板上且包覆该些导电凸块的封装材，其具有多个开口，以令该些导电凸块对应外露于该些开口，以供结合该金属柱。
9.一种封装堆栈结构的制法，其包括：
提供一封装基板与一具有多个金属柱的电子组件，该封装基板上具有多个导电凸块，各该导电凸块由金属球与包覆该金属球的焊锡材所构成；以及
对应结合该金属柱与该导电凸块，使该电子组件堆栈于该封装基板上，令该金属柱与该导电凸块形成导电组件。
10.如权利要求9所述的封装堆栈结构的制法，其特征在于，该导电凸块还具有位于该金属球中的绝缘体。
11.如权利要求9所述的封装堆栈结构的制法，其特征在于，该电子组件为另一封装基板或半导体组件。
12.如权利要求9所述的封装堆栈结构的制法，其特征在于，该制法还包括设置半导体组件于该封装基板上。
13.如权利要求12所述的封装堆栈结构的制法，其特征在于，该半导体组件位于该电子组件与该封装基板之间。
14.如权利要求12所述的封装堆栈结构的制法，其特征在于，该制法还包括形成底胶于该封装基板与该半导体组件之间。
15.如权利要求9所述的封装堆栈结构的制法，其特征在于，该制法还包括于对应结合该金属柱与该导电凸块之后，形成封装材于该电子组件与该封装基板之间，以包覆该些导电组件。
16.如权利要求9所述的封装堆栈结构的制法，其特征在于，该制法还包括于对应结合该金属柱与该导电凸块之前，形成封装材于该封装基板上，以包覆该些导电凸块，再形成多个开口于该封装材上，以令该些导电凸块对应外露于该些开口。
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