CN103606538A - 半导体叠层封装方法 - Google Patents

半导体叠层封装方法 Download PDF

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CN103606538A
CN103606538A CN201310624819.0A CN201310624819A CN103606538A CN 103606538 A CN103606538 A CN 103606538A CN 201310624819 A CN201310624819 A CN 201310624819A CN 103606538 A CN103606538 A CN 103606538A
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packaging body
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张卫红
张童龙
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Nantong Fujitsu Microelectronics Co Ltd
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Abstract

本发明提供了一种半导体叠层封装方法，包括制作上封装体、制作封装有芯片的下封装体，并将上封装体和所述下封装体互连，所述上封装体和所述下封装体互连包括步骤：在所述下封装体基板上表面形成凸点；在所述凸点上镀锡帽，以形成所述连接柱；将上封装体与所述下封装体通过所述连接柱对接以实现电互连；对所述上封装体与所述下封装体进行回流焊接以形成半导体叠层封装结构。本发明提供的方法一次性完成了上下封装的互连制作，省去了上封装体背部置球的过程；并且用于连接上、下封装层的铜柱的高度可以根据芯片的厚度调节，可以满足小节距封装和高密度电流的要求。

Description

半导体叠层封装方法
技术领域
本发明涉及一种半导体封装方法，尤其涉及一种半导体叠层封装方法。
背景技术
POP（Package on Package叠层装配）技术的出现模糊了一级封装与二级装配之间的界线，在大大提高逻辑运算功能和存储空间的同时，也为终端用户提供了自由选择器件组合的可能，生产成本也得以更有效的控制。
在POP结构中，记忆芯片通常以键合方式连接于基板，而应用处理器芯片以倒装方式连接于基板，记忆芯片封装体是直接叠在应用处理器封装体上，相互往往以锡球焊接连接。这样上下结构以减少两个芯片的互连距离来达到节省空间和获得较好的信号完整性。由于记忆芯片与逻辑芯片的连接趋于更高密度，传统封装的POP结构已经很有局限。
发明内容
在下文中给出关于本发明的简要概述，以便提供关于本发明的某些方面的基本理解。应当理解，这个概述并不是关于本发明的穷举性概述。它并不是意图确定本发明的关键或重要部分，也不是意图限定本发明的范围。其目的仅仅是以简化的形式给出某些概念，以此作为稍后论述的更详细描述的前序。
本发明提供一种半导体叠层封装方法，包括制作上封装体，制作封装有芯片的下封装体，并将上封装体和所述下封装体互连；所述将上封装体和所述下封装体的互连包括步骤:
S101:在所述下封装体基板上表面生成凸点；
S102:在所述凸点上镀锡帽，以形成所述连接柱；
S103:将上封装体与所述下封装体通过所述连接柱对接以实现电互连；
S104:对所述上封装体与所述下封装体进行回流焊接以形成半导体叠层封装结构。
所述芯片封装包括步骤：
S201:提供制作所述下封装体的基板；
S202：将芯片通过倒装方式连接在基板上表面上；
S203:在芯片底部填充胶以将所述芯片固定于所述基板上；
S204:在所述基板下表面形成焊球。
本发明提供的一种半导体叠层封装方法，通过在下封装体上形成铜柱并镀锡帽的方法实现上、下封装体的互连，一次性完成了上下封装的互连制作，省去了上封装体背部置球的过程；并且用于连接上、下封装层的铜柱的高度可以根据芯片的厚度调节，可以满足小节距封装和高密度电流的要求。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明将上封装体和所述下封装体互连的方法流程图；
图2为本发明芯片封装的步骤；
图3-图5为本发明下封装体上表面生成铜柱及锡帽的示意图；
图6-图8为本发明芯片封装过程示意图；
图9为本发明叠层封装结构示意图。
附图标记：
1-凸点；  2-锡帽；  3-底充胶；
4-上封装体；  5-下封装体；  6-芯片。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。在本发明的一个附图或一种实施方式中描述的元素和特征可以与一个或更多个其它附图或实施方式中示出的元素和特征相结合。应当注意，为了清楚的目的，附图和说明中省略了与本发明无关的、本领域普通技术人员已知的部件和处理的表示和描述。基于本发明中的实施例，本领域普通技术人员在没有付出创造性劳动的前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明提供了一种半导体叠层封装方法，包括制作上封装体，制作下封装体，芯片封装，上、下封装体的互连和上、下封装体对接回流，如图1所述为上、下封装体的互连步骤，包括：S101:在所述下封装体基板上表面生成凸点；S102:在所述凸点上镀锡帽，以形成所述连接柱；S103:将上封装体与所述下封装体通过所述连接柱对接以实现电互连；S104:对所述上封装体与所述下封装体进行回流焊接以形成半导体叠层封装结构。
上述步骤提供了一种连接上下封装体的方法，如图3-图5所示，在所述下封装体基板上表面生成凸点1，在所述凸点1上镀锡帽2，所述锡帽的大小与凸点的大小一样，保证锡帽的大小合适，既能实现上下封装体之间的电连接，又能保证电流的密度以获得较好的信号；镀上的锡帽上表面为方形，在回流焊接的过程中，铜柱上的锡帽上表面的形状会由方形变为圆形。
可选的，所述凸点材料为金属，如铜等。例如，凸点可为铜柱，铜柱的高度根据下封装体上封装的芯片厚度而定，这样能够保证上下封装体之间有最合适的距离，进行最小节距的叠层封装。
在步骤S103将上封装体与下封装体通过凸点互连焊接之前要对芯片进行封装，所述芯片封装在所述下封装体的上表面，包括步骤：S201:提供制作所述下封装体的基板；S202：将芯片通过倒装方式连接在基板上表面上；S203:在芯片底部填充胶以将所述芯片固定于所述基板上；S204:在所述基板下表面形成焊球。
如图6-8所示，所述芯片6通过倒装方式连接在基板的上表面，与下封装体形成电互通；再通过底部填充胶的方式将所述芯片6固定在基板上。下封装体只通过底部填充胶固定芯片，没有通过塑封包住芯片；所述下封装体上表面封装的芯片可以为多个，排列在所述下封装体上表面。最后在所述下封装体5的下表面置球。
上述填充在芯片底部的胶为一种化学胶，主要成分可为环氧树脂，将芯片与下封装体上表面之间的空隙填满胶，对填充的胶进行加热固化，即可达到加固的目的，又保证了焊接工艺的电气安全特性。
将芯片以倒封装方式连接在下封装体上表面后，将上封装体5与下封装体6对接，通过如铜柱等凸点互连进行回流焊接，以形成叠层封装结构，如图7所示。
封装完成的结构如图9所示，包括叠层设置的上封装体和封装有芯片的下封装体，所述上封装体和所述下封装体通过连接柱实现电互连。本方案所述的封装方法叠层封装了上下两个封装体，通过在下封装基板上形成铜柱以及锡帽，一次性完成了封装的互连，相对于现有技术，省略了上封装层基板下表面的置球，节省了步骤，下封装体基板上的铜柱高度可以根据应用处理芯片的厚度调节，通过对接和回流焊接处理后，上下封装体结合到一起形成稳定的小节距的叠层封装结构。
通过铜柱互连，除去了上封装体基板下表面的锡球，满足了小节距封装和高密度电流的要求。
本实施例的上封装层基板没有锡球或者铜柱，但是本方法仍然适用上封装层下表面有锡球或者铜柱的情况。同时，本方案提出的叠层封装为上下两个封装体的连接，所述上封装体上表面还可以设有一个或者多个封装体，封装体的个数根据实际应用的需要决定。
最后应说明的是：虽然以上已经详细说明了本发明及其优点，但是应当理解在不超出由所附的权利要求所限定的本发明的精神和范围的情况下可以进行各种改变、替代和变换。而且，本发明的范围不仅限于说明书所描述的过程、设备、手段、方法和步骤的具体实施例。本领域内的普通技术人员从本发明的公开内容将容易理解，根据本发明可以使用执行与在此所述的相应实施例基本相同的功能或者获得与其基本相同的结果的、现有和将来要被开发的过程、设备、手段、方法或者步骤。因此，所附的权利要求旨在在它们的范围内包括这样的过程、设备、手段、方法或者步骤。

Claims (8)

1.一种半导体叠层封装方法，其特征在于，包括：制作上封装体，制作封装有芯片的下封装体，并将上封装体和所述下封装体互连；所述将上封装体和所述下封装体互连包括步骤:
S101:在所述下封装体基板上表面形成凸点；
S102:在所述凸点上镀锡帽，以形成所述连接柱；
S103:将上封装体与所述下封装体通过所述连接柱对接以实现电互连；
S104：对所述上封装体与所述下封装体进行回流焊接以形成半导体叠层封装结构。
2.根据权利要求1所述的一种半导体叠层封装方法，其特征在于，所述制作封装有芯片的下封装体包括：
S201:提供制作所述下封装体的基板；
S202：将芯片通过倒装方式连接在基板上表面上；
S203:在芯片底部填充胶以将所述芯片固定于所述基板上；
S204:在所述基板下表面形成焊球。
3.根据权利要求1所述的一种半导体叠层封装方法，其特征在于，所述凸点高度与芯片的厚度相当。
4.根据权利要求1所述的一种半导体叠层封装方法，其特征在于，所述凸点为铜柱。
5.根据权利要求1所述的一种半导体叠层封装方法，其特征在于，所述锡帽的大小与所述凸点的大小匹配。
6.根据权利要求1所述的一种半导体叠层封装方法，其特征在于，还包括：在所述上封装体上表面形成一个或者多个封装体。
7.根据权利要求1-6任一所述的半导体叠层封装方法，其特征在于，还包括：在所述上封装体的下表面形成焊球。
8.根据权利要求1-6任一所述的半导体叠层封装方法，其特征在于，还包括：在所述上封装体的下表面形成所述连接柱。
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