CN104201120A - 半导体倒装封装方法 - Google Patents

半导体倒装封装方法 Download PDF

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CN104201120A
CN104201120A CN201410433222.2A CN201410433222A CN104201120A CN 104201120 A CN104201120 A CN 104201120A CN 201410433222 A CN201410433222 A CN 201410433222A CN 104201120 A CN104201120 A CN 104201120A
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chip
substrate
solder bump
conductive pole
semiconductor flip
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CN104201120B (zh
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林仲珉
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Nantong Fujitsu Microelectronics Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提供一种半导体倒装封装方法,半导体倒装封装方法步骤如下:在基板的功能面触点处排布导电柱;在基板上倒装芯片,使芯片的焊料凸点支撑在导电柱的顶部;对焊料凸点进行回流焊,使焊料凸点融化并至少包覆导电柱的顶部。本发明提供的上述方案,通过在基板上设置导电柱,使得在回流焊接的过程中,焊料凸点融化并沿着导电柱流动,并至少包覆导电柱的顶部,导电柱对芯片具有一定的支撑作用,防止焊料凸点回流后易塌陷溢出形成短路的问题,同时,有效地提高了倒装封装结构的稳定性。

Description

半导体倒装封装方法
技术领域
本发明涉及半导体封装技术领域,尤其涉及一种半导体倒装封装方法。
背景技术
倒装芯片工艺既是一种芯片互连技术,又是一种理想的芯片粘接技术。早在50余年前IBM(国际商业机器公司)公司已研发使用了这项技术。但直到近几年来,倒装芯片已成为高端器件及高密度封装领域中经常采用的封装形式。今天,倒装芯片封装技术的应用范围日益广泛,封装形式更趋多样化,对倒装芯片封装技术的要求也随之提高。同时,倒装芯片工艺也向制造者提出了一系列新的严峻挑战,为这项复杂的技术提供封装,组装及测试的可靠支持。
以往的一级封装技术都是将芯片的有源区面朝上,背对基板和贴后键合,如引线键合和载带自动键合。倒装芯片则将芯片有源区面对基板,通过芯片上呈阵列排列的焊料凸点实现芯片与衬底的互连。硅片直接以倒扣方式安装到印制电路板,从硅片向四周引出输入输出端,互联的长度大大缩短,减小了相移电路的延迟,有效地提高了电性能。显然,这种芯片互连方式能提供更高的输入输出端的密度。倒装占有面积几乎与芯片大小一致。在所有表面安装技术中,倒装芯片可以达到最小、最薄的封装。
但是存在以下问题:在焊料凸点进行回流时,形成焊料凸点的锡球易塌陷溢出形成短路,从而降低了倒装封装的整体稳定性。
发明内容
本发明的目的在于提供一种半导体倒装封装方法。
本发明提供的一种半导体倒装封装方法,包括以下步骤:
在基板的功能面触点处排布导电柱;
在基板上倒装芯片,使芯片的焊料凸点支撑在导电柱的顶部;
对焊料凸点进行回流焊,使焊料凸点融化并至少包覆导电柱的顶部。
本发明提供的上述方案,通过在基板上设置导电柱,使得在回流焊接的过程中,焊料凸点融化并沿着导电柱流动,并至少包覆导电柱的顶部,导电柱对芯片具有一定的支撑作用,防止焊料凸点回流后易塌陷溢出形成短路的问题,同时,有效地提高了倒装封装结构的稳定性。
附图说明
图1为本发明实施例提供的半导体倒装封装方法的流程图;
图2为本发明实施例提供的基板上设置导电柱的结构示意图;
图3为将芯片倒装在基板上的结构示意图;
图4为芯片回流焊接在基板上的结构示意图图;
图5为本发明实施提供的半导体倒装封装结构示意图;
图6为本发明另一实施例提供的半导体倒装封装结构示意图。
具体实施方式
下面参照附图来说明本发明的实施例。在本发明的一个附图或一种实施方式中描述的元素和特征可以与一个或更多个其它附图或实施方式中示出的元素和特征相结合。应当注意,为了清楚的目的,附图和说明中省略了与本发明无关的、本领域普通技术人员已知的部件和处理的表示和描述。
如图1所示,本发明提供实施例提供的半导体倒装封装方法,包括以下步骤:
S1:在基板4的功能面触点处排布导电柱3。
S2:在基板4上倒装芯片1,使芯片1的焊料凸点2支撑在导电柱3的顶部。
S3:对焊料凸点2进行回流焊,使焊料凸点2融化并至少包覆导电柱3的顶部。
本发明提供的上述方案,通过在基板4上设置导电柱3,使得在回流焊接的过程中,焊料凸点2融化并沿着导电柱3流动,并至少包覆导电柱3的顶部,导电柱3对芯片1具有一定的支撑作用,防止焊料凸点2回流后易塌陷溢出形成短路的问题,同时,有效地提高了倒装封装结构的稳定性。
优选地,如图2所示,导电柱3垂直固定于基板4功能面的触点上。
在本发明实施例中,导电柱3采用垂直固定的方式,固定在基板4功能面的触点上,这种方式不仅便于导电柱3的电镀操作,且提高了导电柱3的支撑连接效果。
优选地,通过电镀的方式在基板4的功能面上形成导电柱3。
在本发明实施例中,导电柱3是通过电镀的方式在基板4的触点处形成的,其可以使导电柱3具有良好的耐腐性和导电性能。
优选地,如图2所示,导电柱3背离所述基板4的一端为半球形。
在本发明实施例中,在背离基板4的导电柱3一端上为半球形,以利于焊料凸点2融化后沿着导电柱3向下流动,来增加固定效果。
优选地,在每一触点位置处设置有四个导电柱3,每一焊料凸点2包覆同一触点位置处设置的四个导电柱3。
在本发明实施例中,如图3所示,每一触点处阵列设置四个导电柱3,芯片1的焊料凸点22位于四个导电柱3的顶部,且被四个导电柱3共同支撑,通过四个导电柱3来对焊料凸点22进行支撑,一方面在放置的时候利于定位,防止在回流焊接的时候芯片1位置出现偏移,另一方面也有利于提高焊接的质量,增强焊点处的强度。如图4所示,每一焊料凸点2包覆同一触点位置处设置的四个导电柱3,实现焊料凸点2与导电柱3之间的紧固连接。
应注意的是,在每一个触点处可以设置多个导电柱3,也可以设置一个导电柱3,如图6所示,本发明实施例中,每个基板4的触点上只设置一个导电柱3。
还应注意的是,在进行回流焊接后,每个焊料凸点2包覆导电柱3的形式也有多种,如上述实施例中的整体包覆4个导电柱3,还可以至少只包覆导电柱3的一端,如图6所示,本发明实施例中,在进行回流焊接后,每个焊料凸点2只包覆导电柱3背离基板4的顶部。
优选地,每一触点处设置的四个导电柱3阵列排布在基板4的功能面上。
在本发明实施例中,导电柱3采用阵列方式排布在基板4的触点上,可进一步加强导电柱3对焊料凸点2的支撑固定作用,达到芯片1与基板4的紧固连接。
优选地,如图5和图6所示,上述步骤之后,各个实施例中制造半导体倒装封装方法步骤还包括:在基板4上设有用来包覆芯片1的的塑封体5。
最后应说明的是:以上实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (7)

1.一种半导体倒装封装方法,其特征在于,包括以下步骤:
在基板的功能面触点处排布导电柱;
在基板上倒装芯片,使芯片的焊料凸点支撑在导电柱的顶部;
对所述焊料凸点进行回流焊,使所述焊料凸点融化并至少包覆所述导电柱的顶部。
2.如权利要求1所述的半导体倒装封装方法,其特征在于,所述导电柱垂直固定于所述基板功能面的触点上。
3.如权利要求2所述的半导体倒装封装方法,其特征在于,通过电镀的方式在所述基板的功能面上形成所述导电柱。
4.如权利要求2所述的半导体倒装封装方法,其特征在于,所述导电柱背离所述基板的一端为半球形。
5.如权利要求1所述的半导体倒装封装方法,其特征在于,在每一所述触点位置处设置有四个导电柱,每一所述焊料凸点包覆同一所述触点位置处设置的四个所述导电柱。
6.如权利要求5所述的半导体倒装封装方法,其特征在于,每一所述触点处设置的四个所述导电柱阵列排布在所述基板的功能面上。
7.如权利要求1-6任一项所述的半导体倒装封装方法,其特征在于,在所述基板上设有用来封装的塑封体,所述塑封体包覆所述芯片。
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CN107331628A (zh) * 2017-08-07 2017-11-07 山东晶导微电子有限公司 一种电子元器件焊接装置和工艺
CN109545693A (zh) * 2018-09-26 2019-03-29 广西桂芯半导体科技有限公司 一种半导体倒装结构及其制备方法
CN112652604A (zh) * 2019-10-10 2021-04-13 中芯长电半导体(江阴)有限公司 天线的封装结构及封装方法
WO2021072731A1 (zh) * 2019-10-18 2021-04-22 深圳市大疆创新科技有限公司 半导体芯片封装结构、封装方法及电子设备
CN113675155A (zh) * 2020-05-14 2021-11-19 南茂科技股份有限公司 晶圆级芯片尺寸封装结构及其制造方法

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CN102325431A (zh) * 2011-09-09 2012-01-18 深南电路有限公司 在电路板上制作铜柱的方法和具有表面铜柱的电路板
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107331628A (zh) * 2017-08-07 2017-11-07 山东晶导微电子有限公司 一种电子元器件焊接装置和工艺
CN109545693A (zh) * 2018-09-26 2019-03-29 广西桂芯半导体科技有限公司 一种半导体倒装结构及其制备方法
CN112652604A (zh) * 2019-10-10 2021-04-13 中芯长电半导体(江阴)有限公司 天线的封装结构及封装方法
WO2021072731A1 (zh) * 2019-10-18 2021-04-22 深圳市大疆创新科技有限公司 半导体芯片封装结构、封装方法及电子设备
CN113675155A (zh) * 2020-05-14 2021-11-19 南茂科技股份有限公司 晶圆级芯片尺寸封装结构及其制造方法

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