JP5058714B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP5058714B2 JP5058714B2 JP2007215189A JP2007215189A JP5058714B2 JP 5058714 B2 JP5058714 B2 JP 5058714B2 JP 2007215189 A JP2007215189 A JP 2007215189A JP 2007215189 A JP2007215189 A JP 2007215189A JP 5058714 B2 JP5058714 B2 JP 5058714B2
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- Prior art keywords
- solder
- metal
- bumps
- bump
- solder bump
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- H05K2201/094—Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09472—Recessed pad for surface mounting; Recessed electrode of component
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10227—Other objects, e.g. metallic pieces
- H05K2201/1025—Metallic discs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
20 金属バンプ
22 フラックス
30 中継基板
32 半導体チップ
34 接着剤
36 基板電極
37 チップ電極
38 ワイヤ
40 封止樹脂
42 ソルダーレジスト
44 外部電極
50 バンプ電極
52 アンダーフィル材
60 実装部
100 半導体装置
Claims (13)
- 半導体チップと、
前記半導体チップを外部と電気的に接続する複数の半田バンプと、
前記複数の半田バンプのうち少なくとも一部である第1半田バンプの表面に設けられ、 前記第1半田バンプより融点の高い金属からなる金属バンプと、
を具備し、
前記第1半田バンプのうち少なくとも一部は、表面に前記金属バンプが複数積層して設けられていることを特徴とする半導体装置。 - 半導体チップと、
前記半導体チップを外部と電気的に接続する複数の半田バンプと、
前記複数の半田バンプのうち少なくとも一部である第1半田バンプの表面に設けられ、 前記第1半田バンプより融点の高い金属からなる金属バンプと、
を具備し、
前記第1半田バンプの一部である第3半田バンプは、表面に1以上の前記金属バンプが積層して設けられ、前記第1半田バンプの他の一部である第4半田バンプは、前記第3半田バンプの表面に設けられた前記金属バンプの数と異なる数の前記金属バンプが、表面に積層して設けられていることを特徴とする半導体装置。 - 半導体チップと、
前記半導体チップを外部と電気的に接続する複数の半田バンプと、
前記複数の半田バンプのうち少なくとも一部である第1半田バンプの表面に設けられ、 前記第1半田バンプより融点の高い金属からなる金属バンプと、
を具備し、
前記金属バンプは、スタッドバンプからなることを特徴とする半導体装置。 - 前記第1半田バンプのうち少なくとも一部は、表面に前記金属バンプが複数設けられていることを特徴とする請求項3に記載の半導体装置。
- 前記複数の半田バンプは、表面に前記金属バンプが設けられていない第2半田バンプを含むことを特徴とする請求項1から4のいずれか1項に記載の半導体装置。
- 前記金属バンプは、金からなることを特徴とする請求項1から5のいずれか1項に記載の半導体装置。
- 半導体チップを外部の電極と電気的に接続する複数の半田バンプの少なくとも一部である第1半田バンプの表面に、前記第1半田バンプより融点の高い金属からなる金属バンプを形成する工程と、
前記半導体チップを実装する実装部に、前記第1半田バンプを接合する工程と、
を具備し、
前記第1半田バンプの表面に前記金属バンプを形成する工程は、前記第1半田バンプのうち少なくとも一部の表面に、複数の前記金属バンプを積層して形成する工程を含むことを特徴とする半導体装置の製造方法。
- 半導体チップを外部の電極と電気的に接続する複数の半田バンプの少なくとも一部である第1半田バンプの表面に、前記第1半田バンプより融点の高い金属からなる金属バンプを形成する工程と、
前記半導体チップを実装する実装部に、前記第1半田バンプを接合する工程と、
を具備し、
前記第1半田バンプの表面に前記金属バンプを形成する工程は、前記第1半田バンプの一部である第3半田バンプの表面に、1以上の前記金属バンプを積層して形成し、前記第1半田バンプの他の一部である第4半田バンプの表面に、前記第3半田バンプの表面に形成した前記金属バンプの数と異なる数の前記金属バンプを積層して形成する工程を含むことを特徴とする半導体装置の製造方法。 - 前記第3半田バンプ及び前記第4半田バンプの表面に前記金属バンプを形成する工程は、前記実装部における前記半田バンプが実装される面の凹凸に対応した個数の金属バンプを、前記第3半田バンプ及び前記第4半田バンプの表面に形成する工程を含むことを特徴とする請求項8に記載の半導体装置の製造方法。
- 半導体チップを外部の電極と電気的に接続する複数の半田バンプの少なくとも一部である第1半田バンプの表面に、前記第1半田バンプより融点の高い金属からなる金属バンプを形成する工程と、
前記半導体チップを実装する実装部に、前記第1半田バンプを接合する工程と、
を具備し、
前記第1半田バンプの表面に前記金属バンプを形成する工程は、前記第1半田バンプの表面に高さの異なる前記金属バンプを形成する工程を含むことを特徴とする請求項8に記載の半導体装置の製造方法。 - 前記第1半田バンプの表面に高さの異なる前記金属バンプを形成する工程は、前記実装部における前記半田バンプが実装される面の凹凸に対応した高さの金属バンプを、前記第1半田バンプの表面に形成する工程を含むことを特徴とする請求項10に記載の半導体装置の製造方法。
- 半導体チップを外部の電極と電気的に接続する半田バンプの表面に、前記半田バンプより融点の高い金属を含むフラックスを塗布する工程と、
前記半導体チップを実装する実装部に、前記フラックスが塗布された前記半田バンプを接合する工程と、
を具備することを特徴とする半導体装置の製造方法。 - 前記実装部は、半導体チップが実装された中継基板であることを特徴とする請求項7から12のうちいずれか1項に記載の半導体装置の製造方法。
Priority Applications (2)
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JP2007215189A JP5058714B2 (ja) | 2007-08-21 | 2007-08-21 | 半導体装置及びその製造方法 |
US12/196,210 US7846829B2 (en) | 2007-08-21 | 2008-08-21 | Stacked solder balls for integrated circuit device packaging and assembly |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007215189A JP5058714B2 (ja) | 2007-08-21 | 2007-08-21 | 半導体装置及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
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JP2009049248A JP2009049248A (ja) | 2009-03-05 |
JP5058714B2 true JP5058714B2 (ja) | 2012-10-24 |
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EP2337068A1 (en) * | 2009-12-18 | 2011-06-22 | Nxp B.V. | Pre-soldered leadless package |
US9515036B2 (en) | 2012-04-20 | 2016-12-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for solder connections |
US9768137B2 (en) * | 2012-04-30 | 2017-09-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stud bump structure for semiconductor package assemblies |
US8828860B2 (en) | 2012-08-30 | 2014-09-09 | International Business Machines Corporation | Double solder bumps on substrates for low temperature flip chip bonding |
US9966341B1 (en) | 2016-10-31 | 2018-05-08 | Infineon Technologies Americas Corp. | Input/output pins for chip-embedded substrate |
KR20220048532A (ko) | 2020-10-12 | 2022-04-20 | 삼성전자주식회사 | 반도체 패키지 및 그 제조방법 |
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JPH07142488A (ja) * | 1993-11-15 | 1995-06-02 | Nec Corp | バンプ構造及びその製造方法並びにフリップチップ実装 構造 |
JPH09275106A (ja) * | 1996-04-04 | 1997-10-21 | Nec Corp | バンプの構造と形成方法 |
JPH1126931A (ja) * | 1997-07-03 | 1999-01-29 | Fuji Xerox Co Ltd | 電子部品実装基板およびその接続検査方法 |
JPH11312749A (ja) * | 1998-02-25 | 1999-11-09 | Fujitsu Ltd | 半導体装置及びその製造方法及びリードフレームの製造方法 |
US6940178B2 (en) * | 2001-02-27 | 2005-09-06 | Chippac, Inc. | Self-coplanarity bumping shape for flip chip |
JP3615206B2 (ja) * | 2001-11-15 | 2005-02-02 | 富士通株式会社 | 半導体装置の製造方法 |
JP2004253544A (ja) * | 2003-02-19 | 2004-09-09 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US20050003652A1 (en) * | 2003-07-02 | 2005-01-06 | Shriram Ramanathan | Method and apparatus for low temperature copper to copper bonding |
JP4427298B2 (ja) * | 2003-10-28 | 2010-03-03 | 富士通株式会社 | 多段バンプの形成方法 |
US7223695B2 (en) * | 2004-09-30 | 2007-05-29 | Intel Corporation | Methods to deposit metal alloy barrier layers |
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Also Published As
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JP2009049248A (ja) | 2009-03-05 |
US20090212423A1 (en) | 2009-08-27 |
US7846829B2 (en) | 2010-12-07 |
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