JP2009043793A - 半導体装置、およびその半導体装置の製造方法 - Google Patents

半導体装置、およびその半導体装置の製造方法 Download PDF

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JP2009043793A
JP2009043793A JP2007204825A JP2007204825A JP2009043793A JP 2009043793 A JP2009043793 A JP 2009043793A JP 2007204825 A JP2007204825 A JP 2007204825A JP 2007204825 A JP2007204825 A JP 2007204825A JP 2009043793 A JP2009043793 A JP 2009043793A
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Prior art keywords
electrode
metal
substrate
wire
bonding
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JP2007204825A
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Manabu Tanabe
学 田辺
Hiroaki Fujimoto
博昭 藤本
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Panasonic Corp
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Panasonic Corp
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Priority to JP2007204825A priority Critical patent/JP2009043793A/ja
Priority to US12/185,921 priority patent/US20090039509A1/en
Priority to CNA2008101312950A priority patent/CN101364578A/zh
Publication of JP2009043793A publication Critical patent/JP2009043793A/ja
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Abstract

【課題】ボンディングワイヤ同士の接触を防止することができる半導体装置を提供する。
【解決手段】半導体チップ５の一主面上に形成された複数の素子電極６、７上に、ボンディングワイヤ１２、１３よりも硬度の小さい突起電極８、９を形成する。例えば、突起電極８、９を、Ａｕワイヤにより形成し、半導体チップ５が搭載されたＢＧＡ基板１の基板電極２、３と突起電極８、９とに接合するボンディングワイヤ１２、１３を、Ｃｕ、Ａｌなどの突起電極８、９の硬度より大きい材質にする。
【選択図】図１

Description

本発明は、半導体装置、およびその半導体装置の製造方法に関する。
近年、移動体通信機器等の電子機器の小型化、高機能・多機能化が進展しており、それに対応するべく半導体装置は小型化、高密度化、多ピン化の傾向にある。たとえば、外部端子が底面にエリアアレー状に配置されたパッケージ型の半導体装置が多く用いられるようになってきている。また、パッケージされる半導体チップの素子電極は、チップ外周部（周縁部）に沿って、千鳥配置などのように複数列に配置されるようになってきており、半導体チップの素子電極とパッケージの基板電極とを電気的に接続するボンディングワイヤが長くなってきている。
かかるパッケージ型の半導体装置の一例としてのＢＧＡ（ＢＡｌｌ Ｇｒｉｄ Ａｒｒａｙ）パッケージを図５に示す。図５に示すように、このＢＧＡパッケージでは、ＢＧＡ基板４０（以下、単に基板４０と称す。）に半導体チップ４３が固着され、半導体チップ４３の素子電極４４と基板４０に形成された基板電極４１、４２とがボンディングワイヤ４５、４７により電気的に接続されている。また、半導体チップ４３の素子電極４４には、ボンディングワイヤ４５、４７の先端に形成したボール部４６、４８による接合部が配置されている。
このようなＢＧＡパッケージにおいては、半導体チップ４３のチップ外周部の素子電極４４に接続するボンディングワイヤ４５のループ高さをできるだけ低くして、チップ外周部の素子電極４４よりも内側に配置された素子電極４４に接続するボンディングワイヤ４７との間の距離を保っている（例えば、特許文献１参照。）。
以上のように、従来、半導体装置では、ボンディングワイヤを３次元的に配置して、隣接するボンディングワイヤ同士が接触しないようにしているが、ボンディングワイヤにＡｕを用いているため、そのループ形状を維持することが難しく、ボンディングワイヤ同士が接触することがあり、歩止まり低下の原因となっている。
特開平８−３４００１８号公報
本発明は、上記問題に鑑み、ボンディングワイヤ同士の接触を防止し、歩留まりの向上を図ることができる半導体装置、およびその半導体装置の製造方法を提供することを目的とする。
本発明の請求項１記載の半導体装置は、複数の基板電極を有する支持基板と、複数の素子電極を有する半導体素子と、前記半導体素子の素子電極上に形成された金属突起と、前記支持基板の基板電極と前記金属突起とに接合して、前記支持基板の基板電極と前記半導体素子の素子電極とを電気的に接続する金属細線と、を備え、前記金属突起は、前記金属細線より硬度が小さいことを特徴とする。
また、本発明の請求項２記載の半導体装置は、請求項１記載の半導体装置であって、前記支持基板の基板電極に、前記金属細線の先端に形成したボール部による接合部が配置されており、前記金属突起に前記金属細線のステッチボンディングによる接合部が配置されていることを特徴とする。
また、本発明の請求項３記載の半導体装置は、請求項１記載の半導体装置であって、前記支持基板の基板電極は、前記支持基板の前記半導体素子が搭載される搭載領域の周囲に１列に配置された内側基板電極と、その内側基板電極よりも前記搭載領域から遠い位置に少なくとも１列に配置された外側基板電極と、を有し、前記半導体素子の素子電極は、前記半導体素子の一主面の外周部に１列に配置された外側素子電極と、その外側素子電極よりも前記半導体素子の一主面の中心寄りに少なくとも１列に配置された内側素子電極と、を有し、前記内側基板電極および前記内側素子電極に、前記金属細線の先端に形成したボール部による接合部が配置されており、前記外側基板電極および前記外側素子電極に、前記金属細線のステッチボンディングによる接合部が配置されていることを特徴とする。
また、本発明の請求項４記載の半導体装置は、請求項１記載の半導体装置であって、前記支持基板の基板電極は、前記支持基板の前記半導体素子が搭載される搭載領域の周囲に１列に配置された内側基板電極と、その内側基板電極よりも前記搭載領域から遠い位置に少なくとも１列に配置された外側基板電極と、を有し、前記内側基板電極に、前記金属細線のステッチボンディングによる接合部が配置されており、前記外側基板電極に、前記金属細線の先端に形成したボール部による接合部が配置されており、前記半導体素子の一主面の外周部に１列に配置された素子電極上の前記金属突起には、前記金属細線の先端に形成したボール部による接合部および前記金属細線のステッチボンディングによる接合部が交互に配置されていることを特徴とする。
また、本発明の請求項５記載の半導体装置は、請求項１ないし４のいずれかに記載の半導体装置であって、前記金属突起および前記金属細線の主成分はＡｕであり、前記金属突起のＡｕの含有率は、前記金属細線のＡｕの含有率より多いことを特徴とする。
また、本発明の請求項６記載の半導体装置は、請求項１ないし５のいずれかに記載の半導体装置であって、前記金属細線の主成分はＡｕであり、Ｐｄを含んでいることを特徴とする。
また、本発明の請求項７記載の半導体装置は、請求項１ないし４のいずれかに記載の半導体装置であって、前記金属突起の主成分はＡｕであり、前記金属細線の主成分はＣｕまたはＡｌであることを特徴とする。
また、本発明の請求項８記載の半導体装置の製造方法は、支持基板に搭載された半導体素子の素子電極上に金属突起を形成する工程と、前記支持基板の基板電極と前記金属突起に、前記金属突起よりも硬度が大きい金属細線を接合する工程と、を具備することを特徴とする。
また、本発明の請求項９記載の半導体装置の製造方法は、請求項８記載の半導体装置の製造方法であって、前記支持基板の基板電極と前記金属突起とに前記金属細線を接合するに際し、前記支持基板の基板電極に、前記金属細線の先端に形成したボール部による接合部を配置し、前記金属突起に前記金属細線のステッチボンディングによる接合部を配置することを特徴とする。
また、本発明の請求項１０記載の半導体装置の製造方法は、請求項８記載の半導体装置の製造方法であって、前記支持基板の基板電極と前記金属突起とに前記金属細線を接合する工程は、前記支持基板の前記半導体素子が搭載される搭載領域の周囲に１列に配置された内側基板電極に、前記金属細線の先端に形成したボール部による接合部を配置し、前記半導体素子の一主面の外周部に１列に配置された外側素子電極上の前記金属突起に前記金属細線のステッチボンディングによる接合部を配置する工程と、前記外側素子電極よりも前記半導体素子の一主面の中心寄りに少なくとも１列に配置された内側素子電極上の前記金属突起に、前記金属細線の先端に形成したボール部による接合部を配置し、前記支持基板の前記内側基板電極よりも前記搭載領域から遠い位置に少なくとも１列に配置された外側基板電極に前記金属細線のステッチボンディングによる接合部を配置する工程と、を有することを特徴とする。
また、本発明の請求項１１記載の半導体装置の製造方法は、請求項８記載の半導体装置の製造方法であって、前記支持基板の基板電極と前記金属突起とに前記金属細線を接合する工程は、前記半導体素子の素子電極上の前記金属突起に、前記金属細線の先端に形成したボール部による接合部を配置し、前記支持基板の前記半導体素子が搭載される搭載領域の周囲に１列に配置された内側基板電極に前記金属細線のステッチボンディングによる接合部を配置する第１工程と、前記支持基板の前記内側基板電極よりも前記搭載領域から遠い位置に少なくとも１列に配置された外側基板電極に、前記金属細線の先端に形成したボール部による接合部を配置し、前記半導体素子の素子電極上の前記金属突起に前記金属細線のステッチボンディングによる接合部を配置する第２工程と、を有し、前記第１および第２工程に際し、前記半導体素子の一主面の外周部に１列に配置された素子電極上の前記金属突起に、前記金属細線の先端に形成したボール部による接合部および前記金属細線のステッチボンディングによる接合部を交互に配置することを特徴とする。
また、本発明の請求項１２記載の半導体装置の製造方法は、請求項８ないし１１のいずれかに記載の半導体装置の製造方法であって、前記金属突起および前記金属細線の主成分はＡｕであり、前記金属突起のＡｕの含有率は、前記金属細線のＡｕの含有率より多いことを特徴とする。
また、本発明の請求項１３記載の半導体装置の製造方法は、請求項８ないし１２のいずれかに記載の半導体装置の製造方法であって、前記金属細線の主成分はＡｕであり、Ｐｄを含んでいることを特徴とする。
また、本発明の請求項１４記載の半導体装置の製造方法は、請求項８ないし１１のいずれかに記載の半導体装置の製造方法であって、前記金属突起の主成分はＡｕで、前記金属細線の主成分はＣｕまたはＡｌであることを特徴とする。
また、本発明の請求項１５記載の半導体装置の製造方法は、請求項８ないし１４のいずれかに記載の半導体装置の製造方法であって、前記金属突起は、前記支持基板の基板電極と前記金属突起とを電気的に接続する金属細線よりも硬度が小さい金属細線の先端に形成したボール部を前記半導体素子の素子電極に接合し、その素子電極にボール部を介して接合した金属細線を、そのボール部から切断することで形成することを特徴とする。
本発明の好ましい形態によれば、支持基板の基板電極と半導体素子の素子電極とを電気的に接続する金属細線に硬度の大きいものを用いることにより、半導体装置の多ピン化から金属細線の長さが長くなっても、そのループ形状を維持することができ、隣接する金属細線同士の接触を防止でき、歩留まりの向上を図ることができる。
また、金属突起に硬度の小さいものを用いることにより、半導体素子の素子電極上に金属突起を形成する際や、その素子電極上に金属細線をワイヤボンディング（ボールボンディングまたはステッチボンディング）する際に、半導体素子の素子電極下に形成されている配線や素子へのダメージを低減することができる。
また、支持基板の基板電極と半導体素子の素子電極とを電気的に接続する金属細線の硬度を大きくするために、主成分であるＡｕの含有量を低減したり、金属細線に主成分がＣｕやＡｌのものを用いることにより、非常に高価な材料であるＡｕの使用量を削減することができ、低コスト化を図ることができる。
以下、本発明の実施の形態について図面を参照しながら説明する。なお、ここではＢＧＡパッケージを例に説明する。図１は本発明の第１の実施の形態に係る半導体装置であるＢＧＡパッケージを製造する工程を示す断面図である。
まず、図１（ａ）に示すように、複数の基板電極２、３を有する支持基板であるＢＧＡ基板１（以下、単に基板１と称す。）に、複数の素子電極６、７を有する半導体チップ（半導体素子）５を搭載する。基板１は、ガラスエポキシ、ＢＴレジン、ポリイミド等よりなり、その厚みは、０．０５ｍｍ〜１．６ｍｍ程度である。
基板１の上面には、基板電極として、基板１の半導体チップ５が搭載される搭載領域の周囲に１列に配置された内側基板電極２と、その内側基板電極２よりも前記搭載領域から遠い位置に１列に配置された外側基板電極３と、が形成されている。基板電極２、３は、主導体にＣｕなどを用い、その厚みは５μｍ〜３５μｍ程度である。また、基板電極２、３の表面には、Ａｕめっき等が施されている。この基板電極２、３は、半導体チップ５の素子電極６、７に電気的に接続する。
なお、ここでは、基板１の基板電極が、半導体チップ５が搭載される搭載領域の周囲に２列に配置されている場合について説明するが、基板電極の列数は２列に限定されるものではなく、さらに列数（外側基板電極の列数）を増やすことができる。
基板１の下面には、外部電極４が形成されている。外部電極４は、基板電極２、３に、基板１に形成されたビアやスルーホール（図示せず）を介して電気的に接続する。
基板１のほぼ中央部には、半導体チップ５がダイボンド樹脂（図示せず）により固着されている。半導体チップ５の固着には、エポキシ、ポリイミド等を主成分とする絶縁性樹脂やＡｇフィラーを含有した導電性樹脂などを用い、その厚みは５〜５０μｍ程度である。
半導体チップ５には、素子電極として、半導体チップ５の一主面のチップ外周部に１列に配置された外側素子電極６と、その外側素子電極６よりも半導体チップ５の一主面の中心寄りに１列に配置された内側素子電極７と、が形成されている。素子電極６、７の材質には、通常、Ａｌ、Ｃｕ等を用いる。
半導体チップの素子電極は、通常、半導体チップのチップ外周部に１列に配置されるが、半導体装置の多ピン化により素子電極数が増大した場合、１列では配置ができず、図示するように、半導体チップの外周部から内側に向かって複数列配置する。なお、素子電極の列数は２列に限られるものではなく、ピン数が増大すればさらに列数（内側素子電極の列数）を増やすことができる。
次に、図１（ｂ）に示すように、素子電極６、７上に突起電極（金属突起）８、９を形成する。ここでは、突起電極８、９は、Ａｕワイヤ（金属細線）の先端に形成したボールボンディングによるボール部（金属球）を半導体チップ５の素子電極６、７に接合した後、そのボール部の直上でＡｕワイヤをボール部から切断することで形成する。突起電極８、９の大きさは直径３０〜１００μｍ程度あり、その厚みは５〜５０μｍ程度である。突起電極８、９と素子電極６、７との接合は超音波熱圧着方式などにより行い、素子電極６、７がＡｌの場合はＡｕ−Ａｌの合金を形成することで行う。接合時の温度は５０〜３００℃、過重は５〜１００ｇ程度である。
また、突起電極８、９を形成するのにＡｕ含有率が９９．９９質量％以上のＡｕワイヤを用いることで、突起電極８、９の硬度を小さくでき、突起電極８、９を素子電極６、７に接合する際に、素子電極６、７に印加されるストレスを極めて小さくすることができ、素子電極６、７の下に配線やトランジスタ等の素子が配置されている場合でも、その配線やトランジスタ等の素子が損傷することはない。
次に、図１（ｃ）に示すように、基板１の内側基板電極２と半導体素子５の外側素子電極６上の突起電極８に、突起電極８よりも硬度が大きいボンディングワイヤ（金属細線）１２を接合し、基板１の外側基板電極３と半導体素子５の内側素子電極７上の突起電極９に、突起電極９よりも硬度が大きいボンディングワイヤ（金属細線）１３を接合して、基板１の基板電極２、３と半導体チップ５の素子電極６、７とを電気的に接続する。
ボンディングワイヤの接合は、超音波熱圧着方式などによるワイヤボンディングにより行う。すなわち、基板１の基板電極２、３にはボールボンディングを行い、ボンディングワイヤ１２、１３の先端に形成したボール部（金属球）１０、１１による接合部を配置する。また突起電極８、９にはステッチボンディングを行い、ボンディングワイヤ１２、１３のステッチボンディングによる接合部を配置する。
ボンディングワイヤ１２、１３の長さは、半導体装置のピン数が多いときは５〜８ｍｍ程度になる。ボンディングワイヤ１２、１３には、主成分であるＡｕの含有率が、突起電極８、９の主成分であるＡｕの含有率９９．９９質量％よりも少ない９９．００質量％のワイヤや、ＣｕまたはＡｌを主成分とするワイヤなどを用いる。いずれの場合も、ボンディングワイヤ１２、１３の硬度は突起電極８、９よりも大きくなり、ワイヤ長を長くしても、ループの変形が起きることはなく、ボンディングワイヤ同士の接触を防止することができる。
また、ボンディングワイヤ１２、１３に硬度の大きいものを用いても、半導体チップ５との接合は、硬度の小さい突起電極８、９を介して行われるので、半導体チップ５の素子電極６、７の下に形成されている配線やトランジスタ等の素子へのストレスを極めて小さくすることができ、歩留まりの低下を防ぐことができる。なお、ボンディングワイヤ１２、１３にＡｕ含有率が９９．００質量％のワイヤを用いた場合は、Ｐｄなどの金属を添加することで良好な接続を得ることができる。
次に、図１（ｄ）に示すように、基板１の半導体チップ５が搭載された一主面上に樹脂１４を形成し、半導体チップ５やボンディングワイヤ１２、１３等を封止し、基板１の外部電極４に、はんだ等のボール１５を形成する。
続いて、本発明の第２の実施の形態に係る半導体装置であるＢＧＡパッケージについて、図２を用いて説明する。図２は本発明の第２の実施の形態に係る半導体装置であるＢＧＡパッケージの断面図である。但し、前述した第１の実施の形態において説明した部材に対応する部材には同一符号を付して、説明を省略する。
この第２の実施の形態は、基板１の内側基板電極２に、ボンディングワイヤ１２の先端に形成したボール部（金属球）による接合部が配置されており、半導体チップ５の外側素子電極６に、ボンディングワイヤ１２のステッチボンディングによる接合部が配置されており、半導体チップ５の内側素子電極７に、ボンディングワイヤ１３の先端に形成したボール部（金属球）による接合部が配置されており、基板１の外側基板電極３に、ボンディングワイヤ１３のステッチボンディングによる接合部が配置されている点が、前述した第１の実施の形態と異なる。
このＢＧＡパッケージの製造工程は、基板１の基板電極２、３と突起電極８、９とにボンディングワイヤ１２、１３を接合する工程が、前述した実施の形態１と異なる。すなわち、基板１の内側基板電極２にボールボンディングを行い、その内側基板電極２にボンディングワイヤ１２の先端に形成したボール部１０による接合部を配置し、半導体チップ５の外側素子電極６上の突起電極８にステッチボンディングを行い、その突起電極８にボンディングワイヤ１２のステッチボンディングによる接合部を配置する。また、半導体チップ５の内側素子電極７上の突起電極９にボールボンディングを行い、その突起電極９にボンディングワイヤ１３の先端に形成したボール部１１による接合部を配置し、基板１の外側基板電極３にステッチボンディングを行い、その外側基板電極３にボンディングワイヤ１３のステッチボンディングによる接合部を配置する。
この第２の実施の形態によれば、突起電極８、９付近のボンディングワイヤ１２、１３間の距離を大きくすることができ、ボンディングワイヤ同士の接触による不良をより低減することができ、歩留まりをより向上させることができる。
続いて、本発明の第３の実施の形態に係る半導体装置であるＢＧＡパッケージについて、図３、４を用いて説明する。図３は本発明の第３の実施の形態に係る半導体装置であるＢＧＡパッケージの一部拡大平面図、図４は本発明の第３の実施の形態に係る半導体装置であるＢＧＡパッケージの一部拡大断面図である。但し、前述した第１の実施の形態において説明した部材に対応する部材には同一符号を付して、説明を省略する。
この第３の実施の形態は、半導体チップ５が、その一主面の外周部に１列に配置されている素子電極６のみを有する点が前述した第１の実施の形態と異なる。また、基板１の内側基板電極２に、ボンディングワイヤ１２のステッチボンディングによる接合部が配置されており、外側基板電極３に、ボンディングワイヤ１３の先端に形成したボール部（金属球）による接合部が配置されている点が前述した第１の実施の形態と異なる。さらに、半導体チップ５の素子電極６上の突起電極８に、内側基板電極２に接続するボンディングワイヤ１２の先端に形成したボール部（金属球）による接合部および外側基板電極３に接続するボンディングワイヤ１３のステッチボンディングによる接合部が交互に配置されている点が前述した第１の実施の形態と異なる。
このＢＧＡパッケージの製造工程は、基板１の基板電極２、３と突起電極８とにボンディングワイヤ１２、１３を接合する工程が、前述した実施の形態１と異なる。すなわち、半導体チップ５の素子電極６上の突起電極８にボールボンディングを行い、その突起電極８にボンディングワイヤ１２の先端に形成したボール部による接合部を配置し、基板１の内側基板電極２にステッチボンディングを行い、その内側基板電極２にボンディングワイヤ１２のステッチボンディングによる接合部を配置する（第１工程）。また、基板１の外側基板電極３にボールボンディングを行い、その外側基板電極３にボンディングワイヤ１３の先端に形成したボール部による接合部を配置し、半導体チップ５の素子電極６上の突起電極８にステッチボンディングを行い、その突起電極８にボンディングワイヤ１３のステッチボンディングによる接合部を配置する（第２工程）。また、この第１および第２工程に際し、半導体チップ５の素子電極６上の突起電極８に、内側基板電極２に接続するボンディングワイヤ１２の先端に形成したボール部による接合部および外側基板電極３に接続するボンディングワイヤ１３のステッチボンディングによる接合部を交互に配置する。
この第３の実施の形態によれば、半導体チップ５の突起電極８には、１つおきにボールボンディングを行うので、ボンディング時にキャピラリの傾斜部が隣接するボンディングワイヤに接触することがなく、半導体チップ５の素子電極６を狭いピッチで配置することが可能となり、高密度なパッケージを得ることができる。
また、半導体チップ５から遠い側の外側基板電極３にボールボンディングを行うので、その外側基板電極３においてボンディングワイヤ１３の立ち上がり角度を大きくすることができ、外側基板電極３を、半導体チップ５に近い側の内側基板電極２に近い配置としても、ボンディングワイヤ１３と内側基板電極２とは接触せず、ボンディングワイヤ１３を短くすることができ、コストを下げることができる。
なお、以上説明した第１ないし第３の実施の形態では、ＢＧＡパッケージを例に説明したが、無論、リードフレームを用いるＱＦＰやその他のタイプのパッケージについても同様である。
本発明にかかる半導体装置、およびその半導体装置の製造方法は、ボンディングワイヤ同士の接触を防止することができ、移動体通信機器等の電子機器に搭載する小型・多ピンの半導体装置として、またその製造方法として特に有用である。
本発明の第１の実施の形態に係る半導体装置の製造方法を説明する工程断面図 本発明の第２の実施の形態に係る半導体装置の概略構成を示す断面図 本発明の第３の実施の形態に係る半導体装置の概略構成を示す一部拡大平面図 本発明の第３の実施の形態に係る半導体装置の概略構成を示す一部拡大断面図 従来の半導体装置の断面図
符号の説明
１ ＢＧＡ基板
２ 内側基板電極
３ 外側基板電極
４ 外部電極
５ 半導体チップ
６ 外側素子電極
７ 内側素子電極
８、９ 突起電極
１０、１１ ボンディングワイヤのボール部
１２、１３ ボンディングワイヤ
１４ 樹脂
１５ はんだボール
４０ ＢＧＡ基板
４１、４２ 基板電極
４３ 半導体チップ
４４ 素子電極
４５、４７ ボンディングワイヤ
４６、４８ ボンディングワイヤのボール部

Claims (15)

  1. 複数の基板電極を有する支持基板と、
    複数の素子電極を有する半導体素子と、
    前記半導体素子の素子電極上に形成された金属突起と、
    前記支持基板の基板電極と前記金属突起とに接合して、前記支持基板の基板電極と前記半導体素子の素子電極とを電気的に接続する金属細線と、
    を備え、前記金属突起は、前記金属細線より硬度が小さいことを特徴とする半導体装置。
  2. 前記支持基板の基板電極に、前記金属細線の先端に形成したボール部による接合部が配置されており、前記金属突起に前記金属細線のステッチボンディングによる接合部が配置されていることを特徴とする請求項１記載の半導体装置。
  3. 前記支持基板の基板電極は、前記支持基板の前記半導体素子が搭載される搭載領域の周囲に１列に配置された内側基板電極と、その内側基板電極よりも前記搭載領域から遠い位置に少なくとも１列に配置された外側基板電極と、を有し、
    前記半導体素子の素子電極は、前記半導体素子の一主面の外周部に１列に配置された外側素子電極と、その外側素子電極よりも前記半導体素子の一主面の中心寄りに少なくとも１列に配置された内側素子電極と、を有し、
    前記内側基板電極および前記内側素子電極に、前記金属細線の先端に形成したボール部による接合部が配置されており、前記外側基板電極および前記外側素子電極に、前記金属細線のステッチボンディングによる接合部が配置されている
    ことを特徴とする請求項１記載の半導体装置。
  4. 前記支持基板の基板電極は、前記支持基板の前記半導体素子が搭載される搭載領域の周囲に１列に配置された内側基板電極と、その内側基板電極よりも前記搭載領域から遠い位置に少なくとも１列に配置された外側基板電極と、を有し、
    前記内側基板電極に、前記金属細線のステッチボンディングによる接合部が配置されており、前記外側基板電極に、前記金属細線の先端に形成したボール部による接合部が配置されており、
    前記半導体素子の一主面の外周部に１列に配置された素子電極上の前記金属突起には、前記金属細線の先端に形成したボール部による接合部および前記金属細線のステッチボンディングによる接合部が交互に配置されている
    ことを特徴とする請求項１記載の半導体装置。
  5. 前記金属突起および前記金属細線の主成分はＡｕであり、前記金属突起のＡｕの含有率は、前記金属細線のＡｕの含有率より多いことを特徴とする請求項１ないし４のいずれかに記載の半導体装置。
  6. 前記金属細線の主成分はＡｕであり、Ｐｄを含んでいることを特徴とする請求項１ないし５のいずれかに記載の半導体装置。
  7. 前記金属突起の主成分はＡｕであり、前記金属細線の主成分はＣｕまたはＡｌであることを特徴とする請求項１ないし４のいずれかに記載の半導体装置。
  8. 支持基板に搭載された半導体素子の素子電極上に金属突起を形成する工程と、
    前記支持基板の基板電極と前記金属突起に、前記金属突起よりも硬度が大きい金属細線を接合する工程と、
    を具備することを特徴とする半導体装置の製造方法。
  9. 前記支持基板の基板電極と前記金属突起とに前記金属細線を接合するに際し、前記支持基板の基板電極に、前記金属細線の先端に形成したボール部による接合部を配置し、前記金属突起に前記金属細線のステッチボンディングによる接合部を配置することを特徴とする請求項８記載の半導体装置の製造方法。
  10. 前記支持基板の基板電極と前記金属突起とに前記金属細線を接合する工程は、
    前記支持基板の前記半導体素子が搭載される搭載領域の周囲に１列に配置された内側基板電極に、前記金属細線の先端に形成したボール部による接合部を配置し、前記半導体素子の一主面の外周部に１列に配置された外側素子電極上の前記金属突起に前記金属細線のステッチボンディングによる接合部を配置する工程と、
    前記外側素子電極よりも前記半導体素子の一主面の中心寄りに少なくとも１列に配置された内側素子電極上の前記金属突起に、前記金属細線の先端に形成したボール部による接合部を配置し、前記支持基板の前記内側基板電極よりも前記搭載領域から遠い位置に少なくとも１列に配置された外側基板電極に前記金属細線のステッチボンディングによる接合部を配置する工程と、
    を有することを特徴とする請求項８記載の半導体装置の製造方法。
  11. 前記支持基板の基板電極と前記金属突起とに前記金属細線を接合する工程は、
    前記半導体素子の素子電極上の前記金属突起に、前記金属細線の先端に形成したボール部による接合部を配置し、前記支持基板の前記半導体素子が搭載される搭載領域の周囲に１列に配置された内側基板電極に前記金属細線のステッチボンディングによる接合部を配置する第１工程と、
    前記支持基板の前記内側基板電極よりも前記搭載領域から遠い位置に少なくとも１列に配置された外側基板電極に、前記金属細線の先端に形成したボール部による接合部を配置し、前記半導体素子の素子電極上の前記金属突起に前記金属細線のステッチボンディングによる接合部を配置する第２工程と、
    を有し、前記第１および第２工程に際し、前記半導体素子の一主面の外周部に１列に配置された素子電極上の前記金属突起に、前記金属細線の先端に形成したボール部による接合部および前記金属細線のステッチボンディングによる接合部を交互に配置する
    ことを特徴とする請求項８記載の半導体装置の製造方法。
  12. 前記金属突起および前記金属細線の主成分はＡｕであり、前記金属突起のＡｕの含有率は、前記金属細線のＡｕの含有率より多いことを特徴とする請求項８ないし１１のいずれかに記載の半導体装置の製造方法。
  13. 前記金属細線の主成分はＡｕであり、Ｐｄを含んでいることを特徴とする請求項８ないし１２のいずれかに記載の半導体装置の製造方法。
  14. 前記金属突起の主成分はＡｕで、前記金属細線の主成分はＣｕまたはＡｌであることを特徴とする請求項８ないし１１のいずれかに記載の半導体装置の製造方法。
  15. 前記金属突起は、前記支持基板の基板電極と前記金属突起とを電気的に接続する金属細線よりも硬度が小さい金属細線の先端に形成したボール部を前記半導体素子の素子電極に接合し、その素子電極にボール部を介して接合した金属細線を、そのボール部から切断することで形成することを特徴とする請求項８ないし１４のいずれかに記載の半導体装置の製造方法。
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JP2014027216A (ja) * 2012-07-30 2014-02-06 Renesas Electronics Corp 半導体装置およびその製造方法
JP2019159189A (ja) * 2018-03-15 2019-09-19 住友大阪セメント株式会社 光変調器、及び光伝送装置

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JP6196092B2 (ja) * 2013-07-30 2017-09-13 ルネサスエレクトロニクス株式会社 半導体装置
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JP2019159189A (ja) * 2018-03-15 2019-09-19 住友大阪セメント株式会社 光変調器、及び光伝送装置
JP7052444B2 (ja) 2018-03-15 2022-04-12 住友大阪セメント株式会社 光変調器、及び光伝送装置

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