CN101364578A - 半导体器件和该半导体器件的制造方法 - Google Patents

半导体器件和该半导体器件的制造方法 Download PDF

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CN101364578A
CN101364578A CNA2008101312950A CN200810131295A CN101364578A CN 101364578 A CN101364578 A CN 101364578A CN A2008101312950 A CNA2008101312950 A CN A2008101312950A CN 200810131295 A CN200810131295 A CN 200810131295A CN 101364578 A CN101364578 A CN 101364578A
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Prior art keywords
electrode
metal fine
described metal
substrate
semiconductor element
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田边学
藤本博昭
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Publication of CN101364578A publication Critical patent/CN101364578A/zh
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Abstract

本发明提供能防止将基板的电极与半导体元件的电极电连接的金属细线之间的接触的半导体器件。本发明涉及的半导体器件在半导体元件的电极上形成其硬度小于金属细线的硬度的金属突起，该金属突起与金属细线接合。

Description

半导体器件和该半导体器件的制造方法
技术领域
本发明涉及半导体器件和该半导体器件的制造方法。
背景技术
近年来，移动通信设备等电子设备正向小型化、高性能化、多功能化方向发展，为了与之相适应，半导体器件趋向小型化、高密度化、多引脚化。例如越来越多地使用在其底面以面阵列状配置外部端子的组件型半导体器件。另外，沿芯片的外周部(周边部)以交错配置等方式配置多列将被封装的半导体芯片的电极，因此，电连接半导体芯片的电极与组件的电极的接合金属丝较长。
作为这样的组件型半导体器件的一个例子，有BGA(Ball Grid Array：球栅阵列)组件。图8表示现有的BGA组件。
如图8所示，这种BGA组件包括：BGA基板40(以下简称为基板40)；形成在基板40上的电极41、42；固接于基板40上的半导体芯片43；形成于半导体芯片43的表面的电极44a、44b；以及电连接半导体芯片的电极44a、44b与基板的电极41、42的接合金属丝45、47。半导体芯片的电极44a、44b与由形成于接合金属丝45、47的前端的球形部46、48构成的接合部接合。
在这样的BGA组件中，接合金属丝45与配置在半导体芯片43的外周部的电极44a连接，接合金属丝47与配置在比该外周部的电极44a更靠近中心的位置上的电极44b连接，为了保持接合金属丝45与接合金属丝47之间的距离，将与外周部的电极44a连接的接合金属丝45的环形高度设得尽可能低(例如参照日本专利特开平8—340018号公报)。
如上所述，以往为了使相邻的接合金属丝之间互不接触，在半导体器件中三维配置接合金属丝。
而且，以往为了在接合金属丝与半导体芯片的电极接合时不损坏该电极下面的布线等，以金(Au)为主要成分构成接合金属丝。
但是，若为了防止半导体芯片内部的布线等的损坏而以Au为主要成分构成接合金属丝，则难以维持接合金属丝的环形形状，接合金属丝之间有时会接触，该接触导致合格率下降。
发明内容
鉴于上述问题，本发明目的在于，提供能防止接合金属丝之间相互接触，并提高合格率的半导体器件和该半导体器件的制造方法。
为实现上述目的，本发明的第1半导体器件包括具有多个电极的基板；安装在上述基板上的具有多个电极的半导体元件；分别形成在上述半导体元件的电极上的各金属突起；以及各金属细线，所述各金属细线分别与上述基板的电极和上述金属突起接合，电连接上述基板的电极与上述半导体元件的电极，且上述各金属突起的硬度小于与上述各金属突起接合的上述各金属细线的硬度。
本发明的第2半导体器件基于上述第1半导体器件，上述基板的电极与由形成于上述金属细线的前端的球形部构成的接合部接合，上述金属突起与利用上述金属细线的针脚式接合形成的接合部接合。
本发明的第3半导体器件基于上述第1半导体器件，上述基板的多个电极包括多个内侧电极和多个外侧电极，所述多个内侧电极在上述基板的安装上述半导体元件的安装区域的周围排成1列，所述多个外侧电极在比这些内侧电极更远离上述安装区域的位置上排成至少1列。而且，上述半导体元件的多个电极包括多个外侧电极和多个内侧电极，所述多个外侧电极在上述半导体元件的一个主面的外周部排成1列，所述多个内侧电极在比这些外侧电极更靠近上述一个主面的中心的位置上至少排成1列。此外，上述基板的内侧电极以及上述半导体元件的内侧电极上的上述金属突起与由形成于上述金属细线的前端的球形部构成的接合部接合，上述基板的外侧电极以及上述半导体元件的外侧电极上的上述金属突起与利用上述金属细线的针脚式接合形成的接合部接合。
本发明的第4半导体器件基于上述第1半导体器件，上述基板的多个电极包括多个内侧电极和多个外侧电极，所述多个内侧电极在上述基板的安装上述半导体元件的安装区域的周围排成1列，所述多个外侧电极在比这些内侧电极更远离上述安装区域的位置上排成至少1列。而且，上述基板的外侧电极与由形成于上述金属细线的前端的球形部构成的接合部接合，上述基板的内侧电极与利用上述金属细线的针脚式接合形成的接合部接合。此外，将上述半导体元件的多个电极在上述半导体元件的一个主面的外周部排成1列，多个上述金属突起与由形成于上述金属细线的前端的球形部构成的接合部以及由上述金属细线的针脚式接合形成的接合部交替接合。
本发明的第5半导体器件基于上述第1半导体器件，上述金属突起和上述金属细线的主要成分是金，上述金属突起的含金率多于上述金属细线的含金率。
本发明的第6半导体器件基于上述第1半导体器件，上述金属细线的主要成分是金，且上述金属细线含有钯。
本发明的第7半导体器件基于上述第1半导体器件，上述金属突起的主要成分是金，上述金属细线的主要成分是铜或铝。
另外，本发明的第1半导体器件的制造方法包括：在安装于基板的半导体元件的电极上形成金属突起的工序；以及将硬度大于上述金属突起的金属细线与上述基板的电极和上述金属突起接合的工序。
本发明的第2半导体器件的制造方法基于上述第1半导体器件的制造方法，在将上述金属细线与上述基板的电极和上述金属突起接合时，在上述基板的电极上接合由形成于上述金属细线的前端的球形部构成的接合部，在上述金属突起上接合利用上述金属细线的针脚式接合形成的接合部。
本发明的第3半导体器件的制造方法基于上述第1半导体器件的制造方法，将上述金属细线与上述基板的电极和上述金属突起接合的工序包括：在配置于上述基板的安装上述半导体元件的安装区域的周围的1列上述基板的内侧电极上，接合由形成于上述金属细线的前端的球形部构成的接合部，在配置于上述半导体元件的一个主面的外周部的1列上述半导体元件的外侧电极上的上述金属突起上，接合利用上述金属细线的针脚式接合形成的接合部的工序；以及在配置于比上述半导体元件的外侧电极更靠近上述一个主面的中心的位置的1列上述半导体元件的内侧电极上的上述金属突起上，接合由形成于上述金属细线的前端的球形部构成的接合部，在配置于比上述基板的内侧电极更远离上述安装区域的位置的至少1列上述基板的外侧电极上，接合利用上述金属细线的针脚式接合形成的接合部的工序。
本发明的第4半导体器件的制造方法基于上述第1半导体器件的制造方法，将上述金属细线与上述基板的电极和上述金属突起接合的工序包括：第1工序，所述第1工序在上述半导体元件的电极上的上述金属突起上，接合由形成于上述金属细线的前端的球形部构成的接合部，在配置于上述基板的安装上述半导体元件的安装区域的周围的1列上述基板的内侧电极上，接合利用上述金属细线的针脚式接合形成的接合部；以及第2工序，所述第2工序在配置于比上述基板的内侧电极更远离上述安装区域的位置的至少1列上述基板的外侧电极上，接合由形成于上述金属细线的前端的球形部构成的接合部，在上述半导体元件的电极上的上述金属突起上，接合利用上述金属细线的针脚式接合形成的接合部。而且，在进行上述第1工序和第2工序时，在配置于上述半导体元件的一个主面的外周部的1列上述半导体元件的电极上的上述金属突起上，交替接合由形成于上述金属细线的前端的球形部构成的接合部和利用上述金属细线的针脚式接合形成的接合部。
本发明的第5半导体器件的制造方法基于上述第1半导体器件的制造方法，上述金属突起和上述金属细线的主要成分是金，上述金属突起的含金率多于上述金属细线的含金率。
本发明的第6半导体器件的制造方法基于上述第1半导体器件的制造方法，上述金属细线的主要成分是金，且上述金属细线含钯。
本发明的第7半导体器件的制造方法基于上述第1半导体器件的制造方法，上述金属突起的主要成分是金，上述金属细线的主要成分是铜或铝。
本发明的第8半导体器件的制造方法基于上述第1半导体器件的制造方法，将形成于金属细线的前端的球形部与上述半导体元件的电极接合，所述金属细线的硬度小于电连接上述基板的电极与上述半导体元件的电极的金属细线的硬度，将该硬度小的金属细线从球形部切断，从而形成上述金属突起。
根据本发明的理想形态，基板的电极与半导体元件的电极的电连接采用硬度大的金属细线，因此即使金属细线的长度随半导体器件的多引脚化而增加，也能维持金属细线的环形形状，防止相邻金属细线之间发生接触，提高合格率。
通过使用硬度小的金属突起，在半导体元件的电极上形成金属突起时或在该电极上接合金属细线(球形接合或针脚式接合)时能减少对形成于半导体元件的电极下面的布线和元件的损坏。
另外，为了增加电连接基板的电极与半导体元件的电极的金属细线的硬度，减少主要成分金(Au)的含量或使用主要成分是铜(Aμ)或铝(Al)的金属细线，这样能减少价格高昂的材料Au的使用量，谋求降低成本。
本发明的半导体器件以及该半导体器件的制造方法能防止接合金属丝间的接触，尤其可用于安装于移动通信设备等电子设备的小型·多引脚的半导体器件及其制造方法。
附图说明
图1是用于说明本发明实施方式1的半导体器件的制造方法的工序剖视图。
图2是用于说明本发明实施方式1的半导体器件的制造方法的工序剖视图。
图3是用于说明本发明实施方式1的半导体器件的制造方法的工序剖视图。
图4是用于说明本发明实施方式1的半导体器件的制造方法的工序剖视图。
图5是表示本发明实施方式2的半导体器件的概略结构的剖视图。
图6是表示本发明实施方式3的半导体器件的概略结构的局部放大俯视图。
图7是表示本发明实施方式3的半导体器件的概略结构的局部放大剖视图。
图8是现有的半导体器件的剖视图。
具体实施方式
下面参照附图对本发明的实施方式进行说明。另外，这里以BGA组件为例进行说明。图1～图4是表示制造本发明实施方式1的半导体器件即BGA组件的工序的剖视图。
首先，如图1所示，在具有多个电极2、3的基板即BGA基板1(以下简称为基板1)上安装具有多个电极6、7的半导体芯片(半导体元件)5。基板1由玻纤环氧材料、BT树脂、聚酰亚胺等形成，其厚度为0.05mm～1.6mm左右。
在基板1的上表面，作为电极，形成有在基板1的安装半导体芯片5的安装区域的周围配置的1列内侧电极2和在比上述内侧电极2更远离上述安装区域的位置上配置的1列外侧电极3。电极2、3的主导体为铜(Cu)等，电极2、3的厚度为5μm～35μm左右。而且，电极2、3的表面被镀金等。该电极2、3与半导体芯片5的电极6、7电连接。
另外，在这里对在安装半导体芯片5的安装区域的周围配置2列基板1的电极的情况进行说明，但基板的电极的列数不限于2列，可进一步增加列数(外侧电极的列数)。
在基板1的下表面形成外部电极4。外部电极4通过形成于基板1的导通孔或通孔(未图示)与基板的电极2、3电连接。
半导体芯片5利用芯片接合树脂(未图示)固接于基板1的大致中央部。半导体芯片5的固接采用以环氧树脂、聚酰亚胺等为主要成分的绝缘性树脂或含有Ag填充剂的导电性树脂等，其固接部的厚度为5～50μm左右。
在半导体芯片5上，作为电极，形成有在半导体芯片5的一个主面的外周部配置的1列外侧电极6和在比该外侧电极6更靠近半导体芯片5的一个主面的中心的位置上配置的1列内侧电极7。电极6、7通常由铝(Al)或铜(Cu)等构成。
通常在半导体芯片的外周部配置1列半导体芯片的电极。但是在因半导体器件的多引脚化而使电极数增加的情况下，无法在1列中配置所有电极。因此，在这种情况下，从半导体芯片的外周部向内侧配置多列电极。另外，半导体元件的电极的列数不限于2列，若引脚数增加，则可进一步增加列数(内侧电极的列数)。
接着，如图2所示，在半导体元件的电极6、7上形成突起电极(金属突起)8、9。这里，在半导体芯片5的电极6、7上进行球形接合，将形成于Au丝(金属细线)前端的球形部(金属球)与半导体芯片5的电极6、7接合后，在该球形部的正上方将Au丝从球形部上切下，形成突起电极8、9。突起电极8、9的大小为直径30～100μm左右，其厚度为5～50μm左右。通过超声波热压接合方式等进行突起电极8、9与半导体元件的电极6、7的接合。当半导体元件的电极6、7由铝(Al)形成时，利用超声波热压接方式形成Au—Al的合金。接合时的温度为50～300℃，负荷为5～100g左右。
另外，通过用Au含有率为99.99质量％以上的Au丝形成突起电极8、9，可减小突起电极8、9的硬度，将突起电极8、9与半导体元件的电极6、7接合时，可使施加于上述电极6、7的应力为极小。因此，即使在上述电极6、7的下面配置布线或晶体管等元件的情况下，也不会损坏该布线或晶体管等元件。
下面，如图3所示，将硬度大于突起电极8的接合金属丝(金属细线)12与基板1的内侧电极2和半导体元件5的外侧电极6上的突起电极8接合，将硬度大于突起电极9的接合金属丝(金属细线)13与基板1的外侧电极3和半导体元件5的内侧电极7上的突起电极9接合，从而将基板1的电极2、3与半导体芯片5的电极6、7电连接。
在连接接合金属丝时，利用超声波热压接方式等进行金属丝接合。即通过球形接合，在基板1的电极2、3上接合由形成于接合金属丝12、13的前端的球形部(金属球)10、11构成的接合部。另外，借助于针脚式接合，在突起电极8、9上接合利用接合金属丝12、13的针脚式接合形成的接合部。
当半导体器件的引脚数多时，接合金属丝12、13的长度为5～8mm左右。接合金属丝12、13采用主要成分金(Au)的含有率为99.00质量％的，少于突起电极8、9的主要成分金(Au)的含有率99.99质量％的金属丝，或以铜(Cu)或铝(Al)为主要成分的金属丝等。在任一种情况下，接合金属丝12、13的硬度均大于突起电极8、9的硬度，即使金属丝长度增加，也不会引起环的变形，可防止接合金属丝之间相互接触。
另外，即使使用硬度大的接合金属丝12、13，由于接合金属丝12、13与半导体芯片5的接合通过硬度小的突起电极8、9来进行，因此，可使施加于半导体芯片5的电极6、7下面形成的布线或晶体管等元件上的应力大大减小，能防止合格率的下降。另外，当接合金属丝12、13采用Au含有率为99.00质量％的金属丝时，最好在接合金属丝中添加钯(Pd)等金属。这样能获得良好的连接。
接着，如图4所示，为了封装半导体芯片5和接合金属丝12、13等，在安装基板1的半导体芯片5的一个主面上形成树脂14。然后，在基板1的外部电极4上形成焊锡等的球15。
下面用图5对本发明实施方式2的半导体器件即BGA组件进行说明。图5是本发明实施方式2的半导体器件即BGA组件的剖视图。但是，与上述实施方式1所述的构件对应的构件采用同一符号，并省略说明。
该实施方式2在基板1的内侧电极2上接合由形成于接合金属丝12的前端的球形部(金属球)10构成的接合部，在半导体芯片5的外侧电极6上的突起电极8上，接合利用接合金属丝12的针脚式接合形成的接合部，在半导体芯片5的内侧电极7上的突起电极9上，接合由形成于接合金属丝13的前端的球形部(金属球)11构成的接合部，在基板1的外侧电极3上，接合利用接合金属丝13的针脚式接合形成的接合部，这点与上述实施方式1不同。
该BGA组件的制造工序中，将接合金属丝12、13接合于基板1的电极2、3和突起电极8、9上的工序与上述实施方式1不同。即在基板1的内侧电极2上进行球形接合，将由形成于接合金属丝12的前端的球形部10构成的接合部与该内侧电极2接合，在半导体芯片5的外侧电极6上的突起电极8上进行针脚式接合，将利用接合金属丝12的针脚式接合形成的接合部与该突起电极8接合。而且，在半导体芯片5的内侧电极7上的突起电极9上进行球形接合，将由形成于接合金属丝13的前端的球形部11构成的接合部与该突起电极9接合，在基板1的外侧电极3上进行针脚式接合，将利用接合金属丝13的针脚式接合形成的接合部与该外侧电极3接合。
若采用该实施方式2，则可增加突起电极8、9附近的接合金属丝12、13间的距离，能进一步减少因接合金属丝间的接触而导致的废品，能进一步提高合格率。
下面用图6、图7对本发明实施方式3的半导体器件即BGA组件进行说明。图6是本发明实施方式3的半导体器件即BGA组件的局部放大俯视图，图7是本发明实施方式3的半导体器件即BGA组件的局部放大剖视图。但是，与上述实施方式1所述的构件对应的构件采用同一符号，并省略说明。
该实施方式3中，半导体芯片5仅具有成1列配置在其一个主面的外周部的电极6，这点与上述实施方式1不同。而且，在基板1的内侧电极2上，接合利用接合金属丝12的针脚式接合形成的接合部，在基板1的外侧电极3上，接合由形成于接合金属丝13的前端的球形部(金属球)11构成的接合部，这点与上述实施方式1不同。此外，在半导体芯片5的电极6上的突起电极8上，交替接合由形成于与基板1的内侧电极2连接的接合金属丝12的前端的球形部(金属球)10构成的接合部以及利用与基板1的外侧电极3连接的接合金属丝13的针脚式接合形成的接合部，这点也与上述实施方式1不同。
该BGA组件的制造工序中，将接合金属丝12、13与基板1的电极2、3和突起电极8接合的工序与上述实施方式1不同。即在半导体芯片5的电极6上的突起电极8上进行球形接合，将由形成于接合金属丝12的前端的球形部10构成的接合部与该突起电极8接合，在基板1的内侧电极2上进行针脚式接合，将利用接合金属丝12的针脚式接合形成的接合部与该内侧电极2接合(第1工序)。另外，在基板1的外侧电极3上进行球形接合，将由形成于接合金属丝13的前端的球形部11构成的接合部与该外侧电极3接合，在半导体芯片5的电极6上的突起电极8上进行针脚式接合，将利用接合金属丝13的针脚式接合形成的接合部与该突起电极8接合(第2工序)。此外，在进行上述第1工序和第2工序时，在半导体芯片5的电极6上的突起电极8上，交替接合由形成于与基板1的内侧电极2连接的接合金属丝12的前端的球形部10构成的接合部以及利用与基板1的外侧电极3连接的接合金属丝13的针脚式接合形成的接合部。
如果采用该实施方式3，由于每隔一个突起电极8对半导体芯片5的突起电极8进行球形接合，因此在接合时，毛细管的倾斜部不会与相邻的接合金属丝接触，能以狭小的间距配置半导体芯片5的电极6，可获得高密度的组件。
而且，由于对基板1的电极中远离半导体芯片5侧的外侧电极3进行球形接合，因而能增加该外侧电极3上接合金属丝13的立起角度。因此，即使将基板1的外侧电极3配置在与靠近半导体芯片5侧的内侧电极2接近的位置上，接合金属丝13与基板1的内侧电极2也不会接触，能缩短接合金属丝13，降低成本。
另外，实施方式1～实施方式3以本发明在BGA组件中的使用情况为例进行了说明，当然，本发明也同样可在使用引线框的QFP及其他类型的组件中使用。

Claims (15)

1.一种半导体器件，其特征在于，包括：
具有多个电极的基板；
安装在所述基板上的具有多个电极的半导体元件；
分别形成在所述半导体元件的电极上的各金属突起；以及
各金属细线，所述各金属细线分别与所述基板的电极和所述金属突起接合，将所述基板的电极与所述半导体元件的电极电连接，
所述各金属突起的硬度小于与所述各金属突起接合的所述各金属细线的硬度。
2.如权利要求1所述的半导体器件，其特征在于，所述基板的电极与由形成于所述金属细线的前端的球形部构成的接合部接合，所述金属突起与利用所述金属细线的针脚式接合形成的接合部接合。
3.如权利要求1所述的半导体器件，其特征在于，
所述基板的多个电极包括多个内侧电极和多个外侧电极，所述多个内侧电极在所述基板的安装所述半导体元件的安装区域的周围排成1列，所述多个外侧电极在比所述内侧电极更远离所述安装区域的位置上排成至少1列，
所述半导体元件的多个电极包括多个外侧电极和多个内侧电极，所述多个外侧电极在所述半导体元件的一个主面的外周部排成1列，所述多个内侧电极在比所述外侧电极更靠近所述一个主面的中心的位置上排成至少1列，
所述基板的内侧电极以及所述半导体元件的内侧电极上的所述金属突起与由形成于所述金属细线的前端的球形部构成的接合部接合，所述基板的外侧电极以及所述半导体元件的外侧电极上的所述金属突起与利用所述金属细线的针脚式接合形成的接合部接合。
4.如权利要求1所述的半导体器件，其特征在于，
所述基板的多个电极包括多个内侧电极和多个外侧电极，所述多个内侧电极在所述基板的安装所述半导体元件的安装区域的周围排成1列，所述多个外侧电极在比所述内侧电极更远离所述安装区域的位置上排成至少1列，
所述基板的外侧电极与由形成于所述金属细线的前端的球形部构成的接合部接合，所述基板的内侧电极与利用所述金属细线的针脚式接合形成的接合部接合，
所述半导体元件的多个电极在所述半导体元件的一个主面的外周部排成1列，多个所述金属突起与由形成于所述金属细线的前端的球形部构成的接合部以及利用所述金属细线的针脚式接合形成的接合部交替接合。
5.如权利要求1所述的半导体器件，其特征在于，所述金属突起和所述金属细线的主要成分是金，所述金属突起的含金率多于所述金属细线的含金率。
6.如权利要求1所述的半导体器件，其特征在于，所述金属细线的主要成分是金，且所述金属细线含有钯。
7.如权利要求1所述的半导体器件，其特征在于，所述金属突起的主要成分是金，所述金属细线的主要成分是铜或铝。
8.一种半导体器件的制造方法，其特征在于，包括：
在安装于基板的半导体元件的电极上形成金属突起的工序；以及
将硬度大于所述金属突起的金属细线与所述基板的电极和所述金属突起接合的工序。
9.如权利要求8所述的半导体器件的制造方法，其特征在于，在将所述金属细线与所述基板的电极和所述金属突起接合时，在所述基板的电极上接合由形成于所述金属细线的前端的球形部构成的接合部，在所述金属突起上接合利用所述金属细线的针脚式接合形成的接合部。
10.如权利要求8所述的半导体器件的制造方法，其特征在于，将所述金属细线与所述基板的电极和所述金属突起接合的工序包括：
在配置于所述基板的安装所述半导体元件的安装区域的周围的1列所述基板的内侧电极上，接合由形成于所述金属细线的前端的球形部构成的接合部，在配置于所述半导体元件的一个主面的外周部的1列所述半导体元件的外侧电极上的所述金属突起上，接合利用所述金属细线的针脚式接合形成的接合部的工序；以及
在配置于比所述半导体元件的外侧电极更靠近所述一个主面的中心的位置上的至少1列所述半导体元件的内侧电极上的所述金属突起上，接合由形成于所述金属细线的前端的球形部构成的接合部，在配置于比所述基板的内侧电极更远离所述安装区域的位置的至少1列所述基板的外侧电极上，接合利用所述金属细线的针脚式接合形成的接合部的工序。
11.如权利要求8所述的半导体器件的制造方法，其特征在于，将所述金属细线与所述基板的电极和所述金属突起接合的工序包括：
第1工序，所述第1工序在所述半导体元件的电极上的所述金属突起上，接合由形成于所述金属细线的前端的球形部构成的接合部，在配置于所述基板的安装所述半导体元件的安装区域的周围的1列所述基板的内侧电极上，接合利用所述金属细线的针脚式接合形成的接合部；以及
第2工序，所述第2工序在配置于比所述基板的内侧电极更远离所述安装区域的位置的至少1列所述基板的外侧电极上，接合由形成于所述金属细线的前端的球形部构成的接合部，在所述半导体元件的电极上的所述金属突起上，接合利用所述金属细线的针脚式接合形成的接合部，
在进行所述第1工序和所述第2工序时，在配置于所述半导体元件的一个主面的外周部的1列所述半导体元件的电极上的所述金属突起上，交替接合由形成于所述金属细线的前端的球形部构成的接合部和利用所述金属细线的针脚式接合形成的接合部。
12.如权利要求8所述的半导体器件的制造方法，其特征在于，所述金属突起和所述金属细线的主要成分是金，所述金属突起的含金率多于所述金属细线的含金率。
13.如权利要求8所述的半导体器件的制造方法，其特征在于，所述金属细线的主要成分是金，且所述金属细线含有钯。
14.如权利要求8所述的半导体器件的制造方法，其特征在于，所述金属突起的主要成分是金，所述金属细线的主要成分是铜或铝。
15.如权利要求8所述的半导体器件的制造方法，其特征在于，将形成于金属细线的前端的球形部与所述半导体元件的电极接合，所述金属细线的硬度小于电连接所述基板的电极与所述半导体元件的电极的金属细线，将该硬度小的金属细线从球形部切断，从而形成所述金属突起。
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CN109037184B (zh) * 2013-07-30 2022-05-03 瑞萨电子株式会社 半导体器件
CN106796896A (zh) * 2014-09-01 2017-05-31 株式会社电装 半导体装置
CN106796896B (zh) * 2014-09-01 2019-07-09 株式会社电装 半导体装置

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