TW201742209A - 積體扇出型封裝體 - Google Patents

積體扇出型封裝體 Download PDF

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Publication number
TW201742209A
TW201742209A TW105137580A TW105137580A TW201742209A TW 201742209 A TW201742209 A TW 201742209A TW 105137580 A TW105137580 A TW 105137580A TW 105137580 A TW105137580 A TW 105137580A TW 201742209 A TW201742209 A TW 201742209A
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Taiwan
Prior art keywords
conductive
adhesive layer
integrated circuit
conductive pillar
pillars
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TW105137580A
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English (en)
Inventor
張智浩
廖信宏
蔡豪益
黃見翎
張緯森
江宗憲
郭庭豪
Original Assignee
台灣積體電路製造股份有限公司
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Publication of TW201742209A publication Critical patent/TW201742209A/zh

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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
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    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
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Abstract

一種積體扇出型封裝的製造方法包括下列步驟。將多個導電柱體放置在基板的多個開孔中。提供具有黏著層在其上的載板。將開孔中的導電柱體貼附至黏著層上，以使站立狀態的導電柱體被轉移到載板上。將積體電路組件設置在具有導電柱體貼附在其上的黏著層上。形成絕緣包封體以包覆積體電路組件以及導電柱體。在絕緣包封體、積體電路組件以及導電柱體上形成重佈線路結構，重佈線路結構與積體電路組件以及導電柱體電性連接。移除載板。移除至少部分的黏著層以將導電柱體的表面暴露。在導電柱體被暴露的表面上形成多個導電端子。

Description

積體扇出型封裝體
本發明的實施例是有關於一種積體扇出型封裝體。
由於不同電子元件(例如是電晶體、二極體、電阻、電容等)的積體密度持續地增進，半導體工業經歷了快速成長。大部分而言，積集度的增進是來自於最小特徵尺寸(feature size)上不斷地縮減，這允許更多的較小元件能夠被整合到一預定區域內。較小的電子元件會需要比以往體積更小的封裝。較小型的半導體元件封裝包括有四面扁平封裝(quad flat packages，QFPs)、接腳柵格陣列(pin grid array，PGA)封裝、球狀柵格陣列(ball grid array，BGA)封裝等等。
近來，由於積體扇出型封裝體的高積集度(compactness)，積體扇出型封裝體已逐漸成為主流。如何降低積體扇出型封裝體的製造成本已成為重要的議題。
依據本發明的一些實施例，一種積體扇出型封裝體的製造方法被提出。此積體扇出型封裝的製造方法包括下列步驟。將多個導電柱體放置在基板的多個開孔中。提供具有黏著層在其上的載板。將開孔中的導電柱體貼附至黏著層上，以使站立狀態(standing orientation)的導電柱體被轉移到載板上。將積體電路組件設置在具有導電柱體貼附在其上的黏著層上。形成絕緣包封體以包覆積體電路組件以及導電柱體。在絕緣包封體、積體電路組件以及導電柱體上形成重佈線路結構，其中重佈線路結構與積體電路組件以及導電柱體電性連接。移除載板。移除至少部分的黏著層以將導電柱體的表面暴露。在導電柱體被暴露的表面上形成多個導電端子。
以下內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本發明為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本發明在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地做出解釋。
圖1至圖9為依照一些實施例所繪示的一種積體扇出型封裝體的製造流程圖。請參照圖1，提供基板SUB以及載板C，基板SUB具有呈陣列排列的開孔AP，而載板C具有剝離層DB以及黏著層AD堆疊在其上。在一些實施例中，基板SUB可為鋼板(stencil)，剝離層DB形成在載板C的上表面上，且剝離層DB位在载板C與黏著層AD之間。載板C例如是玻璃基板，而剝離層DB例如是形成在玻璃基板上的光熱轉換釋放層(LTHC)。然而，前述剝離層DB與載板C的材質僅為舉例之用，本發明的實施例不以此為限。
如圖1所示，提供多個預先製造完成的導電柱體102，並且將導電柱體102放置在基板SUB的開孔AP中。在一些實施例中，這些預先製造完成的導電柱體102(例如銅柱體或其他適合的金屬柱體)會被提供至基板SUB上，且導電柱體102可通過振動機台的振動以使導電柱體102能夠被部分地塞入基板SUB的開孔AP中。通過適當的振動機台的振動控制(例如振動頻率及/或振動振幅)，除了基板SUB會被振動之外，具有實質上相同高度的預先製造完成的導電柱體120可被驅使而在基板SUB上移動，進而成功地落入基板SUB的開孔AP中。由於導電柱體102是預先製造完成的，因此具有特定高寬比例的導電柱體102，特別是高寬比例較大(例如高寬比例大於1:3)的導電柱體102可被輕易地製造出來。此外，由於導電柱體102並非採用濺鍍、微影、電鍍以及光阻剝除等製程來製造，因此導電柱體102的製造成本與製造工時可減少。在一些實施例中，預先製造的導電柱體102的高度介於100微米至300微米之間，而預先製造的導電柱體102的寬度介於150微米至300微米之間。在一些其他實施例中，預先製造的導電柱體102的高度介於100微米至500微米之間，而預先製造的導電柱體102的寬度介於150微米至300微米之間。
在一些實施例中，各個導電柱體102包括第一部分102a以及與第一部分102a連接的第二部分102b。導電柱體102的第一部分102a被設計為能夠塞進基板SUB的開孔AP中，而導電柱體102的第二部分102b為凸緣(flange)且仍然位在基板SUB的開孔AP之外。導電柱體102中第一部分102a的寬度W1小於開孔AP的寬度W，而導電柱體102中第二部分102b的寬度W2大於開孔AP的寬度W。導電柱體102的第二部分102b覆蓋基板SUB的開孔AP並且部分地覆蓋住基板SUB的上表面。導電柱體102的第一部分102a與第二部分102b可採用相同材料或不同材料製作。
在一些實施例中，導電柱體102可採用直行切割製程(straight cutting process)預先製作完成。在一些其他實施例中，導電柱體102可採用直行切割製程以及鍛頭製程(heading process)預先製作完成。預先製作完成的導電柱體102的特性(例如寬度、高度、形狀、電氣特性等)可事先被檢測。據此，導電柱體102的製造良率可獲一定程度的提升。由於導電柱體102是預先製作完成的，製造容忍度(fabrication tolerance)所導致的導電柱體102在高度上的變化可較為輕易地且較有彈性地被控制。在一些實施例中，導電柱體102在水平高度上的變化大於1微米且小於10微米。
請參照圖2，將具有剝離層DB以及黏著層AD堆疊在其上的載板C翻覆至基板SUB上並與基板SUB接合，以使得導電柱體102的第二部分102b與黏著層AD相黏著。當黏著層AD被壓在導電柱體102的第二部分102b上並且與導電柱體102的第二部分102b接合時，導電柱體102的第二部分102b會部分地嵌於或陷入黏著層AD中。
如圖2所示，在一些實施例中，當具有剝離層DB以及黏著層AD堆疊在其上的載板C被翻覆至基板SUB上並與基板SUB接合時，黏著層AD會與基板SUB以及導電柱體102的第二部分102b的上表面相黏著。在一些其他實施例中，當具有剝離層DB以及黏著層AD堆疊在其上的載板C被翻覆至導電柱體102的第二部分102b上並與導電柱體102的第二部分102b接合時，黏著層AD實質上不與基板SUB的上表面接觸(即，黏著層AD與基板SUB的上表面之間未產生黏著性)。
請參照圖2與圖3，在黏著層AD與導電柱體102的第二部分102b的上表面相黏著後，載板C會被驅動而向上移動，進而將導電柱體102從基板SUB的開孔AP中拉出。黏著層AD提供足夠的黏著力將導電柱體102從基板SUB的開孔AP中拉出，以使得呈站立狀態的導電柱體102能夠被轉移到黏著層AD上。
請參照圖3，在導電柱體102從基板SUB被轉移到黏著層AD上之後，導電柱體102的第二部分102b會嵌於黏著層AD中，其中黏著層AD的厚度介於約3微米至約30微米之間，而第二部分102b的嵌入深度介於約1微米至約10微米之間。在一些實施例中，第二部分102b的嵌入深度的變化可大於1微米並且小於10微米。當在導電柱體102被轉移到黏著層AD上並且嵌於黏著層AD中時，導電柱體102的底表面之間的水平高度差異ΔH(繪示於圖11A製圖11C中的放大部分)可大於1微米並且小於10微米。此處，水平高度差異ΔH定義為導電柱體102的底表面所在的最低水平高度以及最高水平高度的差異。接著，再次將具有剝離層DB、黏著層AD以及導電柱體102堆疊在其上的載板C翻覆以為後續製程作準備。
如圖3所示，將積體電路組件104設置在具有導電柱體102貼附在其上的黏著層AD上。黏著層AD用以作為晶粒貼附薄膜(DAF)。積體電路組件104包括主動表面104a、多個分佈在主動表面104a上的焊墊104b、覆蓋主動表面104a的鈍化層104c、多個導電柱(conductive pillars)104d以及保護層104e。焊墊104b被鈍化層104c部分暴露，導電柱104d配置在焊墊104b上並與焊墊104b電性連接，且保護層104e覆蓋導電柱104d與鈍化層104c。導電柱104d例如為銅柱(copper pillars)或其他適合的金屬柱。在一些實施例中，保護層104e可為聚苯并噁唑(polybenzoxazole，PBO)、聚亞醯胺(Polyimide，PI)或其他適合的聚合物。在一些其他的實施例中，保護層104e可由無機材料所製成。
在圖3中，可將一個積體電路組件104設置在黏著層AD上。圖中所繪示出的積體電路組件104數量僅是用以舉例說明之用，本發明的實施例不限於此。在一些其他實施例中，可將多個積體電路組件104設置在黏著層AD上，且設置在黏著層AD上的積體電路組件104可排列成陣列(array)。當多個積體電路組件104被設置在黏著層AD上時，可在黏著層AD上設置多組導電柱體102，且各個積體電路組件104分別被其中一組導電柱體102所環繞。積體電路組件104的數量對應於導電柱體102的群組數量。
如圖3所繪示，積體電路組件104的頂表面低於導電柱體102的頂表面。然而，本發明不限於此。在一些其他實施例中，積體電路組件104的頂表面可與導電柱體102的頂表面實質上共平面。
請參照圖4，在黏著層AD上形成絕緣材料106以包覆導電柱體102以及積體電路組件104。在一些實施例中，絕緣材料106例如是模製製程所形成的模製化合物(molding compound)。絕緣材料106包覆積體電路組件104的導電柱體102以及保護層140e。換言之，積體電路組件104的導電柱體102以及保護層104e被絕緣材料106所保護且未顯露於外。在一些實施例中，前述的絕緣材料106例如為環氧化合物(epoxy)或其他合適的材料。
如圖5所示，絕緣材料106與積體電路組件104的保護層104e被研磨直到導電柱104d的頂表面被暴露為止。在絕緣材料106被研磨之後，可在黏著層AD上形成絕緣包封體106'。在上述的研磨期間，部分的保護層104e會一併被研磨而形成保護層104e'。在一些實施例中，在上述絕緣材料106與保護層104e的研磨期間，部分的導電柱104d及部分的導電柱體102會一併被研磨，直到導電柱104d及部分導電柱體102的頂表面被暴露為止。在一些實施例中，絕緣包封體106'可是通過機械研磨製程(mechanical grinding process)及/或化學機械研磨(chemical mechanical polishing, CMP)製程進行研磨。
絕緣包封體106'包覆積體電路組件104的側壁，且導電柱體102會貫穿絕緣包封體106'。換言之，積體電路組件104以及導電柱體102嵌於絕緣包封體106'之中。值得注意的是，導電柱體102的頂表面、保護層104e的頂表面以及導電柱104d的頂表面與絕緣包封體106'的頂表面實質上共平面。
請參照圖6，在絕緣包封體106'以及保護層140e'形成之後，接著，在導電柱體102的頂表面、絕緣包封體106'的頂表面、導電柱104d的頂表面以及保護層140e'的頂表面上形成重佈線路結構108，且重佈線路結構108與積體電路組件104的導電柱104d以及導電柱體102電性連接。如圖6所繪示，重佈線路結構108包括交替堆疊的多個內介電層108a以及多個重佈線導電層108b。重佈線導電層108b與積體電路組件104的導電柱104d以及嵌於絕緣包封體106'中的導電柱體102電性連接。在一些實施例中，導電柱104d的頂表面與導電柱體102的頂表面與重佈線路結構108中最底層的重佈線導電層108b接觸。導電柱104d的頂表面以及導電柱體102的頂表面被最底層的內介電層108a部分地覆蓋。此外，最頂層的重佈線導電層108b包括多個接墊。在一些實施例中，上述的接墊包括多個用以植球(ball placement)的球下金屬圖案108b1及/或至少一用以設置被動元件的接墊(connection pad)108b2。本發明的實施例不限定前述球下金屬圖案108b1及接墊108b2的數量。
請參照圖7，在形成重佈線路結構108之後，在球下金屬圖案108b1上放置多個導電端子110，並且在接墊108b2上設置多個被動元件112。在一些實施例中，導電端子110可通過植球製程而被放置在球下金屬圖案108b1上，且被動元件112可通過焊接製程或迴焊製程而被設置在接墊108b2上。
請參照圖8，在導電端子110與被動元件112被設置在重佈線路結構108上之後，令形成在絕緣包封體106'的底表面上的黏著層AD從剝離層DB上剝離，以使得黏著層AD與載板C分離。在一些實施例中，前述的剝離層DB(例如光熱轉換釋放層)可被紫外光雷射照射以使貼附在絕緣包封體106'的底表面上的黏著層AD能夠從載板C上剝離。如圖8所繪示，接著，黏著層AD會被圖案化而具有多個接觸開口O（即形成圖案化黏著層），以使導電柱體102的第二部分102b被部分暴露。圖案化黏著層AD中的接觸開口O的數量對應於導電柱體102的數量。在一些實施例中，圖案化黏著層AD中的接觸開口O可通過雷射鑽孔製程(laser drilling process)形成。
請參照圖9，在接觸開口O被形成在黏著層AD中之後，可將多個導電端子114放置在接觸開口O中，且導電端子114與導電柱體102的第二部分102b電性連接。如圖9所繪示，在形成導電端子110與導電端子114之後，具有雙面端子設計的積體扇出型封裝體100便初步完成。
圖10為依照本發明一些實施例所繪示的一種堆疊式(POP)封裝體的剖視圖。請參照圖9與圖10，提供另一封裝體200。在一些實施例中，封裝體200例如是記憶體元件或其他合適的積體電路封裝體。封裝體200堆疊於圖9中的積體扇出型封裝體100上，並且通過導電端子114與圖9中的積體扇出型封裝體100電性連接，以完成堆疊式封裝體(POP)的製作。
圖11A至圖11C為依照一些實施例所繪示的不同導電柱體的剖視圖。請參照圖9以及圖11A，在積體扇出型封裝體100中，導電柱體102的第二部分102b以及導電端子114可採用相同或不同材料製作。
在一些實施例中，導電柱體102的第二部分102b以及導電端子114可採用相同材料製作。在一些實施例中，導電柱體102與導電端子114之間的界面(interfaces)可被形成在不同的水平高度上。如圖11A製圖11C所繪示，多種導電柱體102與對應導電端子114之間的接合界面(joint interfaces)的水平高度差異ΔH可大於1微米並且小於10微米。在一些其他實施例中，導電柱體102的第二部分102b以及導電端子114採用不同材料製作，多個位在不同水平高度上的金屬間化合物層116會形成在導電柱體102與導電端子114之間，且導電柱體102與導電端子114之間的金屬間化合物層116的水平高度差異ΔH可大於1微米並且小於10微米。
請參照圖11B，依據設計需求，圖11A中所繪示的導電柱體102可被更動為導電柱體102'。如圖11B所示，各個導電柱體102'分別包括第一部分102a、第二部分102b以及連接在第一部分102a與第二部分102b之間的頸縮部分102c。頸縮部分102c的寬度W3小於第一部分102a的寬度W1以及第二部分102b的寬度W2。導電柱體102'的第一部分102a以及頸縮部分102c嵌於絕緣包封體106'之中，並且被絕緣包封體106'所包覆。導電柱體102'的頸縮部分102c可增進導電柱體102'與絕緣包封體106'之間的黏著性。
請參照圖11C，依據設計需求，圖11A中所繪示的導電柱體102可被更動為導電柱體102''。如圖11C所示，各個導電柱體102''分別包括第一部分102a、第二部分102b以及連接在第一部分102a與第二部分102b之間的二頸縮部分102c。相同的導電柱體102''中的頸縮部分102c彼此連接。頸縮部分102c的寬度W3小於第一部分102a的寬度W1以及第二部分102b的寬度W2。導電柱體102''的頸縮部分102c嵌於絕緣包封體106'之中，並且被絕緣包封體106'所包覆。導電柱體102''的頸縮部分102c可增進導電柱體102''與絕緣包封體106'之間的黏著性。
圖1至圖7以及圖12至13為依照一些實施例所繪示的另一種積體扇出型封裝體的製造流程圖。請參照圖12，在導電端子110與被動元件112被設置在重佈線路結構108(繪示於圖7中)上之後，令形成在絕緣包封體106'的底表面上的黏著層AD從剝離層DB上剝離，以使得黏著層AD與載板C分離。在一些實施例中，前述的剝離層DB(例如光熱轉換釋放層)可被紫外光雷射照射以使貼附在絕緣包封體106'的底表面上的黏著層AD能夠從載板C上剝離。如圖12所示，接著，將黏著層AD完全移除，以使導電柱體102的第二部分102b以及絕緣包封體106'暴露。在一些實施例中，黏著層AD可通過雷射剝離製程(laser lift-off process)形成。
請參照圖13，在黏著層AD被移除之後，可將多個導電端子114放置在導電柱體102的第二部分102b上，且導電端子114與導電柱體102的第二部分102b電性連接。如圖13所繪示，在形成導電端子110與導電端子114之後，具有雙面端子設計的積體扇出型封裝體300便初步完成。
圖14為依照本發明一些實施例所繪示的一種堆疊式封裝體的剖視圖。請參照圖13與圖14，提供另一封裝體400。在一些實施例中，封裝體400例如是記憶體元件或其他合適的積體電路封裝體。封裝體400堆疊於圖13中的積體扇出型封裝體300上，並且通過導電端子114與圖13中的積體扇出型封裝體300電性連接，以完成堆疊式封裝體(POP)的製作。
圖15A至圖15C為依照另一些實施例所繪示的不同導電柱體的剖視圖。請參照圖13以及圖15A，在圖13中所繪示的積體扇出型封裝體200中，導電柱體102的第二部分102b以及導電端子114可採用相同或不同材料製作。在一些實施例中，導電柱體102的第二部分102b以及導電端子114採用相同的材料製作，多個位在不同水平高度上的界面會形成在導電柱體102與導電端子114之間，且導電柱體102與導電端子114之間的界面的水平高度差異ΔH可大於1微米並且小於10微米。在一些其他實施例中，導電柱體102的第二部分102b以及導電端子114採用不同材料製作，多個位在不同水平高度上的金屬間化合物層116會形成在導電柱體102與導電端子114之間，且導電柱體102與導電端子114之間的金屬間化合物層116的水平高度差異ΔH大於1微米並且小於10微米。
請參照圖15B，依據設計需求，圖15A中所繪示的導電柱體102可被更動為導電柱體102'。如圖15B所示，各個導電柱體102'分別包括第一部分102a、第二部分102b以及連接在第一部分102a與第二部分102b之間的頸縮部分102c。頸縮部分102c的寬度W3小於第一部分102a的寬度W1以及第二部分102b的寬度W2。導電柱體102'的第一部分102a以及頸縮部分102c會嵌於絕緣包封體106'之中，並且被絕緣包封體106'所包覆。導電柱體102'的頸縮部分102c可增進導電柱體102'與絕緣包封體106'之間的黏著性。
請參照圖15C，依據設計需求，圖15A中所繪示的導電柱體102可被更動為導電柱體102''。如圖15C所示，各個導電柱體102''分別包括第一部分102a、第二部分102b以及連接在第一部分102a與第二部分102b之間的二頸縮部分102c。相同的導電柱體102''中的頸縮部分102c彼此連接。頸縮部分102c的寬度W3小於第一部分102a的寬度W1以及第二部分102b的寬度W2。導電柱體102''的頸縮部分102c嵌於絕緣包封體106'之中，並且被絕緣包封體106'所包覆。導電柱體102''的頸縮部分102c可增進導電柱體102''與絕緣包封體106'之間的黏著性。
由於上述具有特定高寬比例的導電柱體102、102'以及102''是在被轉移(transfer-bonded)至黏著層AD上之前便已製作完成，因此導電柱體102、102'以及102''的製作不會受到後續封裝製程的限制。此外，由於導電柱體102、102'以及102''並非採用濺鍍、微影、電鍍以及光阻剝除等製程來製造，因此導電柱體102、102'以及102''的製造成本與製造工時可減少。
依據本發明的一些實施例，一種積體扇出型封裝體的製造方法被提出。積體扇出型封裝的製造方法包括下列步驟。將多個導電柱體放置在基板的多個開孔中。提供具有黏著層在其上的載板。將開孔中的導電柱體貼附至黏著層上，以使站立狀態的導電柱體被轉移到載板上。將積體電路組件設置在具有導電柱體貼附在其上的黏著層上。形成絕緣包封體以包覆積體電路組件以及導電柱體。在絕緣包封體、積體電路組件以及導電柱體上形成重佈線路結構，其中重佈線路結構與積體電路組件以及導電柱體電性連接。移除載板。移除(例如圖案化或全面性移除)至少部分的黏著層以將導電柱體的表面暴露。在導電柱體被暴露的表面上形成多個導電端子。
在上述製造方法中，各個導電柱體包括嵌於絕緣包封體中的第一部分以及與第一部分連接的第二部分，第一部分的寬度小於開孔的寬度，且第二部分的寬度大於開孔的寬度。
在上述製造方法中，各個導電柱體更包括連接在第一部分與第二部分之間的頸縮部分，且頸縮部的寬度小於第一部分的寬度以及第二部分的寬度。
在上述製造方法中，第一部分以及頸縮部分嵌於絕緣包封體之中，並被絕緣包封體所包覆，且第二部分被絕緣包封體部分暴露。
在上述製造方法中，在形成導電端子之前，黏著層被圖案化而形成具有多個接觸開口的圖案化黏著層，以使導電柱體的表面被暴露。
在上述製造方法中，在形成導電端子之前，完全移除黏著層。
在上述製造方法中，導電柱體以及導電端子採用不同的材料製作，多個位在不同水平高度上的金屬間化合物層形成在導電柱體與導電端子之間，且導電柱體與導電端子之間的金屬間化合物層的水平高度差異大於1微米並且小於10微米。
在上述製造方法中，導電柱體以及導電端子採用相同的材料製作，且導電柱體與導電端子之間的多個界面的水平高度差異大於1微米並且小於10微米。
依據本發明的其他實施例，一種積體扇出型封裝體包括多個導電柱體、積體電路組件、絕緣包封體、重佈線路結構以及多個導電端子。絕緣包封體包覆積體電路組件以及導電柱體。重配置線路結構配置在絕緣包封體、積體電路組件與導電柱體上。重配置線路結構與積體電路組件以及導電柱體電性連接。導電端子與導電柱體電性連接，其中導電柱體與導電端子之間的多個界面的水平高度差異大於1微米並且小於10微米。
在上述積體扇出型封裝體中，各個導電柱體包括嵌於絕緣包封體中的第一部分以及與第一部分連接的第二部分，且第二部分的寬度大於第一部分的寬度。
在上述積體扇出型封裝體中，各個導電柱體更包括連接在第一部分與第二部分之間的頸縮部分，且頸縮部的寬度小於第一部分的寬度以及第二部分的寬度。
在上述積體扇出型封裝體中，第一部分以及頸縮部分被絕緣包封體所包覆，且第二部分被絕緣包封體部分暴露。
在上述積體扇出型封裝體中，導電柱體以及導電端子採用相同的材料製作。
在上述積體扇出型封裝體中，導電柱體以及導電端子採用不同的材料製作。
上述積體扇出型封裝體更包括：包括多個接觸開口的圖案化黏著層，接觸開口使導電柱體的表面被暴露，其中導電柱體與積體電路組件配置在圖案化黏著層上。
依據本發明的其他實施例，另一種積體扇出型封裝體包括多個導電柱體、積體電路組件、絕緣包封體、重佈線路結構以及多個導電端子。絕緣包封體包覆積體電路組件以及導電柱體。重配置線路結構配置在絕緣包封體、積體電路組件與導電柱體上。重配置線路結構與積體電路組件以及導電柱體電性連接。導電端子與導電柱體電性連接，其中多個位在不同水平高度上的金屬間化合物層形成在導電柱體與導電端子之間，且導電柱體與導電端子之間的金屬間化合物層的水平高度差異大於1微米並且小於10微米。
在上述積體扇出型封裝體中，各個導電柱體包括嵌於絕緣包封體中的第一部分以及與第一部分連接的第二部分，且第二部分的寬度大於第一部分的寬度。
在上述積體扇出型封裝體中，各個導電柱體更包括連接在第一部分與第二部分之間的頸縮部分，且頸縮部的寬度小於第一部分的寬度以及第二部分的寬度。
在上述積體扇出型封裝體中，第一部分以及頸縮部分被絕緣包封體所包覆，且第二部分被絕緣包封體部分暴露。
上述積體扇出型封裝體更包括：包括多個接觸開口的圖案化黏著層，接觸開口使導電柱體的表面被暴露，其中導電柱體與積體電路組件配置在圖案化黏著層上。
以上概述了多個實施例的特徵，使本領域具有通常知識者可更佳了解本發明的態樣。本領域具有通常知識者應理解，其可輕易地使用本發明作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本發明的精神與範疇，且本領域具有通常知識者在不悖離本發明的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
100‧‧‧積體扇出型封裝體 102、102'、102''‧‧‧導電柱體 102a‧‧‧第一部分 102b‧‧‧第二部分 104‧‧‧積體電路組件 104a‧‧‧主動表面 104b‧‧‧焊墊 104c‧‧‧鈍化層 104d‧‧‧導電柱體 104e‧‧‧保護層 106‧‧‧絕緣材料 106'‧‧‧絕緣包封體 108‧‧‧重佈線路結構 108a‧‧‧內介電層 108b‧‧‧重佈線導電層 108b1‧‧‧球下金屬圖案 108b2‧‧‧接墊 110‧‧‧導電端子 112‧‧‧被動元件 114‧‧‧導電端子 200、400‧‧‧封裝體 AP‧‧‧開孔 AD‧‧‧黏著層 C‧‧‧載板 DB‧‧‧剝離層 ΔH‧‧‧水平高度差異 O‧‧‧接觸開口 SUB‧‧‧基板 W、W1、W2‧‧‧寬度
圖1至圖9為依照一些實施例所繪示的一種積體扇出型封裝體的製造流程圖。 圖10為依照本發明一些實施例所繪示的一種堆疊式(Package-On-Packag，POP)封裝體的剖視圖。 圖11A至圖11C為依照一些實施例所繪示的不同導電柱體的剖視圖。 圖12至13為依照一些實施例所繪示的另一種積體扇出型封裝體的製造流程圖。 圖14為依照本發明一些實施例所繪示的一種堆疊式封裝體的剖視圖。 圖15A至圖15C為依照另一些實施例所繪示的不同導電柱體的剖視圖。
102‧‧‧導電柱體
102a‧‧‧第一部分
102b‧‧‧第二部分
AP‧‧‧開孔
AD‧‧‧黏著層
C‧‧‧載板
DB‧‧‧剝離層
SUB‧‧‧基板
W、W1、W2‧‧‧寬度

Claims (1)

  1. 一種積體扇出型封裝體的製造方法，包括： 將多個導電柱體放置在基板的多個開孔中； 提供具有所述黏著層在其上的載板； 將所述開孔中的所述導電柱體貼附至所述黏著層上，以使站立狀態的所述導電柱體被轉移到所述載板上； 將所述積體電路組件設置在具有所述導電柱體貼附在其上的所述黏著層上； 形成絕緣包封體，以包覆所述積體電路組件以及所述導電柱體； 在所述絕緣包封體、所述積體電路組件以及所述導電柱體上形成重佈線路結構，所述重佈線路結構與所述積體電路組件以及所述導電柱體電性連接； 移除所述載板； 移除至少部分的所述黏著層，以將所述導電柱體的表面暴露；以及 在所述導電柱體被暴露的表面上形成多個導電端子。
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