CN107424940A - 集成扇出型封装体的制造方法 - Google Patents

集成扇出型封装体的制造方法 Download PDF

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Publication number
CN107424940A
CN107424940A CN201611024387.XA CN201611024387A CN107424940A CN 107424940 A CN107424940 A CN 107424940A CN 201611024387 A CN201611024387 A CN 201611024387A CN 107424940 A CN107424940 A CN 107424940A
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China
Prior art keywords
conducting post
conducting
post
bonding coat
integrated circuit
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CN201611024387.XA
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English (en)
Inventor
张智浩
廖信宏
蔡豪益
黄见翎
张纬森
江宗宪
郭庭豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN107424940A publication Critical patent/CN107424940A/zh
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Abstract

一种集成扇出型封装的制造方法包括下列步骤。将多个导电柱体放置在衬底的多个开孔中。提供具有黏合层在其上的载板。将开孔中的导电柱体贴附至黏合层上，以使站立状态的导电柱体被转移到载板上。将集成电路组件设置在具有导电柱体贴附在其上的黏合层上。形成绝缘包封体以包覆集成电路组件以及导电柱体。在绝缘包封体、集成电路组件以及导电柱体上形成重布线路结构，重布线路结构与集成电路组件以及导电柱体电性连接。移除载板。移除至少部分的黏合层以将导电柱体的表面暴露。在导电柱体被暴露的表面上形成多个导电端子。

Description

集成扇出型封装体的制造方法
技术领域
本发明的实施例是涉及一种集成扇出型封装体(integrated fan-out package,InFO Package)。
背景技术
由于不同电子器件(例如是晶体管、二极管、电阻、电容等)的集成密度持续地增进，半导体工业经历了快速成长。大部分而言，积集度的增进是来自于最小特征尺寸(feature size)上不断地缩减，这允许更多的较小器件能够被整合到一预定区域内。较小的电子器件会需要比以往体积更小的封装。较小型的半导体器件封装包括有四面扁平封装(quad flat packages，QFPs)、接脚栅格阵列(pin grid array，PGA)封装、球状栅格阵列(ball grid array，BGA)封装等等。
近来，由于集成扇出型封装体的高积集度(compactness)，集成扇出型封装体已逐渐成为主流。如何降低集成扇出型封装体的制造成本已成为重要的议题。
发明内容
依据本发明的一些实施例，一种集成扇出型封装体的制造方法被提出。此集成扇出型封装的制造方法包括下列步骤。将多个导电柱体放置在衬底的多个开孔中。提供具有黏合层在其上的载板。将开孔中的导电柱体贴附至黏合层上，以使站立状态(standingorientation)的导电柱体被转移到载板上。将集成电路组件设置在具有导电柱体贴附在其上的黏合层上。形成绝缘包封体以包覆集成电路组件以及导电柱体。在绝缘包封体、集成电路组件以及导电柱体上形成重布线路结构，其中重布线路结构与集成电路组件以及导电柱体电性连接。移除载板。移除至少部分的黏合层以将导电柱体的表面暴露。在导电柱体被暴露的表面上形成多个导电端子。
附图说明
图1至图9为依照一些实施例所绘示的一种集成扇出型封装体的制造流程图。
图10为依照本发明一些实施例所绘示的一种堆叠式(POP)封装体的剖视图。
图11A至图11C为依照一些实施例所绘示的不同导电柱体的剖视图。
图12至13为依照一些实施例所绘示的另一种集成扇出型封装体的制造流程图。
图14为依照本发明一些实施例所绘示的一种堆叠式封装体的剖视图。
图15A至图15C为依照另一些实施例所绘示的不同导电柱体的剖视图。
附图标记说明：
100：集成扇出型封装体
102、102'、102”：导电柱体
102a：第一部分
102b：第二部分
104：集成电路组件
104a：有源表面
104b：焊垫
104c：钝化层
104d：导电柱
104e：保护层
106：绝缘材料
106'：绝缘包封体
108：重布线路结构
108a：内介电层
108b：重布线导电层
108b1：球下金属图案
108b2：接垫
110：导电端子
112：无源器件
114：导电端子
200、400：封装体
AP：开孔
AD：黏合层
C：载板
DB：剥离层
ΔH：水平高度差异
O：接触开口
SUB：衬底
W、W1、W2：宽度
具体实施方式
以下揭露内容提供用于实施所提供的目标之不同特征的许多不同实施例或实例。以下所描述的构件及配置的具体实例是为了以简化的方式传达本发明为目的。当然，这些仅仅为实例而非用以限制。举例来说，于以下描述中，在第一特征上方或在第一特征上形成第二特征可包括第二特征与第一特征形成为直接接触的实施例，且亦可包括第二特征与第一特征之间可形成有额外特征使得第二特征与第一特征可不直接接触的实施例。此外，本发明在各种实例中可使用相同的组件符号及/或字母来指代相同或类似的部件。组件符号的重复使用是为了简单及清楚起见，且并不表示所欲讨论的各个实施例及/或配置本身之间的关系。
另外，为了易于描述附图中所绘示的一个构件或特征与另一组件或特征的关系，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」及类似术语的空间相对术语。除了附图中所绘示的定向之外，所述空间相对术语意欲涵盖组件在使用或操作时的不同定向。设备可被另外定向(旋转90度或在其他定向)，而本文所用的空间相对术语相应地做出解释。
图1至图9为依照一些实施例所绘示的一种集成扇出型封装体的制造流程图。请参照图1，提供衬底SUB以及载板C，衬底SUB具有呈阵列排列的开孔AP，而载板C具有剥离层DB以及黏合层AD堆叠在其上。在一些实施例中，衬底SUB可为钢板(stencil)，剥离层DB形成在载板C的上表面上，且剥离层DB位在载板C与黏合层AD之间。载板C例如是玻璃衬底，而剥离层DB例如是形成在玻璃衬底上的光热转换释放层(LTHC)。然而，前述剥离层DB与载板C的材质仅为举例之用，本发明的实施例不以此为限。
如图1所示，提供多个预先制造完成的导电柱体102，并且将导电柱体102放置在衬底SUB的开孔AP中。在一些实施例中，这些预先制造完成的导电柱体102(例如铜柱体或其他适合的金属柱体)会被提供至衬底SUB上，且导电柱体102可通过振动机台的振动以使导电柱体102能够被部分地塞入衬底SUB的开孔AP中。通过适当的振动机台的振动控制(例如振动频率及/或振动振幅)，除了衬底SUB会被振动之外，具有实质上相同高度的预先制造完成的导电柱体120可被驱使而在衬底SUB上移动，进而成功地落入衬底SUB的开孔AP中。由于导电柱体102是预先制造完成的，因此具有特定高宽比例的导电柱体102，特别是高宽比例较大(例如高宽比例大于1:3)的导电柱体102可被轻易地制造出来。此外，由于导电柱体102并非采用溅射(sputtering)、光刻(photolithography)、镀覆(plating)以及光刻胶剥除(photoresist stripping)等工艺来制造，因此导电柱体102的制造成本与制造工时可减少。在一些实施例中，预先制造的导电柱体102的高度介于100微米至300微米之间，而预先制造的导电柱体102的宽度介于150微米至300微米之间。在一些其他实施例中，预先制造的导电柱体102的高度介于100微米至500微米之间，而预先制造的导电柱体102的宽度介于150微米至300微米之间。
在一些实施例中，各个导电柱体102包括第一部分102a以及与第一部分102a连接的第二部分102b。导电柱体102的第一部分102a被设计为能够塞进衬底SUB的开孔AP中，而导电柱体102的第二部分102b为凸缘(flange)且仍然位在衬底SUB的开孔AP之外。导电柱体102中第一部分102a的宽度W1小于开孔AP的宽度W，而导电柱体102中第二部分102b的宽度W2大于开孔AP的宽度W。导电柱体102的第二部分102b覆盖衬底SUB的开孔AP并且部分地覆盖住衬底SUB的上表面。导电柱体102的第一部分102a与第二部分102b可采用相同材料或不同材料制作。
在一些实施例中，导电柱体102可采用直行切割工艺(straight cuttingprocess)预先制作完成。在一些其他实施例中，导电柱体102可采用直行切割工艺以及锻头工艺(heading process)预先制作完成。预先制作完成的导电柱体102的特性(例如宽度、高度、形状、电气特性等)可事先被检测。据此，导电柱体102的制造良率可获一定程度的提升。由于导电柱体102是预先制作完成的，制造容忍度(fabrication tolerance)所导致的导电柱体102在高度上的变化可较为轻易地且较有弹性地被控制。在一些实施例中，导电柱体102在水平高度上的变化大于1微米且小于10微米。
请参照图2，将具有剥离层DB以及黏合层AD堆叠在其上的载板C翻覆至衬底SUB上并与衬底SUB接合，以使得导电柱体102的第二部分102b与黏合层AD相黏合。当黏合层AD被压在导电柱体102的第二部分102b上并且与导电柱体102的第二部分102b接合时，导电柱体102的第二部分102b会部分地嵌在或陷入黏合层AD中。
如图2所示，在一些实施例中，当具有剥离层DB以及黏合层AD堆叠在其上的载板C被翻覆至衬底SUB上并与衬底SUB接合时，黏合层AD会与衬底SUB以及导电柱体102的第二部分102b的上表面相黏合。在一些其他实施例中，当具有剥离层DB以及黏合层AD堆叠在其上的载板C被翻覆至导电柱体102的第二部分102b上并与导电柱体102的第二部分102b接合时，黏合层AD实质上不与衬底SUB的上表面接触(即，黏合层AD与衬底SUB的上表面之间未产生黏合性)。
请参照图2与图3，在黏合层AD与导电柱体102的第二部分102b的上表面相黏合后，载板C会被驱动而向上移动，进而将导电柱体102从衬底SUB的开孔AP中拉出。黏合层AD提供足够的黏合力将导电柱体102从衬底SUB的开孔AP中拉出，以使得呈站立状态的导电柱体102能够被转移到黏合层AD上。
请参照图3，在导电柱体102从衬底SUB被转移到黏合层AD上之后，导电柱体102的第二部分102b会嵌在黏合层AD中，其中黏合层AD的厚度介于约3微米至约30微米之间，而第二部分102b的嵌入深度介于约1微米至约10微米之间。在一些实施例中，第二部分102b的嵌入深度的变化可大于1微米并且小于10微米。当在导电柱体102被转移到黏合层AD上并且嵌在黏合层AD中时，导电柱体102的底表面之间的水平高度差异ΔH(绘示在图11A制图11C中的放大部分)可大于1微米并且小于10微米。此处，水平高度差异ΔH定义为导电柱体102的底表面所在的最低水平高度以及最高水平高度的差异。接着，再次将具有剥离层DB、黏合层AD以及导电柱体102堆叠在其上的载板C翻覆以为后续工艺作准备。
如图3所示，将集成电路组件104设置在具有导电柱体102贴附在其上的黏合层AD上。黏合层AD用以作为晶粒贴附薄膜(DAF)。集成电路组件104包括有源表面104a、多个分布在有源表面104a上的焊垫104b、覆盖有源表面104a的钝化层104c、多个导电柱(conductivepillars)104d以及保护层104e。焊垫104b被钝化层104c部分暴露，导电柱104d配置在焊垫104b上并与焊垫104b电性连接，且保护层104e覆盖导电柱104d与钝化层104c。导电柱104d例如为铜柱(copper pillars)或其他适合的金属柱。在一些实施例中，保护层104e可为聚苯并恶唑(polybenzoxazole，PBO)、聚亚酰胺(Polyimide，PI)或其他适合的聚合物。在一些其他的实施例中，保护层104e可由无机材料所制成。
在图3中，可将一个集成电路组件104设置在黏合层AD上。图中所绘示出的集成电路组件104数量仅是用以举例说明之用，本发明的实施例不限在此。在一些其他实施例中，可将多个集成电路组件104设置在黏合层AD上，且设置在黏合层AD上的集成电路组件104可排列成阵列(array)。当多个集成电路组件104被设置在黏合层AD上时，可在黏合层AD上设置多组导电柱体102，且各个集成电路组件104分别被其中一组导电柱体102所环绕。集成电路组件104的数量对应于导电柱体102的群组数量。
如图3所绘示，集成电路组件104的顶表面低于导电柱体102的顶表面。然而，本发明不限于此。在一些其他实施例中，集成电路组件104的顶表面可与导电柱体102的顶表面实质上共平面。
请参照图4，在黏合层AD上形成绝缘材料106以包覆导电柱体102以及集成电路组件104。在一些实施例中，绝缘材料106例如是模制工艺所形成的模制化合物(moldingcompound)。绝缘材料106包覆集成电路组件104的导电柱体102以及保护层140e。换言之，集成电路组件104的导电柱体102以及保护层104e被绝缘材料106所保护且未显露在外。在一些实施例中，前述的绝缘材料106例如为环氧化合物(epoxy)或其他合适的材料。
如图5所示，绝缘材料106与集成电路组件104的保护层104e被研磨直到导电柱104d的顶表面被暴露为止。在绝缘材料106被研磨之后，可在黏合层AD上形成绝缘包封体106'。在上述的研磨期间，部分的保护层104e会一并被研磨而形成保护层104e'。在一些实施例中，在上述绝缘材料106与保护层104e的研磨期间，部分的导电柱104d及部分的导电柱体102会一并被研磨，直到导电柱104d及部分导电柱体102的顶表面被暴露为止。在一些实施例中，绝缘包封体106'可是通过机械研磨工艺(mechanical grinding process)及/或化学机械抛光(chemical mechanical polishing,CMP)工艺进行研磨。
绝缘包封体106'包覆集成电路组件104的侧壁，且导电柱体102会贯穿绝缘包封体106'。换言之，集成电路组件104以及导电柱体102嵌在绝缘包封体106'之中。值得注意的是，导电柱体102的顶表面、保护层104e的顶表面以及导电柱104d的顶表面与绝缘包封体106'的顶表面实质上共平面。
请参照图6，在绝缘包封体106'以及保护层140e'形成之后，接着，在导电柱体102的顶表面、绝缘包封体106'的顶表面、导电柱104d的顶表面以及保护层140e'的顶表面上形成重布线路结构108，且重布线路结构108与集成电路组件104的导电柱104d以及导电柱体102电性连接。如图6所绘示，重布线路结构108包括交替堆叠的多个内介电层108a以及多个重布线导电层108b。重布线导电层108b与集成电路组件104的导电柱104d以及嵌在绝缘包封体106'中的导电柱体102电性连接。在一些实施例中，导电柱104d的顶表面与导电柱体102的顶表面与重布线路结构108中最底层的重布线导电层108b接触。导电柱104d的顶表面以及导电柱体102的顶表面被最底层的内介电层108a部分地覆盖。此外，最顶层的重布线导电层108b包括多个接垫。在一些实施例中，上述的接垫包括多个用以植球(ballplacement)的球下金属图案108b1及/或至少一用以设置无源器件的接垫(connectionpad)108b2。本发明的实施例不限定前述球下金属图案108b1及接垫108b2的数量。
请参照图7，在形成重布线路结构108之后，在球下金属图案108b1上放置多个导电端子110，并且在接垫108b2上设置多个无源器件112。在一些实施例中，导电端子110可通过植球工艺而被放置在球下金属图案108b1上，且无源器件112可通过焊接工艺(solderingprocess)或回焊工艺(reflow process)而被设置在接垫108b2上。
请参照图8，在导电端子110与无源器件112被设置在重布线路结构108上之后，令形成在绝缘包封体106'的底表面上的黏合层AD从剥离层DB上剥离，以使得黏合层AD与载板C分离。在一些实施例中，前述的剥离层DB(例如光热转换释放层)可被紫外光激光照射以使贴附在绝缘包封体106'的底表面上的黏合层AD能够从载板C上剥离。如图8所绘示，接着，黏合层AD会被图案化而具有多个接触开口O(即形成图案化黏合层)，以使导电柱体102的第二部分102b被部分暴露。图案化黏合层AD中的接触开口O的数量对应于导电柱体102的数量。在一些实施例中，图案化黏合层AD中的接触开口O可通过激光钻孔工艺(laser drillingprocess)形成。
请参照图9，在接触开口O被形成在黏合层AD中之后，可将多个导电端子114放置在接触开口O中，且导电端子114与导电柱体102的第二部分102b电性连接。如图9所绘示，在形成导电端子110与导电端子114之后，具有双面端子设计的集成扇出型封装体100便初步完成。
图10为依照本发明一些实施例所绘示的一种堆叠式(POP)封装体的剖视图。请参照图9与图10，提供另一封装体200。在一些实施例中，封装体200例如是存储器器件(memorydevice)或其他合适的集成电路封装体。封装体200堆叠在图9中的集成扇出型封装体100上，并且通过导电端子114与图9中的集成扇出型封装体100电性连接，以完成堆叠式封装体(POP)的制作。
图11A至图11C为依照一些实施例所绘示的不同导电柱体的剖视图。请参照图9以及图11A，在集成扇出型封装体100中，导电柱体102的第二部分102b以及导电端子114可采用相同或不同材料制作。
在一些实施例中，导电柱体102的第二部分102b以及导电端子114可采用相同材料制作。在一些实施例中，导电柱体102与导电端子114之间的界面(interfaces)可被形成在不同的水平高度上。如图11A制图11C所绘示，多种导电柱体102与对应导电端子114之间的接合界面(joint interfaces)的水平高度差异ΔH可大于1微米并且小于10微米。在一些其他实施例中，导电柱体102的第二部分102b以及导电端子114采用不同材料制作，多个位在不同水平高度上的金属间化合物层116会形成在导电柱体102与导电端子114之间，且导电柱体102与导电端子114之间的金属间化合物层116的水平高度差异ΔH可大于1微米并且小于10微米。
请参照图11B，依据设计需求，图11A中所绘示的导电柱体102可被更动为导电柱体102'。如图11B所示，各个导电柱体102'分别包括第一部分102a、第二部分102b以及连接在第一部分102a与第二部分102b之间的颈缩部分102c。颈缩部分102c的宽度W3小于第一部分102a的宽度W1以及第二部分102b的宽度W2。导电柱体102'的第一部分102a以及颈缩部分102c嵌在绝缘包封体106'之中，并且被绝缘包封体106'所包覆。导电柱体102'的颈缩部分102c可增进导电柱体102'与绝缘包封体106'之间的黏合性。
请参照图11C，依据设计需求，图11A中所绘示的导电柱体102可被更动为导电柱体102”。如图11C所示，各个导电柱体102”分别包括第一部分102a、第二部分102b以及连接在第一部分102a与第二部分102b之间的二颈缩部分102c。相同的导电柱体102”中的颈缩部分102c彼此连接。颈缩部分102c的宽度W3小于第一部分102a的宽度W1以及第二部分102b的宽度W2。导电柱体102”的颈缩部分102c嵌在绝缘包封体106'之中，并且被绝缘包封体106'所包覆。导电柱体102”的颈缩部分102c可增进导电柱体102”与绝缘包封体106'之间的黏合性。
图1至图7以及图12至13为依照一些实施例所绘示的另一种集成扇出型封装体的制造流程图。请参照图12，在导电端子110与无源器件112被设置在重布线路结构108(绘示在图7中)上之后，令形成在绝缘包封体106'的底表面上的黏合层AD从剥离层DB上剥离，以使得黏合层AD与载板C分离。在一些实施例中，前述的剥离层DB(例如光热转换释放层)可被紫外光激光照射以使贴附在绝缘包封体106'的底表面上的黏合层AD能够从载板C上剥离。如图12所示，接着，将黏合层AD完全移除，以使导电柱体102的第二部分102b以及绝缘包封体106'暴露。在一些实施例中，黏合层AD可通过激光剥离工艺(laser lift-off process)形成。
请参照图13，在黏合层AD被移除之后，可将多个导电端子114放置在导电柱体102的第二部分102b上，且导电端子114与导电柱体102的第二部分102b电性连接。如图13所绘示，在形成导电端子110与导电端子114之后，具有双面端子设计的集成扇出型封装体300便初步完成。
图14为依照本发明一些实施例所绘示的一种堆叠式封装体的剖视图。请参照图13与图14，提供另一封装体400。在一些实施例中，封装体400例如是存储器器件或其他合适的集成电路封装体。封装体400堆叠在图13中的集成扇出型封装体300上，并且通过导电端子114与图13中的集成扇出型封装体300电性连接，以完成堆叠式封装体(POP)的制作。
图15A至图15C为依照另一些实施例所绘示的不同导电柱体的剖视图。请参照图13以及图15A，在图13中所绘示的集成扇出型封装体200中，导电柱体102的第二部分102b以及导电端子114可采用相同或不同材料制作。在一些实施例中，导电柱体102的第二部分102b以及导电端子114采用相同的材料制作，多个位在不同水平高度上的界面会形成在导电柱体102与导电端子114之间，且导电柱体102与导电端子114之间的界面的水平高度差异ΔH可大于1微米并且小于10微米。在一些其他实施例中，导电柱体102的第二部分102b以及导电端子114采用不同材料制作，多个位在不同水平高度上的金属间化合物层116会形成在导电柱体102与导电端子114之间，且导电柱体102与导电端子114之间的金属间化合物层116的水平高度差异ΔH大于1微米并且小于10微米。
请参照图15B，依据设计需求，图15A中所绘示的导电柱体102可被更动为导电柱体102'。如图15B所示，各个导电柱体102'分别包括第一部分102a、第二部分102b以及连接在第一部分102a与第二部分102b之间的颈缩部分102c。颈缩部分102c的宽度W3小于第一部分102a的宽度W1以及第二部分102b的宽度W2。导电柱体102'的第一部分102a以及颈缩部分102c会嵌在绝缘包封体106'之中，并且被绝缘包封体106'所包覆。导电柱体102'的颈缩部分102c可增进导电柱体102'与绝缘包封体106'之间的黏合性。
请参照图15C，依据设计需求，图15A中所绘示的导电柱体102可被更动为导电柱体102”。如图15C所示，各个导电柱体102”分别包括第一部分102a、第二部分102b以及连接在第一部分102a与第二部分102b之间的二颈缩部分102c。相同的导电柱体102”中的颈缩部分102c彼此连接。颈缩部分102c的宽度W3小于第一部分102a的宽度W1以及第二部分102b的宽度W2。导电柱体102”的颈缩部分102c嵌在绝缘包封体106'之中，并且被绝缘包封体106'所包覆。导电柱体102”的颈缩部分102c可增进导电柱体102”与绝缘包封体106'之间的黏合性。
由于上述具有特定高宽比例的导电柱体102、102'以及102”是在被转移(transfer-bonded)至黏合层AD上之前便已制作完成，因此导电柱体102、102'以及102”的制作不会受到后续封装工艺的限制。此外，由于导电柱体102、102'以及102”并非采用溅射、光刻、镀覆以及光刻胶剥除等工艺来制造，因此导电柱体102、102'以及102”的制造成本与制造工时可减少。
依据本发明的一些实施例，一种集成扇出型封装体的制造方法被提出。集成扇出型封装的制造方法包括下列步骤。将多个导电柱体放置在衬底的多个开孔中。提供具有黏合层在其上的载板。将开孔中的导电柱体贴附至黏合层上，以使站立状态的导电柱体被转移到载板上。将集成电路组件设置在具有导电柱体贴附在其上的黏合层上。形成绝缘包封体以包覆集成电路组件以及导电柱体。在绝缘包封体、集成电路组件以及导电柱体上形成重布线路结构，其中重布线路结构与集成电路组件以及导电柱体电性连接。移除载板。移除(例如图案化或全面性移除)至少部分的黏合层以将导电柱体的表面暴露。在导电柱体被暴露的表面上形成多个导电端子。
在上述制造方法中，各个导电柱体包括嵌在绝缘包封体中的第一部分以及与第一部分连接的第二部分，第一部分的宽度小于开孔的宽度，且第二部分的宽度大于开孔的宽度。
在上述制造方法中，各个导电柱体更包括连接在第一部分与第二部分之间的颈缩部分，且颈缩部的宽度小于第一部分的宽度以及第二部分的宽度。
在上述制造方法中，第一部分以及颈缩部分嵌在绝缘包封体之中，并被绝缘包封体所包覆，且第二部分被绝缘包封体部分暴露。
在上述制造方法中，在形成导电端子之前，黏合层被图案化而形成具有多个接触开口的图案化黏合层，以使导电柱体的表面被暴露。
在上述制造方法中，在形成导电端子之前，完全移除黏合层。
在上述制造方法中，导电柱体以及导电端子采用不同的材料制作，多个位在不同水平高度上的金属间化合物层形成在导电柱体与导电端子之间，且导电柱体与导电端子之间的金属间化合物层的水平高度差异大于1微米并且小于10微米。
在上述制造方法中，导电柱体以及导电端子采用相同的材料制作，且导电柱体与导电端子之间的多个界面的水平高度差异大于1微米并且小于10微米。
依据本发明的其他实施例，一种集成扇出型封装体包括多个导电柱体、集成电路组件、绝缘包封体、重布线路结构以及多个导电端子。绝缘包封体包覆集成电路组件以及导电柱体。重配置线路结构配置在绝缘包封体、集成电路组件与导电柱体上。重配置线路结构与集成电路组件以及导电柱体电性连接。导电端子与导电柱体电性连接，其中导电柱体与导电端子之间的多个界面的水平高度差异大于1微米并且小于10微米。
在上述集成扇出型封装体中，各个导电柱体包括嵌在绝缘包封体中的第一部分以及与第一部分连接的第二部分，且第二部分的宽度大于第一部分的宽度。
在上述集成扇出型封装体中，各个导电柱体更包括连接在第一部分与第二部分之间的颈缩部分，且颈缩部的宽度小于第一部分的宽度以及第二部分的宽度。
在上述集成扇出型封装体中，第一部分以及颈缩部分被绝缘包封体所包覆，且第二部分被绝缘包封体部分暴露。
在上述集成扇出型封装体中，导电柱体以及导电端子采用相同的材料制作。
在上述集成扇出型封装体中，导电柱体以及导电端子采用不同的材料制作。
上述集成扇出型封装体更包括：包括多个接触开口的图案化黏合层，接触开口使导电柱体的表面被暴露，其中导电柱体与集成电路组件配置在图案化黏合层上。
依据本发明的其他实施例，另一种集成扇出型封装体包括多个导电柱体、集成电路组件、绝缘包封体、重布线路结构以及多个导电端子。绝缘包封体包覆集成电路组件以及导电柱体。重配置线路结构配置在绝缘包封体、集成电路组件与导电柱体上。重配置线路结构与集成电路组件以及导电柱体电性连接。导电端子与导电柱体电性连接，其中多个位在不同水平高度上的金属间化合物层形成在导电柱体与导电端子之间，且导电柱体与导电端子之间的金属间化合物层的水平高度差异大于1微米并且小于10微米。
在上述集成扇出型封装体中，各个导电柱体包括嵌在绝缘包封体中的第一部分以及与第一部分连接的第二部分，且第二部分的宽度大于第一部分的宽度。
在上述集成扇出型封装体中，各个导电柱体更包括连接在第一部分与第二部分之间的颈缩部分，且颈缩部的宽度小于第一部分的宽度以及第二部分的宽度。
在上述集成扇出型封装体中，第一部分以及颈缩部分被绝缘包封体所包覆，且第二部分被绝缘包封体部分暴露。
上述集成扇出型封装体更包括：包括多个接触开口的图案化黏合层，接触开口使导电柱体的表面被暴露，其中导电柱体与集成电路组件配置在图案化黏合层上。
最后应说明的是：以上各实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述各实施例对本发明进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (1)

1.一种集成扇出型封装体的制造方法，其特征在于，包括：
将多个导电柱体放置在衬底的多个开孔中；
提供具有所述黏合层在其上的载板；
将所述开孔中的所述导电柱体贴附至所述黏合层上，以使站立状态的所述导电柱体被转移到所述载板上；
将所述集成电路组件设置在具有所述导电柱体贴附在其上的所述黏合层上；
形成绝缘包封体，以包覆所述集成电路组件以及所述导电柱体；
在所述绝缘包封体、所述集成电路组件以及所述导电柱体上形成重布线路结构，所述重布线路结构与所述集成电路组件以及所述导电柱体电性连接；
移除所述载板；
移除至少部分的所述黏合层，以将所述导电柱体的表面暴露；以及
在所述导电柱体被暴露的表面上形成多个导电端子。
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