TWI671861B - 半導體封裝結構及其製作方法 - Google Patents

半導體封裝結構及其製作方法 Download PDF

Info

Publication number
TWI671861B
TWI671861B TW107107834A TW107107834A TWI671861B TW I671861 B TWI671861 B TW I671861B TW 107107834 A TW107107834 A TW 107107834A TW 107107834 A TW107107834 A TW 107107834A TW I671861 B TWI671861 B TW I671861B
Authority
TW
Taiwan
Prior art keywords
substrate
layer
connection
chip
supporting
Prior art date
Application number
TW107107834A
Other languages
English (en)
Other versions
TW201939678A (zh
Inventor
許詩濱
余俊賢
蔡憲銘
Original Assignee
恆勁科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 恆勁科技股份有限公司 filed Critical 恆勁科技股份有限公司
Priority to TW107107834A priority Critical patent/TWI671861B/zh
Priority to US16/291,065 priority patent/US20190279925A1/en
Application granted granted Critical
Publication of TWI671861B publication Critical patent/TWI671861B/zh
Publication of TW201939678A publication Critical patent/TW201939678A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

半導體封裝結構包括晶片與具有置晶凹槽之基板。基板包括基底介電層與複數個支撐介電層，基底介電層堆疊在下作為置晶凹槽之底部，支撐介電層堆疊在上作為置晶凹槽之側壁。基板另包括基底連線層與支撐連線層。基底連線層位於基底介電層內部，包括第一連接點與底層連接點，分別暴露於置晶凹槽底部與基底介電層底面。晶片係以主動面向下設置於置晶凹槽中，並電性連接第一連接點。本發明利用增層互連技術與基板凹槽技術，在基板凹槽底部製作覆晶連結用接點，將晶片埋入基板凹槽內，降低整體系統封裝高度，並提高整體結構可靠度。

Description

半導體封裝結構及其製作方法
本發明是有關於一種覆晶封裝用基板結構，且特別是有關於一種降低整體封裝高度之立體式多晶片封裝結構及其製作方法。
晶片封裝主要提供積體電路(IC)保護、散熱、電路導通等功能。承載基板是介於積體電路晶片及印刷電路板(printed circuit board，PCB)之間的結構，主要功能為承載晶片，做為載體之用，並以基板線路連結晶片與印刷電路板之間訊號連結。隨晶圓製程技術演進，積體電路密度、傳輸速率及降低訊號干擾等效能需求提高，使得積體電路晶片封裝的技術要求逐漸增加。
晶片封裝引腳數需求不斷增加，封裝技術也由導線架與打線封裝(wire bound，WB)逐步發展至覆晶封裝(flip chip package)。打線焊接是利用導線連接晶片上之電性連接點(electric connection pad)與基板。覆晶封裝是在晶片連接點上長凸塊(bump)，然後翻轉晶片，使凸塊與基板直接連接。相較於打線僅能連接於晶片邊緣，覆晶封裝可利用晶片的整個表面製作連接點，大幅增加晶片引腳數，且亦可與打線封裝併用，進行立體式封裝。
對於習知覆晶與打線的複合封裝技術，覆晶基板採用厚基材為核心去製作線路，且封裝需要包含打線高度，因此導致整體封裝高度較厚，不適合輕薄型應用。再者，由於基板偏厚，且基板材料導熱係數低，因此散熱效果較差。此外，由於覆晶接點需要設計防銲開口與襯墊，導致接點間距無法縮小，影響輸入 輸出連接點數量難以提升。
為此，未來的封裝趨勢係力圖輕薄的系統式封裝。在行動應用世界中，堆疊的封裝體之高度係為應用發展的重要因素。降低封裝體的高度可容許其配合在較薄的行動裝置中或行動裝置內的新位置。堆疊式封裝(package on package，PoP)堆疊係為一種重要的系統級封裝(system in package，SiP)技術。堆疊式封裝之上下基板以大錫球作為支撐與電性連接。
第1圖繪示的是習知堆疊式封裝結構900的剖視示意圖。堆疊式封裝結構900包括一第一基板934、一線路層913、一第一封膠層915、嵌入一第一封膠層915內之一第一晶片910、堆疊於第一封膠層915上方之一第二基板935、安裝至第二基板935上之一第二晶片920、安裝至第二晶片920上之一第三晶片930與一第二封膠層925。第一封膠層915與第二封膠層925分別位於第一基板934與第二基板935上。線路層913形成於第一基板934與第二基板935中，包括傳導線及貫孔。第二基板935需藉由錫球926而電連接至線路層913。
堆疊式封裝之缺點在於，由於錫球926必須高於下方第一晶片910厚度，因此需要使用大直徑錫球926。錫球926所增加之高度約為250微米(micrometer，μm)，而錫球926與錫球926之間的間距大約需要500~600微米，這會導致第一基板934與第二基板935所需面積極大，且需要設計額外之層間對位補償用襯墊作為錫球926之接點，容易產生封裝翹曲效應(warpage)。基板彎翹會嚴重影響第一基板934與第二基板935間的錫球926銲接，造成外側錫球926脫銲短路。除了基板面積因素，堆疊式封裝之封裝流程繁雜，且需經過多次回銲，亦會導致基板彎翹變形脫銲。此外，由於堆疊式封裝需要使用兩片基板(第一基板934與第二基板935)來輸入輸出第一晶片910與第二晶片920之訊號，且用到打線封裝，因此整體封裝高度仍然較高。
另有一種整合型扇型封裝(integrated fan-out package，InFo封裝)之堆疊式封裝技術，上下封裝體之間以厚銅 柱作為支撐與電性連接。InFo堆疊式封裝技術的缺點在於，為了使用晶圓級製程技術在封裝晶片周圍形成高度高於晶片的厚銅柱，必須要反覆進行數量繁多的銅電鍍加工製程，製程時間加長，控制困難。由於InFo封裝技術門檻高且製作成本昂貴，因此技術普及較難。
因此，本發明之目的係提供一種半導體封裝結構，其於晶片側邊外設置佈線結構，同時提供支撐與配線雙功能，可降低整體系統封裝高度，並提高整體結構可靠度。
根據上述目的，本發明提供一種半導體封裝結構，包括一第一晶片與一基板。第一晶片具有一第一主動面與相反側之一第一背面。基板包括一基底介電層、一基底連線層、複數個支撐介電層與複數個支撐連線層。基底介電層具有一基底頂面與相反側之一基底底面。基底連線層位於基底介電層內部。基底連線層包括複數個第一連接點與複數個底層連接點，分別暴露於基底頂面與基底底面。支撐介電層與第一晶片均設置於基底頂面。支撐介電層與基底介電層配合形成一置晶凹槽。第一晶片係以第一主動面向下設置於置晶凹槽中，且第一主動面電性連接第一連接點。支撐連線層位於支撐介電層內部。支撐連線層包括複數個第二連接點暴露於支撐頂面。
於本發明之一實施例中，半導體封裝結構另包括一第二晶片，第二晶片具有一第二主動面與一相對之第二背面，其中第二晶片係位於支撐介電層之支撐頂面與第一晶片之上，且第二晶片係以第二主動面向下覆晶連接第二連接點。
根據上述目的，本發明提供一種製作半導體封裝結構之方法。首先，提供一承載板。再者，於承載板上形成基底連線層與基底介電層。基底連線層位於基底介電層內部。基底介電層之一基底頂面具有一置晶預定區。接著，於置晶預定區表面提供一離型膜。其後，於基底介電層上形成複數個支撐介電層與複數個支撐連線層。支撐介電層位於基底介電層之基底頂面。支撐 連線層位於支撐介電層內部。部分之支撐連線層暴露於支撐介電層之支撐頂面，作為複數個第二連接點。之後，對置晶預定區進行一切割製程，以去除置晶預定區上方之支撐介電層與離型膜。暴露出置晶預定區。支撐介電層與基底介電層配合形成一置晶凹槽。接著，去除承載板。部分之基底連線層暴露於基底介電層之基底頂面，作為複數個第一連接點。部分之基底連線層暴露於基底介電層之一基底底面，作為複數個底層連接點。
於本發明之一實施例中，本發明更包括：在進行切割製程之前，於支撐介電層之支撐頂面上覆蓋一保護膜，保護膜用以在切割製程的過程中保護第二連接點。之後，對置晶預定區內之基底連線層進行一蝕刻製程，以暴露出第一連接點。接著，再去除保護膜。
綜合上述，本發明係為一種覆晶封裝用基板結構，利用增層互連技術，搭配後開蓋式基板凹槽製作技術，在基板凹槽底部製作覆晶連結用接點，將晶片局部或全部埋入基板內，再於其上疊合其他晶片，降低整體系統封裝高度，並提高整體結構可靠度。
10‧‧‧基板
13a、13b‧‧‧基底介電層
14a、14b‧‧‧基底連線層
21‧‧‧第一晶片
22‧‧‧第二晶片
23‧‧‧第三晶片
m0‧‧‧置晶預定區
31‧‧‧置晶凹槽
35‧‧‧佈線層
37‧‧‧導電柱
38‧‧‧貫孔
42‧‧‧離型膜
44‧‧‧保護膜
46‧‧‧第一凸塊
47‧‧‧第二凸塊
48‧‧‧第三凸塊
50‧‧‧印刷電路板
53a、53b‧‧‧支撐介電層
54a、54b‧‧‧支撐連線層
62‧‧‧緩衝層
64‧‧‧封裝層
100、200、300‧‧‧半導體封裝結構
131‧‧‧基底底面
132‧‧‧基底頂面
141‧‧‧第一連接點
142‧‧‧底層連接點
211‧‧‧第一主動面
212‧‧‧第一背面
220‧‧‧承載板
221‧‧‧第二主動面
222‧‧‧第二背面
231‧‧‧第三主動面
232‧‧‧第三背面
532‧‧‧支撐頂面
542‧‧‧第二連接點
900‧‧‧習知堆疊式封裝結構
910‧‧‧第一晶片
913‧‧‧線路層
915‧‧‧第一封膠層
920‧‧‧第二晶片
925‧‧‧第二封膠層
926‧‧‧錫球
930‧‧‧第三晶片
934‧‧‧第一基板
935‧‧‧第二基板
第1圖繪示的是習知堆疊式封裝結構的剖視示意圖。
第2圖繪示的是本發明第一實施例之半導體封裝結構的剖視示意圖。
第3圖繪示的是本發明第一實施例之半導體封裝結構的俯視示意圖。
第4圖繪示的是本發明第一實施例之半導體封裝結構的仰視示意圖。
第5圖繪示的是本發明第二實施例之半導體封裝結構的剖視示意圖。
第6圖繪示的是本發明第三實施例之半導體封裝結構的剖視示意圖。
第7圖至第18圖係表示本發明製作半導體封裝結構之方法的剖視示意圖。
關於本發明之優點與精神可以藉由以下發明詳述及所附圖式得到進一步的瞭解。本發明較佳實施例之製造及使用係詳細說明如下。必須瞭解的是本發明提供了許多可應用的創新概念，在特定的背景技術之下可以做廣泛的實施。此特定的實施例僅以特定的方式表示，以製造及使用本發明，但並非限制本發明的範圍。
第2圖至第4圖分別是本發明第一實施例之半導體封裝結構100的剖視示意圖、俯視示意圖與仰視示意圖。如第2圖至第4圖所示，本實施例之半導體封裝結構100為一種具有置晶凹槽31之覆晶封裝用基板10。基板10由下而上依序包括兩個基底介電層13a、13b與兩個支撐介電層53a、53b，而支撐介電層53a、53b與基底介電層13a、13b配合形成置晶凹槽31。更具體地說，基底介電層13a、13b堆疊在下作為置晶凹槽31之底部，支撐介電層53a、53b堆疊在上作為置晶凹槽31之側壁。基底介電層13a、13b具有一基底頂面132與相反側之一基底底面131，而支撐介電層53a、53b具有一支撐頂面532。亦即，支撐介電層53a、53b係設置於基底介電層13a、13b之基底頂面132上。
基底介電層13a、13b與支撐介電層53a、53b之材質可以為高填料含量介電材(high filler content dielectric material)，例如為鑄模化合物(molding compound)，其係以環氧樹脂(epoxy)為主要基質，其佔鑄模化合物之整體比例約為8%~12%，並摻雜佔整體比例約70%~90%的填充劑而形成。其中，填充劑可以包括二氧化矽及氧化鋁，以達到增加機械強度、降低線性熱膨脹係數、增加熱傳導、增加阻水及減少溢膠的功效。於其他實施例中，基底介電層13a、13b可以是單層結構也可以是多層結構，層數不限。
基板10另包括兩個基底連線層14a、14b與兩個支撐 連線層54a、54b。基底連線層14a、14b位於基底介電層13a、13b內部，支撐連線層54a、54b位於支撐介電層53a、53b內部。兩層基底連線層14a、14b由下而上依序包括複數個底層連接點142、一佈線層35與複數個導電柱37。個別來說，底層之基底連線層14a包括底層連接點142，位於底層基底介電層13a內，而上層之基底連線層14b包括佈線層35與導電柱37，位於上層基底介電層13b內。其中暴露於置晶凹槽31底部(基底頂面132)之導電柱37係作為第一連接點141，而底層連接點142係暴露於基底底面131。
各支撐連線層54a、54b由下而上依序包括一佈線層35與複數個導電柱37，其中暴露於支撐頂面532之導電柱37係作為第二連接點542。亦即，兩層支撐連線層54a、54b由下而上依序包括一佈線層35、一層導電柱37、另一佈線層35、另一層導電柱37與第二連接點542，其中下層支撐連線層54a之佈線層35係電性連接上層基底連線層14b之導電柱37。
佈線層35可作為線路重佈層(redistribution layer，RDL)，用以調整輸入輸出連接點的位置，使各晶片得以藉此向外扇出(fan out)作電性延伸，導電柱37用以電性連接佈線層35。佈線層35與導電柱37之材料例如係銅金屬。由於佈線層35重新分佈了連接點之位置，支撐連線層54a、54b投影於支撐頂面532之圖案會異於第二連接點542投影於支撐頂面532之圖案。進一步說明，由整體俯視觀之，支撐連線層54a、54b所構成之圖案係異於第二連接點542所構成之圖案。
置晶凹槽31內之第一連接點141可供下層晶片覆晶連接用，支撐頂面532上之第二連接點542可供其他晶片覆晶連接或打線連接用，而基底底面131上之底層連接點142可供電性連接至印刷電路板(printed circuit board，PCB)。其中，第一連接點141、第二連接點542與底層連接點142可依晶片設計與封裝需求製作為高於或低於周圍之介電層表面，若高於介電層表面則利於銅柱對接，若低於介電層表面則利於錫球焊接。
本發明前述之基板10進行晶片連接(die bond)製 程、封裝(molding)製程與印刷電路板製程後之結構可參閱第5圖與第6圖。第5圖與第6圖繪示的分別是本發明第二與第三實施例之半導體封裝結構200、300的剖視示意圖。其中與第一實施例之主要不同在於，第二實施例之半導體封裝結構200包括兩個晶片21、22，而第三實施例之半導體封裝結構300包括三個晶片21、22、23。
如第5圖所示，半導體封裝結構200包括一基板10、一第一晶片21、一第二晶片22、緩衝層62、複數個第一凸塊46、複數個第二凸塊47與一封裝層64。第一晶片21具有一第一主動面211與相反側之一第一背面212。第一晶片21係以第一主動面211向下之方式，全部埋入於基板10之置晶凹槽31中。第一凸塊46連接第一晶片21與第一連接點141，作為第一主動面211與第一連接點141間之覆晶電性連接。
第二晶片22具有一第二主動面221與相對之一第二背面222，其中第二晶片22係位於支撐介電層53b之支撐頂面532與第一晶片21之上。第二晶片22係以第二主動面221向下之方式，設置於第一晶片21與緩衝層62上，且第二凸塊47連接第二晶片22與第二連接點542，作為第二主動面221與第二連接點542間之覆晶電性連接。其中第一晶片21與第二晶片22可為任何晶片、晶粒、其他主動元件或被動元件，諸如功率管理積體電路(PMIC)或記憶體組件，諸如高帶寬記憶體(HBM)、積體電路晶片或發光二極體晶片。
緩衝層62位於第一晶片21與第二晶片22之間，作為第一晶片21與第二晶片22間之緩衝，保護第一晶片21與第二晶片22。緩衝層62之材質可包含彈性材料，例如為矽膠膜或黏著膠，但不限於此。封裝層64覆蓋基板10、第一晶片21、第二晶片22、緩衝層62、第一凸塊46與第二凸塊47。封裝層64之材質亦可為高填料含量介電材，以達到增加機械強度、降低線性熱膨脹係數、增加熱傳導、增加阻水及減少溢膠的功效。
半導體封裝結構200可選擇性地另包括一印刷電路 板50與複數個第三凸塊48。第三凸塊48位於基板10的基底底面131上，作為對外連接端，使各半導體封裝結構200可進一步連接在印刷電路板50上。
於此實施例中，第一晶片21之第一背面212與支撐連線層54a、54b之支撐頂面532大致上等高，但不限於此。第一晶片21之第一背面212可略高於支撐介電層53b之支撐頂面532，其高度差距較佳小於一般錫球之直徑。而於其他實施例中，第一晶片21之第一背面212亦可小於支撐介電層53b之支撐頂面532。當第一晶片21與第二晶片22之間距較大時，本發明可以省略緩衝層62，而封裝層64會填充第一晶片21與第二晶片22之間作為緩衝結構。
與第二實施例之主要不同在於，第三實施例之半導體封裝結構300另包括一個第三晶片23。如第6圖所示，半導體封裝結構300另包括一第三晶片23。第三晶片23具有一第三主動面231與相對之一第三背面232，其中第三晶片23係以第三主動面231向上之方式設置於第二晶片22之上，且第三晶片23係以打線連接第二連接點542。
根據上述覆晶封裝用基板10之結構，置晶凹槽31可以將下層第一晶片21局部或全部埋入基板10內，再於下層第一晶片21上疊合第二與第三晶片22、23，內嵌式設計可薄化整體系統封裝高度。再者，由於本發明利用單一基板10同時提供複數個晶片21、22、23之支撐與配線雙功能，因此不再需要使用厚銅柱或大錫球(直徑接近或大於晶片厚度之錫球)來做支撐，故也不需要額外之層間對位補償用襯墊，可以大幅縮小接點間距。
此外，由於內嵌第一晶片21更貼近基板10之基底底面131，因此可以縮短內部連線之電路設計長度，提高散熱效率，進而改善系統式封裝常見之發熱問題。另外，由於本發明基板10之介電材料包括高填料含量環氧樹脂，取代傳統印刷電路板使用之防銲樹酯材料，因此可進一步提高熱傳導率與封裝材料結合率，增加產品可靠度。又，由於本發明利用模封銅導線增層技術製作基板10，故於晶座下方與非晶片區槽壁均可自由設計佈線， 總層數與各層厚度也可依實際需求自由調整，可提高電路設計自由度並縮減整體封裝尺寸。
第7圖至第18圖係表示本發明製作半導體封裝結構100之方法的剖視示意圖。半導體封裝結構100之製造方法大致上包含在承載板220上形成底層連接點142(第7圖)、進行底層基底介電層13a模封與研磨製程(第8圖)、半加成法形成上層基底連線層14b(第9圖)、進行上層基底介電層13b模封與研磨製程(第10圖)、半加成法形成下層支撐連線層54a之佈線層35(第11圖)、貼合離型膜42(第12圖)、進行下層支撐介電層53a模封與鑽孔製程(第13圖)、形成導電柱37與上層支撐連線層54b(第14圖)、進行上層支撐介電層53b模封與研磨製程(第15圖)、覆蓋保護膜44並切割開蓋(第16圖)、蝕刻露出第一連接點141(第17圖)與移除承載板220(第18圖)。製作半導體封裝結構100之方法詳述如下。
首先如第7圖所示，先提供一承載板220。在承載板220上利用銅柱電鍍製程形成複數個底層連接點142(即基底連線層14a)。底層連接點142的形成方法例如係於承載板220上形成銅金屬層，進而以電鍍阻劑疊覆於銅金屬層，並依次將電鍍阻劑曝光及顯像而形成圖樣遮罩。此後，藉由圖樣遮罩而對銅金屬層進行使用蝕刻液的圖樣蝕刻處理。經由圖樣蝕刻處理，在承載板220之部分表面形成陣列狀配置的底層連接點142。另外，底層連接點142除了上述以厚銅蝕刻的方式形成之外，亦可以利用半加成技術(semi-additive process，SAP)形成之，於此並不加以限制。
再者如第8圖所示，進行底層基底介電層13a模封與研磨製程。例如，於承載板220與底層連接點142上提供一介電材料，再對介電材料進行一壓合製程，以於承載板220與底層連接點142上形成基底介電層13a。繼之，利用化學機械研磨(chemical mechanical polishing，CMP)製程或機械研磨(grinding)製程來薄化基底介電層13a並暴露出底層連接點142。基底介電層13a下表面為基底底面131。
之後如第9圖所示，利用半加成法，於底層連接點142 與基底介電層13a上形成上層基底連線層14b之佈線層35，並利用銅柱電鍍製程於佈線層35上形成複數個導電柱37。接著如第10圖所示，於基底連線層14b上進行上層基底介電層13b模封與研磨製程，暴露出導電柱37。然後如第11圖所示，利用半加成法形成下層支撐連線層54a之佈線層35。
據此，於承載板220上形成基底連線層14a、14b與基底介電層13a、13b。基底連線層14a、14b位於基底介電層13a、13b內部。基底介電層13a、13b之基底頂面132上定義有一置晶預定區30。
其後如第12圖所示，於置晶預定區30表面貼合一離型膜42。繼之如第13圖所示，進行下層支撐介電層53a模封製程。對支撐介電層53a進行一雷射鑽孔製程，以於支撐介電層53a中形成複數個貫孔38。接著如第14圖所示，施以無電解銅電鍍、電解銅電鍍或沈積製程而於貫孔38之中填入導電材料，形成複數個導電柱37。其後，利用半加成法於下層支撐介電層53a上形成上層支撐連線層54b，包括佈線層35與導電柱37，電性連接支撐連線層54a。之後如第15圖所示，進行上層支撐介電層53b模封製程，再進行研磨製程而暴露出第二連接點542。基板10表面之第二連接點542可包括打線用接點，例如利用導電柱37支撐來加強打線接點強度。
據此，於基底介電層13a、13b上形成支撐介電層53a、53b與支撐連線層54a、54b。支撐介電層53a、53b位於基底介電層13a、13b之基底頂面132。支撐連線層54a、54b位於支撐介電層53a、53b內部。支撐連線層54b之第二連接點542暴露於支撐介電層53a、53b之支撐頂面532。
其後如第16圖所示，於支撐介電層53b之支撐頂面532與支撐連線層54b表面覆蓋一保護膜44。保護膜44用以在切割製程的過程中保護第二連接點542與支撐介電層53b。接著對置晶預定區30進行一雷射切割製程，再利用真空吸盤吸取置晶預定區30上之保護膜44。由於置晶預定區30上有離型膜42，因此真空吸 盤可以取下離型膜42及其上方之支撐介電層53a、53b與保護膜44，暴露出置晶預定區30。此時，支撐介電層53a、53b與基底介電層13a、13b配合形成置晶凹槽31。
然後如第17圖所示，蝕刻露出第一連接點141。對置晶預定區30內之基底連線層14a、14b進行一蝕刻製程，暴露出第一連接點141。
接著如第18圖所示，從基底介電層13a之基底底面131去除承載板220與保護膜44。部分之基底連線層14b暴露於基底介電層13b之基底頂面132，作為複數個第一連接點141，部分之基底連線層14a暴露於基底介電層13a之基底底面131，作為複數個底層連接點142。據此，完成本發明第一實施例所示之基板10(半導體封裝結構100)。
若欲形成前述第二與三實施例所示之半導體封裝結構200、300，可進一步進行晶片連接(die bond)製程與封裝(molding)製程。例如，先進行第一晶片21之覆晶製程。在第一晶片21之電性接點上形成複數個第一凸塊46。第一凸塊46是電性導通元件，例如為錫球(solder ball)。其後以第一晶片21之主動面211朝下的方式，將第一晶片21置放在置晶凹槽31內，使第一凸塊46電性連接第一晶片21之電性接點與基板10之第一連接點141。之後，利用覆晶製程與打線製程，分別連接至第二晶片22與第三晶片23，再利用壓合製程在基板10上形成封裝層64，以包覆住第一凸塊46、整個第一晶片21及基板10之整個支撐頂面532。接著可選擇性地在基板10的基底底面131上形成複數個第三凸塊48，作為對外連接端，使各半導體封裝結構100、200、300可進一步連接在印刷電路板50上。
於前述實施例中，各支撐連線層54a、54b與各支撐介電層53a、53b之高度可小於嵌入式第一晶片21的厚度。本發明可輕易利用半加成法於各支撐介電層53a、53b中形成支撐連線層54a、54b，不再需要使用晶圓級製程在晶片周圍形成高寬比極大的厚銅柱。相較於厚銅柱只能單純向上單方向延伸，本發明之支 撐連線層54a、54b更具有重新佈線的功能，因此支撐連線層54a、54b投影於支撐頂面532之圖案會異於第二連接點542投影於支撐頂面532之圖案。亦即，以垂直於晶片方向的俯視觀之，在相鄰二個終端第二連接點542之間，存在有支撐連線層54a、54b之橫向配線。
前述實施例係以兩層支撐介電層53a、53b為例進行說明，但本發明不限於此。於其他實施例中，可以有三個以上之支撐連線層54a、54b位於第一晶片21之第一背面212之延伸面與第一主動面211之延伸面之間，且各支撐介電層53a、53b之厚度可小於第一晶片21之厚度。以直接增層方式逐層製作，層間偏移小且可依需求製作任意層數。此外，本發明亦可應用於單晶片封裝結構，亦即半導體封裝結構200可不包含第二晶片22與第二凸塊47。
綜合上述，本發明係為一種覆晶封裝用基板結構，利用增層互連技術，搭配雷射切割後開蓋式基板凹槽製作技術，在基板凹槽底部製作覆晶連結用接點，將晶片局部或全部埋入基板內，再於其上疊合其他晶片。與嵌入式晶片封裝相比，本發明之基板於晶片側邊外設置複數層佈線結構，同時提供晶片支撐與配線雙功能，不但整合了習知兩片基板之功能，可降低整體系統封裝高度，強化散熱能力，並提高整體結構可靠度。
以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包括於後附之申請專利範圍中。

Claims (9)

  1. 一種半導體封裝結構，包括：一第一晶片，該第一晶片具有一第一主動面與相反側之一第一背面；以及一基板，該基板包括：至少一基底介電層，具有一基底頂面與相反側之一基底底面；至少一基底連線層，位於該至少一基底介電層內部，該至少一基底連線層包括複數個第一連接點與複數個底層連接點，分別暴露於該基底頂面與該基底底面；複數個支撐介電層，該等支撐介電層與該第一晶片均設置於該基底頂面，該等支撐介電層與該至少一基底介電層配合形成一置晶凹槽，該第一晶片係以該第一主動面向下設置於該置晶凹槽中，且該第一主動面電性連接該等第一連接點；複數個支撐連線層，該等支撐連線層位於該等支撐介電層內部，該等支撐連線層包括複數個第二連接點暴露於該支撐頂面；一第二晶片，該第二晶片具有一第二主動面，其中該第二晶片係位於該等支撐介電層之該支撐頂面與該第一晶片之上，且該第二晶片係以該第二主動面向下覆晶連接該等支撐連線層之該等第二連接點；以及一第三晶片，該第三晶片具有一第三主動面，其中該第三晶片係以該第三主動面向上之方式設置於該第二晶片之上，且該第三晶片係以打線連接該等支撐連線層之該等第二連接點。
  2. 如申請專利範圍第1項所述之半導體封裝結構，另包括：複數個第一凸塊，該等第一凸塊連接該第一晶片與該等第一連接點；以及複數個第二凸塊，該等第二凸塊連接該第二晶片與該等第二連接點。
  3. 如申請專利範圍第1項所述之半導體封裝結構，其中各該支撐介電層之厚度小於該第一晶片之厚度。
  4. 如申請專利範圍第1項所述之半導體封裝結構，其中各該支撐連線層包括一佈線層與複數個導電柱，該等導電柱用以電性連接該等佈線層。
  5. 如申請專利範圍第1項所述之半導體封裝結構，其中該第一晶片之該第一背面與該等支撐連線層之該支撐頂面大致上等高。
  6. 如申請專利範圍第1項所述之半導體封裝結構，其中該等支撐連線層投影於該支撐頂面之圖案異於該等第二連接點投影於該支撐頂面之圖案。
  7. 如申請專利範圍第1項所述之半導體封裝結構，其中該至少一基底介電層與該等支撐介電層為高填料含量介電材(high filler content dielectric material)，主要包括環氧樹脂(epoxy)。
  8. 一種製作半導體封裝結構之方法，包含：提供一承載板；於該承載板上形成至少一基底連線層與至少一基底介電層，該至少一基底連線層位於該至少一基底介電層內部，該至少一基底介電層之一基底頂面具有一置晶預定區；於該置晶預定區表面提供一離型膜；於該至少一基底介電層上形成複數個支撐介電層與複數個支撐連線層，該等支撐介電層位於該至少一基底介電層之該基底頂面，該等支撐連線層位於該等支撐介電層內部，部分之該等支撐連線層暴露於該等支撐介電層之該支撐頂面，作為複數個第二連接點；對該置晶預定區進行一切割製程，以去除該置晶預定區上方之該等支撐介電層與該離型膜，暴露出該置晶預定區，該等支撐介電層與該至少一基底介電層配合形成一置晶凹槽；以及去除該承載板，部分之該至少一基底連線層暴露於該至少一基底介電層之該基底頂面，作為複數個第一連接點，部分之該至少一基底連線層暴露於該至少一基底介電層之一基底底面，作為複數個底層連接點。
  9. 如申請專利範圍第8項所述之製作半導體封裝結構之方法，更包括：在進行該切割製程之前，於該等支撐介電層之該支撐頂面上覆蓋一保護膜，該保護膜用以在該切割製程的過程中保護該等第二連接點；對該置晶預定區內之該至少一基底連線層進行一蝕刻製程，暴露出該等第一連接點；以及去除該保護膜。
TW107107834A 2018-03-08 2018-03-08 半導體封裝結構及其製作方法 TWI671861B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW107107834A TWI671861B (zh) 2018-03-08 2018-03-08 半導體封裝結構及其製作方法
US16/291,065 US20190279925A1 (en) 2018-03-08 2019-03-04 Semiconductor package structure and method of making the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW107107834A TWI671861B (zh) 2018-03-08 2018-03-08 半導體封裝結構及其製作方法

Publications (2)

Publication Number Publication Date
TWI671861B true TWI671861B (zh) 2019-09-11
TW201939678A TW201939678A (zh) 2019-10-01

Family

ID=67842812

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107107834A TWI671861B (zh) 2018-03-08 2018-03-08 半導體封裝結構及其製作方法

Country Status (2)

Country Link
US (1) US20190279925A1 (zh)
TW (1) TWI671861B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI733569B (zh) * 2020-08-27 2021-07-11 矽品精密工業股份有限公司 電子封裝件及其製法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI703685B (zh) * 2018-11-21 2020-09-01 欣興電子股份有限公司 發光二極體封裝及其製作方法
CN111446235B (zh) * 2020-01-19 2022-01-28 弘凯光电(深圳)有限公司 一种发光体及发光模组
US11088090B1 (en) * 2020-02-12 2021-08-10 Qualcomm Incorporated Package comprising a substrate that includes a stress buffer layer
US11430776B2 (en) 2020-06-15 2022-08-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacturing
KR20220008168A (ko) * 2020-07-13 2022-01-20 삼성전자주식회사 반도체 패키지
CN112713126A (zh) * 2020-12-30 2021-04-27 成都芯源系统有限公司 多裸片封装结构、芯片及方法
CN112736043B (zh) * 2020-12-30 2022-09-06 成都芯源系统有限公司 多裸片封装模块及方法
CN114698259B (zh) * 2020-12-30 2024-05-28 中芯集成电路（宁波）有限公司 射频前端模组板级系统封装结构及其封装方法
CN113130420A (zh) * 2021-03-19 2021-07-16 南通越亚半导体有限公司 一种嵌埋封装结构及其制造方法
CN115881654B (zh) * 2023-01-31 2023-08-22 深圳新声半导体有限公司 埋入式滤波器和射频前端模组的封装结构及其制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140103527A1 (en) * 2012-03-23 2014-04-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units
US20170207205A1 (en) * 2016-01-14 2017-07-20 Jichul Kim Semiconductor packages

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140103527A1 (en) * 2012-03-23 2014-04-17 Stats Chippac, Ltd. Semiconductor Device and Method of Forming a POP Device with Embedded Vertical Interconnect Units
US20170207205A1 (en) * 2016-01-14 2017-07-20 Jichul Kim Semiconductor packages

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI733569B (zh) * 2020-08-27 2021-07-11 矽品精密工業股份有限公司 電子封裝件及其製法

Also Published As

Publication number Publication date
TW201939678A (zh) 2019-10-01
US20190279925A1 (en) 2019-09-12

Similar Documents

Publication Publication Date Title
TWI671861B (zh) 半導體封裝結構及其製作方法
US10128211B2 (en) Thin fan-out multi-chip stacked package structure and manufacturing method thereof
US10867897B2 (en) PoP device
US8143710B2 (en) Wafer-level chip-on-chip package, package on package, and methods of manufacturing the same
US8120186B2 (en) Integrated circuit and method
US11515290B2 (en) Semiconductor package
TWI496270B (zh) 半導體封裝件及其製法
TWI662667B (zh) 封裝結構及其製造方法
US20100252937A1 (en) Electronic device and method of manufacturing same
JP2010050489A (ja) 半導体装置
JP3651346B2 (ja) 半導体装置およびその製造方法
JP6100489B2 (ja) 半導体装置の製造方法
CN112038305A (zh) 一种多芯片超薄扇出型封装结构及其封装方法
KR20210157787A (ko) 반도체 패키지 및 이의 제조 방법
TW201737452A (zh) 系統級封裝及用於製造系統級封裝的方法
TW202025419A (zh) 低翹曲扇出型封裝結構
TW202220151A (zh) 電子封裝件及其製法
TW201438159A (zh) 超薄封裝上封裝ＰｏＰ之封裝
JP2022023830A (ja) 半導体パッケージにおける放熱及びその形成方法
US20230395571A1 (en) Electronic package and manufacturing method thereof
CN110246812A (zh) 一种半导体封装结构及其制作方法
CN111312676A (zh) 一种扇出型封装件及其制作方法
US12027484B2 (en) Electronic package and carrier thereof and method for manufacturing the same
CN117153805A (zh) 电子封装件及其制法
TW202339130A (zh) 電子封裝件及其製法