CN111312676A - 一种扇出型封装件及其制作方法 - Google Patents
一种扇出型封装件及其制作方法 Download PDFInfo
- Publication number
- CN111312676A CN111312676A CN202010116109.7A CN202010116109A CN111312676A CN 111312676 A CN111312676 A CN 111312676A CN 202010116109 A CN202010116109 A CN 202010116109A CN 111312676 A CN111312676 A CN 111312676A
- Authority
- CN
- China
- Prior art keywords
- redistribution layer
- input
- chip
- fan
- output ports
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0233—Structure of the redistribution layers
- H01L2224/02331—Multilayer structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02373—Layout of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02375—Top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02379—Fan-out arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Abstract
本发明是一种扇出型封装件,包括基底,所述基底上设有容置槽;至少一块芯片,位于所述基底的容置槽中;塑封材料,包封所述至少一块芯片并固定于所述基底的容置槽中;其中,所述芯片中引入TSV结构,将部分输入输出端口电引导至背面,然后在正反两面都设计再分布层结构,减少了单一侧的再分布层金属层数,从而降低了寄生电容和信号串扰的发生,使得器件的稳定性和可靠性得到提升。
Description
技术领域
本发明涉及半导体技术领域,尤其是涉及一种扇出型封装件及其制作方法。
背景技术
半导体封装领域,随着封装高集成度的要求,以硅通孔(Through Silicon Via,TSV)为核心的3D IC封装成为高密度封装领域的重要技术。
同时,随着芯片变得越来越小,I/O数越来越多,扇入型晶圆级封装已不能满足互连的要求。扇出(fanout)封装技术作为解决此矛盾的方案,通过重构芯片在晶元的排布,将小芯片I/O引出本体之外,形成比其更大的封装体。
上述fanout方案之一的先上芯,芯片正面朝上工艺,当芯片正面I/O较多时,会不可避免出现不同信号金属层在芯片正上方重叠的设计,两者之间使用PI聚酰亚胺绝缘层阻隔(通常为5um厚度)。
请参见图1,图1是一种现有的扇出型封装结构的示意图。如图所示,该扇出型封装结构200包括基底201,芯片202,该芯片202上具有多个输入输出端口(I/O)203a、203b等,芯片202通过塑封材料204被封装在基底201上。这些输入输出端口203a、203b通过再分布层206被连接至外部的栅型球阵列(BGA)上,该栅型球阵列包括多个焊球207a、207b等,再分布层206中具有多层金属层导线,并通过钝化层(PI、聚酰亚胺绝缘层)205包封,形成保护。
然而上述扇出型封装结构中,当输入输出端口(I/O)较多,存在不同信号金属层在芯片正上方重叠的设计时,会带来以下问题:一、引入更高的寄生电容电感;二、不同信号层间的串扰;三、钝化层受外力易发生形变断裂造成信号短路或断路的风险。
因此,提出一种新的扇出型封装结构,以应对多I/O口器件带来的挑战成为业内普遍关注的问题。
发明内容
有鉴于此,本发明的目的在于提出一种新的扇出型封装件及其制作方法,通过结合TSV结构,让芯片的部分I/O口引入至背面,从而在正反两面实施再分布层,减少单面再分布层的层数,从而减少现有技术中存在的问题。
根据本发明的目的提出的一种扇出型封装件,包括
基底,所述基底上设有容置槽;
至少一块芯片,位于所述基底的容置槽中;
塑封材料,包封所述至少一块芯片并固定于所述基底的容置槽中;
其中,所述芯片包括第一表面和与所述第一表面相背的第二表面,所述第一表面设有多个输入输出端口,所述第二表面设有多个凸块,所述多个凸块的位置对应所述多个输入输出端口中的至少部分,每一对对应的凸块和输入输出端口之间由贯穿所述芯片的TSV电连接;
第一再分布层,电连接在所述第一表面的至少部分输入输出端口上,并按所述第一再分布层的图形将该部分输入输出端口分别引导至多个外部焊球上;
第二再分布层,电连接在所述第二表面的至少部分凸块上,并按所述第二再部分层的图形将该部分凸块电互连或电引出。
优选的,所述芯片的数量为至少两块,每块所述芯片有至少一个凸块通过所述第二再分布层与其它芯片中的至少一个凸块电互连。
优选的,所述塑封材料至少溢出在所述容置槽的外部,并在对应所述第一表面的至少部分输入输出端口位置具有开口,以露出所述部分输入输出端口。
优选的,还包括钝化层,设置在所述塑封材料上,所述钝化层包封所述第一再分布层,并露出与所述外部焊球连接的区域。
优选的,所述塑封材料充满所述容置槽内,将所述芯片和所述第二再分布层进行包封。
根据本发明的目的还提出了一种如上所述的扇出型封装件的制作方法,包括步骤:
提供一基底,并在所述基底上开设容置槽;
在所述容置槽的底部制作导电层,并刻蚀处所需的图形,形成第二再分布层;
将至少一块芯片的第二表面粘接在所述第二再分布层上,使得所述第二表面的至少部分凸块被所述第二再部分层电互连或电引出;
填充塑封材料并固化,使所述芯片被包封于所述塑封材料中;
使所述芯片第一表面上的部分输入输出端口露出,并在所述塑封材料上制作第一再分布层,使得所述第一表面的至少部分输入输出端口被所述第一再分布层的图形电引导至多个外部焊球上;
在所述第一再分布层上制作多个所述外部焊球。
优选的,所述塑封材料充满整个容置槽并溢出,使得所述第二再分布层被包封于所述塑封材料中。
优选的,在填充所述塑封材料后,还包括露出所述第一表面输入输出端口的步骤,所述露出所述第一表面输入输出端口的步骤包括使用光刻法在对应所述输入输出端口位置处开窗,或者将该塑封材料减薄,以露出所述第一表面的输入输出端口。
优选的,还包括在所述第一再分布层上制作钝化层,所述钝化层包封所述第一再分布层,并露出与所述外部焊球连接的区域,所述外部焊球制作在该些区域上。
优选的,当所述芯片的数量为至少两块时,所述第二再分布层的图形将所述至少两块芯片中对应TSV的凸块电互连或电引出。
本发明通过在扇出型封装结构中引入TSV结构,让芯片的正反两面通过TSV导通,使得部分输入输出端口被电连接至背面,然后在芯片的正反两面分别设计第一再分布层和第二再分布层,将需要互连或者需要被引出到外部的输入输出端口在正反两面分别通过第一再分布层和第二再分布层实现。和现有技术相比,本发明的优势在于:
1、由于再分布层被设计在芯片的正反两面,能够减少同一侧再分布层的金属层数,从而减少寄生电容的产生,同时能够减少不同层间的信号串扰。
2、同样由于再分布层的金属层数减少,使得钝化层的保护能力提升,被包封的金属层不易断裂或接触,降低了短路和断路的风险。
3、由于再分布层的金属层数减少,制作单侧再分布层的工艺步骤被大大缩减,提升了器件的制作效率和良率。
4、通过将芯片包封在基底的凹槽内,增加了整个器件的牢固性,并可以减少塑封材料的使用,提高器件的品质。
附图说明
图1是一种现有的扇出型封装结构的示意图。
图2是本发明第一实施方式下的扇出型封装件的结构示意图。
图3a-3g是本发明第一实施方式扇出型封装件的制作方法流程示意图。
图4是本发明第二实施方式下的扇出型封装件的结构示意图。
具体实施方式
以下将结合附图所示的具体实施方式对本发明进行详细描述,但这些实施方式并不限制本发明,本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
如背景技术中所述的,现有的扇出型封装器件,在一些多I/O管脚的芯片上,需要引入多层再分布层,这些再分布层的金属层之间,会引入更多的寄生电容,同时在一些高频信号的处理场景中,很容易产生信号串扰的问题,并且多层再分布层的塑封也是一种挑战,不仅工艺复杂,而且容易让器件形成断路或短路。
因此,本发明提出了一种基于TSV结构的扇出型封装器件,通过在多I/O管脚的芯片中引入TSV,使得部分I/O管脚被TSV电传导至背面,并且在背面也制作再分布层,这样一来,就可以让再分布层分布在芯片的两侧,减少了单侧再分布层的层数,从而有效解决现有技术中存在的问题。
下面将通过具体实施方式对本发明的技术方案做详细描述。
实施方式一
请参见图2,图2是本发明第一实施方式下的扇出型封装件的结构示意图。如图所示,该扇出型封装件100,包括基底1,芯片2,塑封材料6,第一再分布层7,第二再分布层5,以及多个焊球9。该基底1通常为半导体材料,比如硅、锗、硒,或是化合物半导体、有机物半导体等,基底1上设有容置槽,作为放置和支撑芯片的作用,同时承担一部分电气性能。
芯片2被放置于基底1的容置槽内上,该芯片2包括第一表面和与第一表面相背的第二表面,第一表面设有多个输入输出端口8,第二表面设有多个凸块3,多个凸块3的位置对应多个输入输出端口8中的至少部分,每一对对应的凸块3和输入输出端口8之间由贯穿所述芯片的TSV4电连接。
如图中所示,TSV4将一部分输入输出端口7导通至多个凸块3中。通常情况下,在一些高密度芯片中,并非每个输入输出端口需要外接输入源或输出给下游电路,本发明优选一些并非需要外接的输入输出端口通过TSV4导通到第二表面,分散第一表面上需要外接的输入输出端口数量。当然即使选择一些需要外接的端口通过TSV4导通到第二表面,也不背离本发明的发明精神,在这种情况下,同样可以使用再分布层技术将位于第二表面的需外接的端口进行引出。
芯片2相对基底1的第二表面与设置在容置槽底部的第二再分布层5粘接,如图中所示,在该芯片2的周围填充塑封材料6,使得该塑封材料6充满整个容置槽且溢出。该塑封材料6除了将芯片2包封外,还将第二再分布层2包封在其中,起到保护第二再分布层5以及让芯片2封装在容置槽内的作用。该塑封材料6比如是环氧树脂材料或其它使用在半导体封装上的塑封材料。
在一种实施方式中,该塑封材料6至少溢出在容置槽的外部,通过光刻法,在塑封材料6上涂敷光刻胶材料,或者填充的塑封材料本身选用光敏材料,如聚酰亚胺(PI)等,然后曝光刻蚀,在对应芯片2第一表面的至少部分输入输出端口8位置处开窗,以露出对应的这些部分输入输出端口8。在另一种实施方式中,在输入输出端口本身具有凸出的焊盘时,可以将该塑封材料8减薄至与这些端口焊盘齐平的高度,从而露出这些端口,使得后续的再分布层可以直接制作在这些焊盘上。
第一再分布层7电连接在第一表面的至少部分输入输出端口8上,这部分输入输出端口8通常为需要和外部电路之间有信号传输,或为预设的外接端口。该第一再分布层7的一部分覆盖在塑封材料6上,一部分沿着塑封材料6的开口向下延伸,接触在输入输出端口8上,一部分向上延伸形成焊盘或与其它再分布层的衔接柱。该第一再分布层7被设计成具有一定的图形,该第一再分布层的图形将该部分输入输出端口分别引导至多个外部焊球9上。
第二再分布层5电连接在第二表面的至少部分凸块3上,该第二再分布层5制作在容置槽的底部,并且被设计成一定的图形,该第二再部分层5的图形将该部分凸块电互连或电引出。
在图2的实施方式中,芯片2的数量为一块,该芯片2内具有多个TSV4,通过这些TSV4将多个输入输出端口8电引导至第二表面,在通过第二再分布层5将这些被TSV4引导至第二表面的端口进行电互连或电引出。在本实施方式对应的应用场景中,通常选择两个或两个以上需要对接的输入输出端口制作TSV,并在第二表面上用第二再分布层进行电互连,这样可以避免这些对接的端口占用一层第一再分布层。
优选地,还可以在塑封材料6上制作一层钝化层,该钝化层包封第一再分布层7,并露出与外部焊球9连接的区域,用以避免外部接触对第一再分布层7造成破坏。该钝化层比如是聚酰亚胺绝缘层(PI)或其它具有钝化保护效果的材料。钝化层在第一再分布层7与外部焊球9连接的区域设有开口,以露出这些区域的第一再分布层7。
请再参见图3a-图3g,是本发明第一实施方式扇出型封装件的制作方法流程示意图。该制作方法包括步骤:
提供一基底1,并在该基底1上开设容置槽,该容置槽的开口大小应满足放置所需封装芯片的尺寸,深度应至少大于芯片的厚度,如图3a-图3b所示,其中左边图示部分为剖面图,右边为对应的俯视图(下同)。
在容置槽的底部制作导电层,并刻蚀处所需的图形,形成第二再分布层5,如图3c所示。该第二再分布层5的图形中,至少包括对应在芯片第二表面凸块的焊接点,以及连接这几个焊接点的若干导线,这些导线将焊接点引出到其它位置或进行互连,实现芯片的电气功能。
将芯片2的第二表面电连接在第二再分布层5上。连接时,需将第二表面的凸块3对准在第二再分布层5对应的焊盘上,如图3d所示,这样这些凸块3对应的输入输出端口就可以通过第二再分布层5实现电互连或电引出。
然后在容置槽中填充塑封材料6并固化,使芯片2被包封于塑封材料6中。填充时,需将塑封材料6充满整个容置槽并溢出,确保第二再分布层5也被包封于塑封材料6中,如图3e所示。
接下来对溢出的塑封材料6进行光刻或者减薄,在芯片2第一表面对应需引出的部分输入输出端口8处形成开窗,使该部分输入输出端口8露出。然后在塑封材料上制作第一再分布层7,使得该第一再分布层7的一部分覆盖在塑封材料6上,一部分沿着塑封材料6的开口向下延伸,接触在输入输出端口8上,一部分向上延伸形成焊盘或与其它再分布层的衔接柱,形成所需的图形,如图3f所示。这样,通过该第一再分布层7,这些部分输入输出端口8将会被分别引导至位于不同位置的外接焊盘上。
最后,在第一再分布层7的外接焊盘上制作多个外部焊球9,使得位于芯片2第一表面的部分输入输出端口8被电引导至这些外部焊球9上,如图3g所示。
优选地,可以在该第一再分布层上制作钝化层,该钝化层用来包封所述第一再分布层,并露出与所述外部焊球连接的区域,所述外部焊球制作在该些区域上。
本实施方式针对的是单一芯片的封装,该芯片比如是高密度管脚芯片,包括多个输入输出端口,将其中部分端口通过TSV结构电引导至第二表面,并在第二表面对应位置设置接线用的凸块。利用第一再分布层将第一表面的部分端口引出,利用第二再分布层将第二表面的凸块互连或引出,从而使得芯片两侧都具有再分布层的结构,避免了再分布层集中在一侧时容易引入更多寄生电容等问题。
第二实施方式
请参见图4,图4是本发明第二实施方式下扇出型封装件的结构示意图。如图所示,在该实施方式中,扇出型封装件110引入了两块芯片2a和2b,每一块芯片都具有至少一个TSV4’。这两块芯片可以是不同功能的芯片,也可以是相同功能的芯片,且彼此之间需要有信号传递,即芯片2a的至少一个输入输出端口需要连接到芯片2b的至少一个输入输出端口上。根据本发明的主旨,这些需要互连或引出的输入输出端口将通过TSV4’电引导至第二表面对应的凸块3’上。
在该实施方式中,第一再分布层7’和第二再分布层5’的图形需要按照具体的电路需求,分别将第一表面需要电互连或电引出的输入输出端口8’引导至外部,与焊球9’连接,以及将芯片2a和芯片2b对应TSV4’的凸块3’电互连在一起,或者,这些凸块对应的输入输出端口8’需要向外引出时,第二再分布层5’的图形被设计成将这些凸块3’电引出的功能。
实施方式二给出了两块芯片的封装件结构,应当注意的是,对于两块以上的多芯片封装,同样可以根据本发明的发明主旨、无需经过创造性劳动被设计出来。对于该实施方式二的制作方法,与实施方式一基本相同,仅在设计第一再分布层和第二再分布层的图形时,需要根据具体的电路需求进行设计。对和实施方式一相同之处,不再赘述。
综上所述,本发明提出了一种新的扇出型封装件及其制作方法,该封装件通过在芯片中引入TSV结构,将部分输入输出端口电引导至背面,然后在正反两面都设计再分布层结构,减少了单一侧的再分布层金属层数,从而降低了寄生电容和信号串扰的发生,使得器件的稳定性和可靠性得到提升。
尽管为示例目的,已经公开了本发明的优选实施方式,但是本领域的普通技术人员将意识到,在不脱离由所附的权利要求书公开的本发明的范围和精神的情况下,各种改进、增加以及取代是可能的。
Claims (10)
1.一种扇出型封装件,其特征在于:包括
基底,所述基底上设有容置槽;
至少一块芯片,位于所述基底的容置槽中;
塑封材料,包封所述至少一块芯片并固定于所述基底的容置槽中;
其中,所述芯片包括第一表面和与所述第一表面相背的第二表面,所述第一表面设有多个输入输出端口,所述第二表面设有多个凸块,所述多个凸块的位置对应所述多个输入输出端口中的至少部分,每一对对应的凸块和输入输出端口之间由贯穿所述芯片的TSV电连接;
第一再分布层,电连接在所述第一表面的至少部分输入输出端口上,并按所述第一再分布层的图形将该部分输入输出端口分别引导至多个外部焊球上;
第二再分布层,电连接在所述第二表面的至少部分凸块上,并按所述第二再部分层的图形将该部分凸块电互连或电引出。
2.如权利要求1所述的扇出型封装件,其特征在于:所述芯片的数量为至少两块,每块所述芯片有至少一个凸块通过所述第二再分布层与其它芯片中的至少一个凸块电互连。
3.如权利要求1或2所述的扇出型封装件,其特征在于:所述塑封材料至少溢出在所述容置槽的外部,并在对应所述第一表面的至少部分输入输出端口位置具有开口,以露出所述部分输入输出端口。
4.如权利要求3所述的扇出型封装件,其特征在于:还包括钝化层,设置在所述塑封材料上,所述钝化层包封所述第一再分布层,并露出与所述外部焊球连接的区域。
5.如权利要求1或2所述的扇出型封装件,其特征在于:所述塑封材料充满所述容置槽内,将所述芯片和所述第二再分布层进行包封。
6.一种如权利要求1-5任意一项所述的扇出型封装件的制作方法,其特征在于,包括步骤:
提供一基底,并在所述基底上开设容置槽;
在所述容置槽的底部制作导电层,并刻蚀出所需的图形,形成第二再分布层;
将至少一块芯片的第二表面粘接在所述第二再分布层上,使得所述第二表面的至少部分凸块被所述第二再部分层电互连或电引出;
填充塑封材料并固化,使所述芯片被包封于所述塑封材料中;
使所述芯片第一表面上的部分输入输出端口露出,并在所述塑封材料上制作第一再分布层,使得所述第一表面的至少部分输入输出端口被所述第一再分布层的图形电引导至多个外部焊球上;
在所述第一再分布层上制作多个所述外部焊球。
7.如权利要求6所述的扇出型封装件的制作方法,其特征在于:所述塑封材料充满整个容置槽并溢出,使得所述第二再分布层被包封于所述塑封材料中。
8.如权利要求7所述的扇出型封装件的制作方法,其特征在于:在填充所述塑封材料后,还包括露出所述第一表面输入输出端口的步骤,所述露出所述第一表面输入输出端口的步骤包括使用光刻法在对应所述输入输出端口位置处开窗,或者将该塑封材料减薄,以露出所述第一表面的输入输出端口。
9.如权利要求6所述的扇出型封装件的制作方法,其特征在于:还包括在所述第一再分布层上制作钝化层,所述钝化层包封所述第一再分布层,并露出与所述外部焊球连接的区域,所述外部焊球制作在该些区域上。
10.如权利要求6所述的扇出型封装件的制作方法,其特征在于:当所述芯片的数量为至少两块时,所述第二再分布层的图形将所述至少两块芯片中对应TSV的凸块电互连或电引出。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010116109.7A CN111312676B (zh) | 2020-02-25 | 2020-02-25 | 一种扇出型封装件及其制作方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010116109.7A CN111312676B (zh) | 2020-02-25 | 2020-02-25 | 一种扇出型封装件及其制作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111312676A true CN111312676A (zh) | 2020-06-19 |
CN111312676B CN111312676B (zh) | 2021-11-09 |
Family
ID=71161915
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010116109.7A Active CN111312676B (zh) | 2020-02-25 | 2020-02-25 | 一种扇出型封装件及其制作方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN111312676B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11288431B2 (en) | 2020-03-06 | 2022-03-29 | Joulwatt Technology (Hangzhou) Co., Ltd. | Method and system for establishing metal interconnection layer capacitance prediction model |
CN114980499A (zh) * | 2022-05-19 | 2022-08-30 | 维沃移动通信有限公司 | 封装结构、封装结构的封装方法以及电子设备 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130171772A1 (en) * | 2009-11-09 | 2013-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via structure formation process |
CN203871322U (zh) * | 2014-01-21 | 2014-10-08 | 华进半导体封装先导技术研发中心有限公司 | 一种应用于高速宽带光互连的硅通孔器件 |
CN107644870A (zh) * | 2016-07-20 | 2018-01-30 | 台湾积体电路制造股份有限公司 | 半导体组件及封装方法 |
CN209029376U (zh) * | 2018-12-26 | 2019-06-25 | 华进半导体封装先导技术研发中心有限公司 | 一种基于基板的ipd集成封装结构 |
-
2020
- 2020-02-25 CN CN202010116109.7A patent/CN111312676B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20130171772A1 (en) * | 2009-11-09 | 2013-07-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-silicon via structure formation process |
CN203871322U (zh) * | 2014-01-21 | 2014-10-08 | 华进半导体封装先导技术研发中心有限公司 | 一种应用于高速宽带光互连的硅通孔器件 |
CN107644870A (zh) * | 2016-07-20 | 2018-01-30 | 台湾积体电路制造股份有限公司 | 半导体组件及封装方法 |
CN209029376U (zh) * | 2018-12-26 | 2019-06-25 | 华进半导体封装先导技术研发中心有限公司 | 一种基于基板的ipd集成封装结构 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11288431B2 (en) | 2020-03-06 | 2022-03-29 | Joulwatt Technology (Hangzhou) Co., Ltd. | Method and system for establishing metal interconnection layer capacitance prediction model |
CN114980499A (zh) * | 2022-05-19 | 2022-08-30 | 维沃移动通信有限公司 | 封装结构、封装结构的封装方法以及电子设备 |
Also Published As
Publication number | Publication date |
---|---|
CN111312676B (zh) | 2021-11-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI482261B (zh) | 三維系統級封裝堆疊式封裝結構 | |
US6534859B1 (en) | Semiconductor package having heat sink attached to pre-molded cavities and method for creating the package | |
US8076770B2 (en) | Semiconductor device including a first land on the wiring substrate and a second land on the sealing portion | |
TWI671861B (zh) | 半導體封裝結構及其製作方法 | |
US7345365B2 (en) | Electronic component with die and passive device | |
US7045391B2 (en) | Multi-chips bumpless assembly package and manufacturing method thereof | |
KR100404373B1 (ko) | 칩-온-칩 패키지 및 그 제조 방법 | |
US6620648B2 (en) | Multi-chip module with extension | |
KR20190005728A (ko) | 이중 측면의 금속 라우팅을 갖는 반도체 패키지 | |
US20140227832A1 (en) | Semiconductor packages and methods of packaging semiconductor devices | |
US20140170814A1 (en) | Ball grid array semiconductor device and its manufacture | |
KR20170075125A (ko) | 반도체 패키지 및 제조 방법 | |
KR100926002B1 (ko) | 반도체 패키지 디바이스와 그의 형성 및 테스트 방법 | |
TWI622153B (zh) | 系統級封裝及用於製造系統級封裝的方法 | |
CN111312676B (zh) | 一种扇出型封装件及其制作方法 | |
KR20210157787A (ko) | 반도체 패키지 및 이의 제조 방법 | |
CN110581107A (zh) | 半导体封装及其制造方法 | |
KR20110076606A (ko) | 반도체 패키지 제조방법 | |
TW202127602A (zh) | 半導體封裝 | |
KR100713931B1 (ko) | 고속 및 고성능의 반도체 패키지 | |
US20040150099A1 (en) | Cavity down MCM package | |
US11227814B2 (en) | Three-dimensional semiconductor package with partially overlapping chips and manufacturing method thereof | |
CN111312677B (zh) | 一种扇出型封装件及其制作方法 | |
TW202213163A (zh) | 半導體結構 | |
KR100673378B1 (ko) | 칩 스케일 적층 칩 패키지와 그 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
CB02 | Change of applicant information | ||
CB02 | Change of applicant information |
Address after: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province Applicant after: Jiehuate Microelectronics Co.,Ltd. Address before: Room 901-23, 9 / F, west 4 building, Xigang development center, 298 Zhenhua Road, Sandun Town, Xihu District, Hangzhou City, Zhejiang Province Applicant before: JOULWATT TECHNOLOGY (HANGZHOU) Co.,Ltd. |
|
GR01 | Patent grant | ||
GR01 | Patent grant |