CN105895610B - 半导体装置以及具有竖直连接条的引线框 - Google Patents

半导体装置以及具有竖直连接条的引线框 Download PDF

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CN105895610B
CN105895610B CN201410858172.2A CN201410858172A CN105895610B CN 105895610 B CN105895610 B CN 105895610B CN 201410858172 A CN201410858172 A CN 201410858172A CN 105895610 B CN105895610 B CN 105895610B
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lead
connection strap
outlet
interior
leads
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CN105895610A (zh
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刘鹏
贺青春
吴萍
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NXP USA Inc
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Abstract

一种半导体装置，包括具有管芯支撑区域和包围该管芯支撑区域的多个内排和外排引线的引线框，以及安装在该管芯支撑区域上并利用接合线电连接至所述引线的半导体管芯。模制材料封装该半导体管芯、接合线以及引线并限定出封装体。该半导体装置进一步包括从引线竖直地延伸至封装体的顶部表面的连接条。在执行该模制处理之前，所述连接条将内排引线连接至外排引线中各自的外排引线。

Description

半导体装置以及具有竖直连接条的引线框
背景技术
本发明涉及集成电路(IC)装置装配以及、特别地涉及用于半导体封装的引线框。
许多通行的方形扁平无引脚(QFN)封装包括多排引线以在保持封装尺寸的同时增加封装的输入和输出(I/O)数量。图1是示出了常规QFN封装100的底部表面的等距视图。使用包括包围标志108的第一和第二排引线104和106的引线框102装配所述QFN封装100。将管芯(未示出)安装在标志108上并电连接到第一和第二排引线104和106。然后由模制原料110封装该管芯和引线框102。
图2示出了封装后的该QFN封装100的横截面视图。将管芯112安装在标志108上并且利用接合线114电连接到第一和第二排引线104和106。在常规方法中，提供具有连接到第一排引线104的第二排引线106的引线框102。因此，在模制或封装处理之后，必须采用刀116对QFN封装100的底侧进行额外的半切割，以将该第二排引线106和该第一排引线104断开。此外，还需要在该第一和第二排引线的切割侧面118上进行选择性电镀。因此，具有装配具有多排引线的QFN封装的替代方式将会是有利的。
附图说明
本发明连同其目的和优点一起，通过参考与附图一起的优选实施例的下述说明能够得到最好的理解，在附图中：
图1是示出了具有两排引线的常规QFN封装的底部表面的等距视图；
图2示出了图1的常规QFN封装在模制处理后的横截面视图；
图3是根据本发明的实施例的引线框的示意性顶视图；
图4是根据本发明的实施例的图3中所示的引线框的连接条的放大示意性顶视图；
图5和6是根据本发明的其他实施例的连接条的放大示意性顶视图；
图7-9是根据本发明的实施例的自图4的线A-A处的连接条的横截面视图，其示出形成竖直连接条的步骤；
图10是根据本发明的实施例的具有竖直连接条的引线框的等距视图；
图11是具有图10所示的竖直连接条的引线框的顶视图；
图12-16是根据本发明的实施例的示出封装半导体装置的步骤的一系列图示；
图17是根据本发明的另一个实施例的引线框的示意性顶视图；
图18是根据本发明的实施例的部分地装配的半导体装置的示意性顶视图；
图19是根据本发明的又一个实施例的引线框的示意性顶视图；
图20是图19所示的具有竖直连接条的该引线框的示意性顶视图；以及
图21是根据本发明的实施例的部分地装配的半导体装置的示意性俯视图。
具体实施方式
下述与附图关联提出的详细描述意图作为本发明目前优选实施例的说明，并且不意图代表本发明可以实践的仅有方式。应理解可以由意图包含在本发明的精神和范围之内的不同的实施例实现相同或者等价的功能。在附图中，相同的数字用于在全文中指示相同的元件。此外，术语“包括”、“包含”或其任何其他变形意图覆盖非排他性的包含，因此包括一系列元件或步骤的模块、电路、装置组件、结构和方法步骤不仅包含那些元件，而是可以包含未明确列出或这些模块、电路、装置组件或方法步骤固有的其他元件或步骤。前接“包括...一个”的元件或步骤，在没有更多限制的情况下，并不排除包括所述元件或步骤的额外的相同元件或步骤的存在。
在一个实施例中，本发明提供了包括引线框的半导体装置，所述引线框具有管芯支撑区域和包围该管芯支撑区域的至少内排和外排引线。将半导体管芯安装在该管芯支撑区域上并利用接合线电连接至所述两排引线。模制材料覆盖该半导体管芯、接合线以及两排引线。该模制材料限定出封装体，两排引线在该封装体的底部表面露出。该半导体装置进一步包括连接至该内部引线的内连接条。该内连接条从该内排引线竖直延伸到该封装体的顶部表面。在将模制材料提供为封装该半导体管芯、接合线和该两排引线之前，该内连接条连接到该外排引线中各自的外排引线。
在另一个实施例中，本发明提供了包括用于支撑半导体管芯的管芯支撑区域和包围该管芯支撑区域的至少两排引线的引线框。所述两排引线包括内排引线和外排引线，以及将每个内排引线连接至外排引线中的各自的外排引线的连接条。该连接条能够弯曲至竖直位置。
在又一个实施例中，本发明提供了一种用于封装半导体装置的方法。该方法包括提供具有管芯支撑区域、包围该管芯支撑区域的至少两排引线以及多个连接条的引线框，其中所述两排引线包括内排引线和外排引线。该内排引线利用连接条连接至该外排引线。该方法进一步包括将该连接条弯曲至竖直位置、将半导体管芯附接至该管芯支撑区域、利用接合线将该管芯电连接至两排引线、利用模制材料封装该管芯、接合线以及两排引线以形成模制封装体、以及去除该模制封装体的顶部部分，其中将该连接条切断从而使得内排引线不再连接到外排引线。
现在参考图3，其示出根据本发明的实施例的引线框200的示意性顶视图。该引线框200包括用于支撑半导体管芯(未示出)的管芯支撑区域202，以及包围该管芯支撑区域202的至少两排引线。所述两排引线包括多个内排引线204和多个外排引线206。该引线框200进一步包括将每个内排引线204连接至外排引线206中的各自的外排引线的连接条208。该连接条208能够从水平位置弯曲至竖直或近似竖直的位置。通过冲压或刻蚀优选地由一片金属片(例如铜片)形成引线框200。
图4示出了根据本发明的实施例的图3中所示的引线框200的连接条208的放大示意性顶视图。在一个优选实施例中，每个引线具有近端和相对的远端，并且该连接条208从每个内排引线204的远端210延伸至每个外排引线206的近端212。每个引线进一步包括彼此相对并且邻近所述近端和远端的两个侧面。该连接条208优选地偏移至所述两个侧面中的一个侧面。在一个优选实施例中，每个引线包括在每个内排引线204的远端210或者在每个外排引线206的近端212处的突出部分214，其中连接条208从该突出部分214延伸。
在一个优选实施例中，该连接条208包括延伸自内排引线204的内部部分216和延伸自外排引线206的外部部分218。该内部部分216与该外部部分218相互平行并通过连接部分220相连接。
图5和6是根据本发明的其他实施例的连接条208的放大示意性顶视图。在一个优选实施例中，该内部部分216和外部部分218在远端222处相交。在一个优选实施例中，如图6所示，内部和外部部分216和218中的一个平行于引线框200的一个侧面。
图7-9是根据本发明的实施例的自图4的线A-A的连接条的横截面视图，其示出形成竖直连接条的步骤。由图7开始，将固定块224放置在内排和外排引线204和206上以帮助弯曲该连接条208。在下一步骤中，如图8所示，从引线框200的底侧推该连接条208并将其弯曲到竖直位置(如图9所示)。
图10和11分别是根据本发明的实施例的具有弯曲至竖直位置的连接条208的引线框200的等距视图和顶视图。每个连接条208将一个内排引线204连接至各自的外排引线206。相邻外排引线206由坝条226连接。该内排和外排引线204和206包围管芯支撑区域202。
图12-16是根据本发明的实施例的示出装配或封装具有引线框200的半导体装置的步骤的一系列图示，该引线框200具有弯曲至竖直位置的连接条208。
由图12开始，提供了具有弯曲至竖直位置的连接条208的引线框200。图12是从图11的线B-B处的引线框200的横截面视图。
在图13所示的下一步骤中，半导体管芯228附接到引线框200的管芯支撑区域202，并利用多个接合线230将管芯电连接至内排和外排引线204和206以形成部分地装配的半导体装置300。由于管芯附接和引线接合是半导体装置装配中的众所周知的步骤，因此除了表述出竖直连接条208的高度优选地大于接合线230的线环的高度之外，这些步骤的详细描述对于本发明的完整理解并不是必要的。图14是图13所示的部分地装配的半导体装置300的顶视图。将每个连接条208偏移设置到每个引线204和206的两个侧面中的一个提供了用于从半导体管芯228到外排引线206结合接合线230的空间。
在图15所示的下一步骤中，利用模制材料302封装半导体管芯228、接合线230以及内排和外排引线204和206以形成模制封装体304。类似于管芯附接和引线接合，封装也是半导体装置装配中的众所周知的步骤。
在图16所示的下一步骤中，沿着图15的线C-C去除模制封装体304的顶部部分以切断连接条208的顶部部分从而使得内排引线204不再连接到外排引线206。在一个优选实施例中，通过研磨或锯切处理沿着图15的线C-C去除模制封装体304的顶部部分。图15的线C-C的高度在连接条208的高度与接合线230的最高的线环的高度之间。还通过切割或冲穿工艺移除坝条226以断开相邻的外排引线206。以这种方式装配该半导体装置300。如图16所示半导体装置300包括具有管芯支撑区域202和包围该管芯支撑区域202的至少两排引线的引线框200，其中所述两排引线包括内排引线204和外排引线206。该半导体装置300还包括安装在管芯支撑区域202上并利用接合线230电连接至两排引线204和206的半导体管芯228、以及封装半导体管芯228、接合线230和两排引线204和206的模制材料302。该模制材料限定出封装体306并且两排引线204和206在该封装体306的底部表面露出。该半导体装置300进一步包括连接至该内排引线204的内连接条208，其中该内连接条208从该内排引线204竖直延伸到该封装体306的顶部表面，并且其中在将模制材料302提供为封装该半导体管芯228、接合线230和该两排引线204和206之前，该内连接条208连接到该外排引线206中各自的外排引线。
图17是根据本发明的另一个实施例的引线框400的示意性顶视图。该引线框400包括用于支撑半导体管芯(未示出)的管芯支撑区域402，包围该管芯支撑区域402的至少两排引线，其中所述两排引线包括多个内排引线404和多个外排引线406。内排引线404和外排引线406交错排列，并且由坝条408将相邻外排引线406相互连接。引线框400进一步包括将每个内排引线404连接到坝条408中的各自的坝条的连接条410，其中该连接条410能够从水平位置弯曲至竖直位置。引线框400优选地通过冲压或刻蚀处理由诸如铜的一片金属片形成。
图18是具有图17所示的引线框400的部分地装配的半导体装置500的示意性顶视图，所述引线框具有弯曲至竖直位置的连接条。半导体管芯228附接到管芯支撑区域402并利用接合线230电连接至内排和外排引线404和406。如图18所示，内排引线404和外排引线406交错排列并且具有将内排引线404连接至坝条408的连接条410，以上提供了用于将接合线230自半导体管芯228接合至外排引线406的空间。
图19是根据本发明的又一实施例的引线框600的示意性顶视图。引线框600包括用于支撑半导体管芯(未示出)的管芯支撑区域602，包围该管芯支撑区域602的至少两排引线，其中所述两排引线包括多个内排引线604和多个外排引线606。引线框600进一步包括将每个内排引线604连接到外排引线606中的各自的外排引线的连接条608，其中该连接条608能够从水平位置弯曲至竖直位置。优选地通过冲压或刻蚀(如本领域公知的)由一片金属片形成引线框600。
图20是根据本发明的实施例的具有弯曲至竖直位置的连接条608的引线框600的示意性顶视图。在将连接条608弯曲至竖直位置之后，并且在管芯附接和引线接合处理之前，将该内排引线604水平地推到虚线所示的位置610以使得内排引线604与外排引线606交错排列。
图21是具有图20所示的引线框600的部分地装配的半导体装置700的示意性顶视图。半导体管芯228附接到管芯支撑区域602并利用接合线230电连接至内排和外排引线604和606。如图21所示，内排引线604和外排引线606的交错排列提供了用于将接合线230自半导体管芯228接合至外排引线606的空间。
为了阐述和描述的目的已经提出了本发明优选实施例的描述，但不意图是详尽的或将本发明限制在所公开的形式内。本领域技术人员将认识到在不脱离其广义发明理念的情况下能够对以上所述的实施例作出改变。因此可以理解本发明不限于所公开的特定实施例，而是覆盖了在如所附权利要求所定义的本发明的精神和范围之内的修改。

Claims (18)

1.一种半导体装置，包括：
引线框，具有管芯支撑区域和包围所述管芯支撑区域的至少两排引线，其中所述两排引线包括互相电学隔离的多个内排引线和多个外排引线；
半导体管芯，安装在所述管芯支撑区域上并利用多个接合线电连接至所述多个内排引线、以及利用多个接合线物理地连接至所述多个外排引线；
模制材料，包封所述半导体管芯、所述接合线以及所述两排引线，其中所述模制材料限定封装体，并且所述两排引线在所述封装体的底部表面露出；以及
多个内连接条，各连接至所述内排引线的对应一个，其中所述内连接条从所述内排引线竖直延伸到所述封装体的顶部表面；
多个外连接条，各连接至所述外排引线的对应一个，其中所述外连接条从所述外排引线竖直延伸到封装体的顶部表面，其中：
在提供模制材料来包封所述半导体管芯、接合线和所述两排引线之前，将所述外连接条连接到所述内连接条中的对应一个；以及
所述模制材料填充在所述内连接条与所述外连接条之间。
2.根据权利要求1所述的半导体装置，其中每个引线包括近端和相对的远端，每个内排引线的内连接条从每个内排引线的远端延伸，并且每个外排引线的外连接条从每个外排引线的近端延伸。
3.根据权利要求2所述的半导体装置，其中每个引线进一步包括彼此相对并且邻近所述近端和远端的两个侧面，并且其中内连接条和外连接条中的每一个被偏移至每个引线的所述两个侧面中的一个。
4.根据权利要求1所述的半导体装置，其中所述内连接条和外连接条中的至少一个以大于90°的倾斜角延伸至所述封装体的顶部表面。
5.根据权利要求1所述的半导体装置，其中所述内排引线和外排引线交错排列。
6.一种半导体装置，包括：
引线框，具有管芯支撑区域和包围所述管芯支撑区域的至少两排引线，其中所述两排引线包括互相电学隔离的多个内排引线和多个外排引线；
半导体管芯，安装在所述管芯支撑区域上并利用多个接合线电连接至所述多个内排引线、以及利用多个接合线物理地连接至所述多个外排引线；
模制材料，包封所述半导体管芯、所述接合线以及所述两排引线，其中所述模制材料限定封装体，并且所述两排引线在所述封装体的底部表面露出；以及
多个连接条，各连接至所述内排引线的对应一个，其中所述连接条从所述内排引线竖直延伸到所述封装体的顶部表面；
坝条，其中在模制之前通过坝条将相邻的所述外排引线相互连接，以及在模制之前多个连接条的每个将对应连接的内排引线连接到坝条。
7.一种引线框，包括：
管芯支撑区域，用于支撑半导体管芯；
至少两排引线，包围所述管芯支撑区域，其中所述两排引线包括多个内排引线和多个外排引线；以及
多个连接条，分别将每个内排引线连接至外排引线中相应的外排引线，其中所述多个连接条能够弯曲至竖直位置；每个连接条包括：
内连接条，连接到相应的内排引线，所述内连接条能够从所述内排引线弯曲至竖直位置；以及
外连接条，连接到相应的外排引线，所述外连接条能够从所述外排引线弯曲至竖直位置；
每个所述外连接条连接到相应一个所述内连接条，并在模制后断开与所述内连接条的连接且与所述内连接条互相电学隔离。
8.根据权利要求7所述的引线框，其中每个引线包括近端和相对的远端，所述连接条从每个内排引线的远端、以及每个外排引线的近端延伸。
9.根据权利要求8所述的引线框，其中每个引线进一步包括彼此相对并且与所述近端和远端邻近的两个侧面，所述连接条偏移至所述两个侧面中的一个。
10.根据权利要求7所述的引线框，其中所述内排引线和外排引线交错排列。
11.一种引线框，包括：
管芯支撑区域，用于支撑半导体管芯；
至少两排引线，包围所述管芯支撑区域，其中所述两排引线包括多个内排引线和多个外排引线；
连接相邻外排引线的坝条；以及
连接条，所述连接条将每个内排引线连接至所述坝条，其中所述连接条能够弯曲至竖直位置；
其中所述多个内排引线与所述多个外排引线交错排列。
12.一种用于封装半导体装置的方法，所述方法包括：
提供具有管芯支撑区域、包围所述管芯支撑区域的至少两排引线以及多个连接条的引线框，其中所述两排引线包括多个内排引线和多个外排引线，其中所述内排引线利用所述连接条连接至所述外排引线；连接条包括内连接条和外连接条，内连接条连接到相应的内排引线，所述内连接条能够从所述内排引线弯曲至竖直位置；外连接条连接到相应的外排引线，所述外连接条能够从所述外排引线弯曲至竖直位置；所述外连接条连接到相应的所述内连接条；
将所述连接条弯曲至竖直位置；
将半导体管芯附接至所述管芯支撑区域；
利用多个接合线将所述半导体管芯电连接至所述两排引线；
利用模制材料包封所述半导体管芯、所述接合线以及所述两排引线以形成模制的封装体；以及
去除所述模制封装体的顶部部分，其中所述连接条切断从而使得所述内排引线不再连接到所述外排引线。
13.根据权利要求12所述的方法，其中通过研磨实现去除所述模制的封装体的顶部部分。
14.根据权利要求12所述的方法，其中在所述去除之后，所述连接条在所述封装体的顶部表面露出，并且所述两排引线在所述封装体的底部表面露出。
15.根据权利要求14所述的方法，其中每个引线包括近端和相对的远端，所述连接条从每个内排引线的远端、以及每个外排引线的近端延伸。
16.根据权利要求15所述的方法，其中每个引线进一步包括彼此相对并且与所述近端和远端相邻的两个侧面，所述连接条偏移至所述两个侧面中的一个。
17.根据权利要求12所述的方法，其中所述内排引线和所述外排引线交错排列。
18.一种用于封装半导体装置的方法，所述方法包括：
提供具有管芯支撑区域、包围所述管芯支撑区域的至少两排引线以及多个连接条的引线框，其中所述两排引线包括多个内排引线和多个外排引线；所述多个内排引线与所述多个外排引线交错排列；其中所述引线框进一步包括连接相邻外排引线的坝条，所述连接条将每个内排引线连接至所述坝条；
将所述连接条弯曲至竖直位置；
将半导体管芯附接至所述管芯支撑区域；
利用多个接合线将所述半导体管芯电连接至所述两排引线；
利用模制材料包封所述半导体管芯、所述接合线以及所述两排引线以形成模制的封装体；
去除所述模制封装体的顶部部分，其中所述连接条切断从而使得所述内排引线不再连接到所述坝条。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107919339B (zh) * 2016-10-11 2022-08-09 恩智浦美国有限公司 具有高密度引线阵列的半导体装置及引线框架
US20180114786A1 (en) 2016-10-21 2018-04-26 Powertech Technology Inc. Method of forming package-on-package structure
US20180301401A1 (en) * 2017-04-12 2018-10-18 Intel Corporation Multi-level lead frame structures and method of providing same
CN108198761B (zh) * 2017-12-29 2020-06-09 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺
CN108198797B (zh) * 2017-12-29 2020-03-06 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺
CN108198804B (zh) * 2017-12-29 2020-03-06 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的堆叠封装结构及其制造工艺
CN108109972B (zh) * 2017-12-29 2020-03-06 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺
CN108198790B (zh) * 2017-12-29 2020-03-06 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的堆叠封装结构及其制造工艺
CN108206170B (zh) * 2017-12-29 2020-03-06 江苏长电科技股份有限公司 具有引脚侧壁爬锡功能的半导体封装结构及其制造工艺

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101477972A (zh) * 2007-10-04 2009-07-08 松下电器产业株式会社 引线框、具备引线框的电子元器件及其制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7049177B1 (en) 2004-01-28 2006-05-23 Asat Ltd. Leadless plastic chip carrier with standoff contacts and die attach pad
US7338841B2 (en) * 2005-04-14 2008-03-04 Stats Chippac Ltd. Leadframe with encapsulant guide and method for the fabrication thereof
US8310060B1 (en) 2006-04-28 2012-11-13 Utac Thai Limited Lead frame land grid array
US7517733B2 (en) * 2007-03-22 2009-04-14 Stats Chippac, Ltd. Leadframe design for QFN package with top terminal leads
JP5358077B2 (ja) * 2007-09-28 2013-12-04 スパンション エルエルシー 半導体装置及びその製造方法
US8785253B2 (en) 2009-04-03 2014-07-22 Kaixin, Inc. Leadframe for IC package and method of manufacture
US8072051B2 (en) * 2009-09-15 2011-12-06 Fairchild Semiconductor Corporation Folded lands and vias for multichip semiconductor packages
US8575732B2 (en) 2010-03-11 2013-11-05 Utac Thai Limited Leadframe based multi terminal IC package
US8377750B2 (en) 2010-12-14 2013-02-19 Stats Chippac Ltd. Integrated circuit packaging system with multiple row leads and method of manufacture thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101477972A (zh) * 2007-10-04 2009-07-08 松下电器产业株式会社 引线框、具备引线框的电子元器件及其制造方法

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