CN107978571A - 堆叠封装结构的制造方法 - Google Patents

堆叠封装结构的制造方法 Download PDF

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Publication number
CN107978571A
CN107978571A CN201710976350.5A CN201710976350A CN107978571A CN 107978571 A CN107978571 A CN 107978571A CN 201710976350 A CN201710976350 A CN 201710976350A CN 107978571 A CN107978571 A CN 107978571A
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China
Prior art keywords
conductor wire
seal
distance piece
circuit carrier
encapsulating structure
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CN201710976350.5A
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Inventor
王启安
徐宏欣
蓝源富
许献文
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Powertech Technology Inc
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Powertech Technology Inc
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Publication of CN107978571A publication Critical patent/CN107978571A/zh
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Abstract

本发明提供一种堆叠封装结构的制造方法，其包含至少以下步骤。接合晶粒于第一电路载体上。设置间隔件在晶粒上。通过多个导电线连接间隔件和第一电路载体。形成密封体以密封晶粒、间隔件以及导电线。减少密封体的厚度直到移除导电线中的每一者的至少一部分以形成第一封装结构。在第一封装结构上堆叠第二封装结构。第二封装结构电性连接到导电线。

Description

堆叠封装结构的制造方法
技术领域
本发明大体上涉及一种封装(package)结构的制造方法，且更具体地说涉及一种堆叠封装(package-on-package，POP)结构的制造方法。
背景技术
为了使电子产品设计实现轻、薄、短和小，半导体封装技术持续发展，尝试开发出体积较小、重量较轻、集成度较高且在市场中更有竞争性的产品。举例来说，已经开发例如POP等3D堆叠(3Dstacking)技术来满足较高封装密度的要求。因此，如何以较低制造成本实现更薄的POP结构已经变为本领域中的研究人员的挑战。
发明内容
本发明提供一种堆叠封装(POP)结构的制造方法，其减少了结构的总体厚度和制造成本。
本发明提供一种POP结构的制造方法。所述方法至少包含以下步骤。接合晶粒于第一电路载体上。设置间隔件在晶粒上。通过多个导电线连接间隔件和第一电路载体。形成密封体以密封晶粒、间隔件以及导电线。减少密封体的厚度直到移除导电线中的每一者的至少一部分以形成第一封装结构。在第一封装结构上堆叠第二封装结构。第二封装结构电性连接到导电线。
在本发明的一实施例中，晶粒通过倒装芯片接合电性连接到第一电路载体。
在本发明的一实施例中，间隔件通过粘着层接合到晶粒。
在本发明的一实施例中，导电线是通过打线机形成。
在本发明的一实施例中，在减少密封体的厚度之前，导电线中的每一者的第一焊接区段与第一电路载体之间的角度大于导电线中的每一者的第二焊接区段与间隔件之间的角度。
在本发明的一实施例中，在减少密封体的厚度之后，密封体暴露出导电线的第一焊接区段中的每一者的一部分以及导电线的第二焊接区段中的每一者的一部分。
在本发明的一实施例中，间隔件通过热粘着层接合到晶粒。
在本发明的一实施例中，在减少密封体的厚度之前，导电线中的每一者的焊接区段与第一电路载体之间的角度大于导电线中的每一者的牺牲区段与间隔件之间的角度。
在本发明的一实施例中，在减少密封体的厚度之后，密封体暴露出导电线的焊接区段中的每一者的一部分。
基于上述，设置于晶粒上的间隔件有利于形成导电线。另外，由于密封体的厚度减少且导电线中的每一者的至少一部分也被移除以形成第一封装结构，因此在密封体中的导电线的剩余部分可以作为第一封装结构与第二封装结构之间的电性连接路径。换句话说，不必在第一封装结构与第二封装结构之间设置额外的中介层(interposer)用于电性连接。因此，可以减少POP结构的总体厚度且可以实现较低的制造成本。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1A到图1F是说明根据本发明的实施例的POP结构的制造方法的剖面示意图。
图2A到图2F是说明根据本发明的另一实施例的POP结构的制造方法的剖面示意图。
附图标号说明
10、20：堆叠封装结构；
100、300：第一封装结构；
110：第一电路载体；
112：核心层；
114：顶部电路层；
114a、116a：导电衬垫；
116：底部电路层；
118：导电结构；
120：第一晶粒；
122：导电凸块；
130、330：间隔件；
132：第二电路载体；
140：粘着层；
150：导电线；
152：第一焊接区段；
152a：焊接部分；
152b、352b：线部分；
154、354：牺牲区段；
156：第二焊接区段；
160：密封体；
200：第二封装结构；
202：第二晶粒；
204：导电端子；
332：导电板；
332a：顶部表面；
340：热粘着层；
350：导电线；
352：焊接区段；
352a：焊接部分；
354a：弧形部分；
354b：尾部部分；
CR：中心区；
H1、H2、H3、H4：高度；
PR：外围区；
S1：顶部表面；
S2：底部表面；
T1、T2：厚度；
θ1、θ2、θ3、θ4：角度。
具体实施方式
图1A到图1F是说明根据本发明的实施例的POP结构的制造方法的剖面示意图。参考图1A，提供第一电路载体(circuitcarrier)110。第一电路载体110可具有顶部表面S1以及与顶部表面S1相对的底部表面S2。举例来说，第一电路载体110可包含核心层(corelayer)、设置于顶部表面S1上的顶部电路层114以及设置于第一电路载体110的底部表面S2上的底部电路层116。核心层112设置于顶部电路层114与底部电路层116之间且电性连接顶部电路层114和底部电路层116。在一些实施例中，顶部电路层114和底部电路层116可以分别包含用于进一步电性连接的多个导电衬垫(conductivepad)114a和116a。此外，导电衬垫114a和导电衬垫116a可以由相同材料和相同工艺形成，例如通过光刻(photolithography)和蚀刻(etching)工艺使用铜、焊料、金、镍或类似物。在一些其它实施例中，导电衬垫114a和导电衬垫116a可以根据设计要求而由不同材料和/或不同工艺形成。
核心层112可进一步包含多个嵌入电路层，其作为电性连接到顶部电路层114和底部电路层116的中间电路层。核心层112可包含基底层(baselayer)以及穿过所述基底层的多个导电通孔(conductivevias)。核心层112的导电通孔的两个相对末端可以电性连接到顶部电路层114的导电衬垫114a和底部电路层116的导电衬垫116a。在一些实施例中，第一封装结构100可包含形成于第一封装结构100的底部表面S2上的多个导电结构118。举例来说，导电结构118的材料可以包含铜、锡、金、镍或其它合适的导电材料。导电结构118可以例如为导电凸块(conductivebump)、导电柱(conductivepillar)或者通过植球工艺(ballplacementprocess)和回焊工艺(reflowprocess)形成的焊球(solderball)。可以利用导电结构118的其它可能的形式和形状用于进一步电性连接。在一些实施例中，导电结构118可以形成阵列，所述阵列被布置成在第一电路载体110的底部表面S2上具有微间距以用于后续工艺中的需求。
第一晶粒(die)120可以设置于第一电路载体110的顶部表面S1上。第一晶粒120可以通过倒装芯片接合(flip-chipbonding)电性连接到第一电路载体110。在一些实施例中，第一晶粒120的有源面(未示出)通过多个导电凸块122耦合到第一电路载体110的顶部电路层114的导电衬垫114a。导电凸块122可以是铜凸块(copper bumps)。在一些实施例中，焊料(未示出)可以施加到导电凸块122的表面上以与导电衬垫114a耦合。第一晶粒120可以是例如专用集成电路(Application-SpecificIntegratedCircuit，ASIC)。在一些实施例中，第一晶粒120可用以执行逻辑应用(logic applications)，但本发明并不以此为限。其它合适的有源装置也可以用作第一晶粒120。
参考图1B，间隔件(spacer)130设置于第一晶粒120上。另外，间隔件130通过粘着层(adhesivelayer)140接合到第一晶粒120。在一些实施例中，粘着层140可以是晶粒附着膜(die attach film)或由包含环氧树脂(epoxy resin)的粘合剂组合物形成。粘着层140可以通过例如旋涂(spincoating)、喷墨印刷(injectprinting)等方法或用于提供结构支撑的其它合适方法而形成，而不需要第一晶粒120与间隔件130之间的机械夹持。
间隔件130可包含第二电路载体132，在与第一晶粒120相对的表面上具有导电衬垫，以用于后续接合工艺。可以利用其它合适形式的间隔件130，且在后续其它实施例中将描述细节。在一些实施例中，间隔件130可以作为虚设芯片(dummychip)，用于执行后续线接合工艺和/或提供间隔件功能，以防止对第一晶粒120的损坏。间隔件130的大小和厚度可以不解释为对第一晶粒120的单元大小和单元厚度的限制。在一些实施例中，间隔件130可以是具有与其中未形成有有源装置的芯片相似的形状或外观的半导体载体。在一些其它实施例中，当整个制造过程完成时，间隔件130和第一晶粒120可以机械地耦合但彼此电性隔离(electrically isolated)。
参考图1C，间隔件130和第一电路载体110通过多个导电线150连接。举例来说，导电线150可以通过打线机(wire bonder)(未示出)形成。打线机的类型可包含根据设计要求的楔型接合(wedge bond)、球型接合(ball bond)或其它合适的打线机。此外，导电线150连接于间隔件130的第二电路载体132与第一电路载体110之间。导电线150的材料可以是金、铜或其它合适的材料，但不限于此。在一些实施例中，导电线150中的每一者可包含第一焊接区段152、牺牲区段(sacrificialsegment)154以及第二焊接区段156。导电线150的第一焊接区段152中的每一者耦合到第一电路载体110，且导电线150的第二焊接区段156中的每一者耦合到间隔件130的第二电路载体132。导电线150是从第一电路载体110形成到间隔件130。此外，导电线150的牺牲区段154中的每一者形成于第一焊接区段152中的任一者与第二焊接区段156中的任一者之间。换句话说，导电线150中的每一者可以由第一焊接区段152、牺牲区段154以及第二焊接区段156的顺序形成。
在一些实施例中，打线机可包含焊接导电线150的自动化装置。举例来说，通过例如瓷嘴(capillary)(未示出)等接合工具(bonding tool)，其施加热、超声波能量、压力或其组合馈送(feed)导电线150中的每一者，以将导电线150中的每一者接合于第一电路载体110与间隔件130之间。在一些实施例中，每条导电线150的第一焊接区段152可以包含接合到第一电路载体110的焊接部分152a以及耦合到焊接部分152a的线部分152b。举例来说，每个第一焊接区段152中的焊接部分152a可以取决于设计要求，通过球型接合、楔型接合或其它合适的接合而形成。在将焊接部分152a接合到第一电路载体110的顶部表面S1之后，耦合到焊接部分152a的每个第一焊接区段152中的线部分152b可以通过打线机的接合工具而被递送出(deliver out)。举例来说，打线机的接合工具可以按垂直的方式从第一电路载体110向上移动，以形成线部分152b。
接着，接合工具可以在向上远离第一电路载体110且朝向间隔件130的方向上移动，以形成牺牲区段154。每条导电线150中的牺牲区段154可以形成为弧形(arc shape)。另外，导电线150中的每一者的线弧(loop)高度H1可以是牺牲区段154的弧形的顶端(peak)与耦合到第一电路载体110的第一焊接区段152的焊接部分152a的底端之间的距离。线弧高度H1可以取决于打线机的类型和/或设计要求，但不限于此。随后，打线机的接合工具可以定位在间隔件130的第二电路载体132的导电衬垫处，且可以形成每条导电线150的第二焊接区段156中的尾部接合(tail bond)，以接合第二电路载体132。因此，第一电路载体110和间隔件130的第二电路载体132上的线接合工艺完成。
在一些实施例中，每条导电线150中的第一焊接区段152与第一电路载体110之间的角度θ1大于或等于每条导电线150中的第二焊接区段156与间隔件130之间的角度θ2。角度θ1可以取决于打线接合的类型和/或设计要求。举例来说，球型打线机在第一电路载体110的导电衬垫114a上焊接导电球(conductive ball)至引线，每条导电线150的引线以直角延伸远离导电球。然而，对于楔型打线机，在一些实施例中，导电线150的引线侧面被按压抵靠着，因此导电线150的第一焊接区段152中的每一者与第一电路载体110的顶部表面S1之间的角度θ1可以小于90度，但实质上接近于90度。在一些其它实施例中，导电线150的第二焊接区段156中的每一者可以垂直于间隔件130。因此，角度θ2可以是90度或实质上接近于90度。
参考图1D，密封体(encapsulant)160形成于第一电路载体110的顶部表面S1上，以密封第一晶粒120、间隔件130、粘着层140以及导电线150。在一些实施例中，密封体160的厚度T1大于导电线150中的每一者的线弧高度H1。密封体160可包含由模制工艺(moldingprocess)形成的模制化合物(molding compound)。在一些实施例中，密封体160可以通过例如环氧树脂或其它合适的树脂等绝缘材料形成。然而，其在本发明中并不解释为限制。
参考图1E，减少密封体160的厚度T1直到导电线150中的每一者的至少一部分被移除，以形成第一封装结构100。举例来说，密封体160的厚度T1减少到如图1E中所示的厚度T2。当密封体160的厚度T1减少时，可以移除导电线150的牺牲区段154。另外，密封体160可以暴露出每条导电线150的第一焊接区段152中的一部分以及每条导电线150的第二焊接区段156中的一部分。换句话说，由于导电线150的牺牲区段154被移除，而第一焊接区段152的所述部分和第二焊接区段156的所述部分保留在密封体160中，因此导电线150不再是连续线。在此条件下，间隔件130不再通过导电线150耦合到第一电路载体110。因此，间隔件130不再电性连接到第一电路载体110。换句话说，在减少密封体160的厚度T1之后，间隔件130作为虚设间隔件。
在一些实施例中，密封体160可以通过研磨工艺(grinding process)移除。此外，研磨工艺可以是机械研磨、化学机械抛光(chemicalmechanicalpolishing，CMP)、蚀刻或其它合适的方法，但不限于此。此外，在减少密封体160的厚度T1之后，密封体160暴露出每个第一焊接区段152中的线部分152b的顶部表面以及每个第二焊接区段156中的顶部表面。在一些实施例中，在减少密封体160的厚度T1之后，每个第一焊接区段152中的线部分152b的顶部表面、每个第二焊接区段156中的顶部表面以及密封体160的顶部表面可以是共面的。其中，密封体160的顶部表面可以是最远离第一电路载体110的表面。换句话说，在减少密封体160的厚度T1之后，第一焊接区段152中的每一者的高度H2等于密封体160的厚度T2。
在一个实施例中，在减少密封体160的厚度T1之后，线部分152b的顶部表面可以用于与第一电路载体110的进一步电性连接。第二焊接区段156中的每一者的顶部表面可以是虚设路径。在一些其它实施例中，在减少密封体160的厚度T1之后，每个第一焊接区段152中的线部分152b的顶部表面以及每个第二焊接区段156中的顶部表面可以作为导电路径，以用于根据设计要求的进一步电性连接。另外，如图1E中所示的厚度减少工艺能够帮助整体封装结构中的总厚度减少，从而实现封装小型化。
参考图1F，第二封装结构200堆叠于第一封装结构100上以形成堆叠封装(POP)结构10。举例来说，第二封装结构200电性连接到第一封装结构100的导电线150。在一些实施例中，第二封装结构200可包含第二晶粒202，例如动态随机存取存储器(DRAM)或NAND快闪存储器。在一些其它实施例中，第二封装结构200中也可以利用其它有源装置。在一些实施例中，第二封装结构200可包含多个导电端子204，作为第二封装结构200与第一封装结构100之间的电性连接路径。此外，在一些实施例中，第二晶粒202和导电端子204可以通过类似连接于第一晶粒120与导电结构118之间的电路层而电性连接。
在一个实施例中，第二封装结构200可包含中心区(centralregion)CR以及围绕中心区CR的外围区(peripheralregion)PR。举例来说，第二晶粒202可以位于中心区CR中，且导电端子204可以设置于外围区PR中。此外，当第二封装结构200堆叠于第一封装结构100上时，第二封装结构200的中心区CR中的第二晶粒202可以对应于第一封装结构100的第一晶粒120而设置。另外，第二封装结构200的外围区PR中的导电端子204中的每一者可以分别设置于由第一封装结构100的密封体160暴露的导电线150的第一焊接区段152中的任一者上。在一个实施例中，第二封装结构200的中心区CR中的第二晶粒202可以交错于第一封装结构100的第一晶粒120。在另一实施例中，导电端子204可以设置于中心区CR和外围区PR两者中，以用于电性连接到第一封装结构100。在一些实施例中，导热层(thermal conductivelayer)(未示出)可以被设置成热接触(thermal contact)或热耦合(thermal coupled)于第二封装结构200与第一封装结构100之间，以用于增强散热效率。因此，在后续可靠性测试期间施加到POP结构10上的应力可以由导热层分担，以用于增加POP结构10的可靠性。
由于第一焊接区段152可以作为第一封装结构100与第二封装结构200之间的电性连接路径，因此可省略用于第一封装结构100与第二封装结构200之间的电性连接的额外中介层。从而可以减少POP结构10的总体厚度和制造成本。
图2A到图2F是说明根据本发明的另一实施例的POP结构的制造方法的剖面示意图。参考图2A，提供第一电路载体110且第一晶粒120接合于第一电路载体110上。图2A的实施例类似于图1A的实施例，因此在此省略详细描述。
参考图2B，间隔件330设置于第一电路载体110上且接合到第一晶粒120。举例来说，间隔件330包含作为散热金属板的导电板332。另外，间隔件330的导电板332可适合于执行后续的打线接合工艺。导电板332的材料可包含导热且导电材料，例如铝、铜或其合金。然而，导电板332的材料取决于设计要求，其在本发明中并不解释为限制。
此外，热粘着层(thermal adhesive layer)340可以设置于第一晶粒120与间隔件330之间。在一些实施例中，热粘着层340可包含拥有高热导率的晶粒附接组合物，例如银、覆银(silver coated)或铝氮化物颗粒(aluminum nitride particles)，其通过例如旋涂、喷墨印刷或其它合适的方法形成。然而，热粘着层340的材料和形成工艺在本发明中并不解释为限制。热粘着层340可以作为从第一晶粒120到间隔件330的直接热传导路径，并且在从第一晶粒120产生热的期间进一步增强散热效率。此外，热粘着层340可以提供结构支撑而不需要第一晶粒120与间隔件330之间的机械夹持。
参考图2C，间隔件330和第一电路载体110通过多个导电线350连接。导电线350的材料和形成方法可以类似于图1C中所示的导电线150的材料和形成方法。在此省略了详细描述。在本实施例中，导电线350可以连接于间隔件330的导电板332与第一电路载体110之间。另外，导电线350中的每一者可包含连接到第一电路载体110的焊接区段352以及连接于焊接区段352与间隔件330之间的牺牲区段354。换句话说，导电线350通过焊接区段352从第一电路载体110通过牺牲区段354连接到间隔件330。
另外，导电线350的焊接区段352中的每一者可包含耦合到第一电路载体110的焊接部分352a以及耦接到焊接部分352a的线部分352b。举例来说，每个焊接区段352中的的焊接部分352a可以取决于设计要求而通过球型接合、楔型接合或其它合适的接合而形成。焊接区段352的焊接部分352a和线部分352b的形成工艺可以类似于图1C中说明的第一焊接区段152的焊接部分152a和线部分152b的形成工艺，在此省略了详细描述。
导电线350的牺牲区段354中的每一者可包含弧形(arc-shape)部分354a以及尾部(tail)部分354b。牺牲区段354的形成工艺可以类似于导电线150的牺牲区段154和第二焊接区段156的形成工艺。这里省略了详细描述。另外，导电线350中的每一者的线弧高度H3可以是牺牲区段354的弧形部分354a的顶端与耦合到第一电路载体110的焊接区段352的焊接部分352a的底端之间的距离。线弧高度H3取决于打线机的类型和/或设计要求，但不限于此。
在一些实施例中，导电线350中的每一者的焊接区段352与第一电路载体110之间的角度θ3大于导电线350中的每一者的牺牲区段354与间隔件330之间的角度θ4。类似于图1C中说明的实施例，在本实施例中，角度θ3(类似于角度θ1)和角度θ4(类似于角度θ2)可以取决于线接合的类型和/或设计要求。
参考图2D，密封体160形成于第一电路载体110上，以密封第一晶粒120、间隔件330、粘着层340以及导电线350。图2D中说明的实施例的工艺类似于图1D中说明的实施例的工艺，在此省略了详细描述。参考图2E，减少密封体160的厚度T1直到移除导电线350中的每一者的至少一部分，以形成第一封装结构300。图2E中说明的实施例的减少方法类似于图1E中说明的实施例的减少方法，在此省略了详细描述。
在本实施例中，导电线350的牺牲区段354被移除。举例来说，密封体160的厚度T1减少到如图2E中所示的厚度T2。另外，在减少密封体160的厚度T1之后，密封体160暴露出间隔件330的导电板332的顶部表面332a。此外，密封体160暴露出每条导电线350的焊接区段352中的线部分352b的顶部表面。换句话说，导电线350的牺牲区段354被移除，而焊接区段352的一部分保留在密封体160中。在此条件下，间隔件330不连接到导电线350，并且不再通过导电线350电性连接到第一电路载体110。因此，间隔件330不再电性连接到第一电路载体110。在一些实施例中，在减少密封体160的厚度T1之后，每个焊接区段352中的线部分352b的顶部表面、间隔件330的导电板332的顶部表面332a以及密封体160的顶部表面是共面的。其中，密封体160的顶部表面可以是最远离第一电路载体110的表面。换句话说，在减少密封体160的厚度T1之后，焊接区段352中的每一者的高度H4等于密封体160的厚度T2。另外，如图2E中所示的厚度减少工艺能够辅助封装结构整体的总厚度减少，从而实现封装小型化。此外，包含导电板332的间隔件330可以首先作为用于形成导电线350的导电接合垫，如图2D中所示。随后，由于在减少密封体160的厚度T1之后移除了导电线350的牺牲区段354，因此，间隔件330是电性浮置的(electrically floated)。据此，包含导电板332的间隔件330可以用作第一封装结构300中的散热元件。
参考图2F，第二封装结构200堆叠于第一封装结构300上，以形成POP结构20。举例来说，第二封装结构200电性连接到第一封装结构100的导电线350。在一些实施例中，当第二封装结构200堆叠于第一封装结构300上时，第二封装结构200的中心区CR中的第二晶粒202可以对应于第一封装结构300的第一晶粒120而设置。另外，第二封装结构200的外围区PR中的导电端子204中的每一者可以设置于被密封体160暴露出的第一封装结构300的导电线350的焊接区段352中的任一者上。在一个实施例中，第二封装结构200的中心区CR中的第二晶粒202可以交错于第一封装结构300的第一晶粒120。在另一实施例中，导电端子204可以设置于第二封装结构200的中心区CR和外围区PR两者中，以电性连接到第一封装结构300。
基于上述，设置于晶粒上的间隔件有利于导电线的形成工艺。此外，由于在减少密封体的厚度期间移除导电线的至少一部分，因此，保留在密封体中的导电线的其余部分可以作为第一封装结构与第二封装结构之间的电性连接路径。因此，在第一封装结构与第二封装结构之间不必额外设置用于电性连接的中介层。因此，不仅可以减少POP结构的总体厚度，也可以减少制造成本。另外，密封体可以暴露出间隔件，因此在减少密封体的厚度之后，间隔件可以作为散热元件。据此，可以开启各种POP结构设计的可能性。
对于所属领域的技术人员将显而易见的是，在不脱离本发明的范围或精神的情况下，可以对本发明的结构进行各种修改和变化。鉴于以上内容，希望本发明涵盖本发明的修改和变化，只要所述修改和变化落入所附权利要求和其等效物的范围内。

Claims (10)

1.一种堆叠封装结构的制造方法，其特征在于，包括：
接合晶粒于第一电路载体上；
设置间隔件在所述晶粒上；
通过多个导电线连接所述间隔件和所述第一电路载体；
形成密封体以密封所述晶粒、所述间隔件以及所述导电线；
减少所述密封体的厚度直到移除所述导电线中的每一者的至少一部分以形成第一封装结构；以及
堆叠第二封装结构在所述第一封装结构上，其中所述第二封装结构电性连接到所述导电线。
2.根据权利要求1所述的堆叠封装结构的制造方法，其特征在于，所述间隔件包括第二电路载体，在减少所述密封体的所述厚度之前，所述导电线连接于所述第二电路载体与所述第一电路载体之间。
3.根据权利要求2所述的堆叠封装结构的制造方法，其特征在于，在减少所述密封体的所述厚度之前，所述导电线中的每一者包括连接到所述第一电路载体的第一焊接区段以及连接到所述间隔件的第二焊接区段，所述导电线通过所述第一焊接区段从所述第一电路载体通过所述第二焊接区段连接到所述间隔件。
4.根据权利要求3所述的堆叠封装结构的制造方法，其特征在于，在减少所述密封体的所述厚度之前，所述导电线中的每一者进一步包括连接于所述第一焊接区段与所述第二焊接区段之间的牺牲区段，当减少所述密封体的所述厚度时，所述导电线的所述牺牲区段被移除，在移除所述导电线的所述牺牲区段之后，所述间隔件是电性浮置的。
5.根据权利要求4所述的堆叠封装结构的制造方法，其特征在于，所述第二封装结构包括多个导电端子，所述第二封装结构的所述导电端子中的每一者分别设置于由所述密封体暴露的所述导电线的所述第一焊接区段中的任一者上。
6.根据权利要求1所述的堆叠封装结构的制造方法，其特征在于，所述间隔件包括导电板。
7.根据权利要求6所述的堆叠封装结构的制造方法，其特征在于，在减少所述密封体的所述厚度之后，所述间隔件的表面从所述密封体暴露。
8.根据权利要求6所述的堆叠封装结构的制造方法，其特征在于，在减少所述密封体的所述厚度之前，所述导电线中的每一者包括连接到所述第一电路载体的焊接区段以及连接于所述焊接区段与所述间隔件之间的牺牲区段，所述导电线通过所述焊接区段从所述第一电路载体通过所述牺牲区段连接到所述间隔件。
9.根据权利要求8所述的堆叠封装结构的制造方法，其特征在于，当减少所述密封体的所述厚度时，所述导电线的所述牺牲区段被移除，在移除所述导电线的所述牺牲区段之后，所述间隔件是电性浮置的。
10.根据权利要求8所述的堆叠封装结构的制造方法，其特征在于，所述第二封装结构包括多个导电端子，所述第二封装结构的所述导电端子中的每一者分别设置于由所述密封体暴露的所述焊接区段中的任一者上。
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