TW202002209A - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TW202002209A
TW202002209A TW108101599A TW108101599A TW202002209A TW 202002209 A TW202002209 A TW 202002209A TW 108101599 A TW108101599 A TW 108101599A TW 108101599 A TW108101599 A TW 108101599A TW 202002209 A TW202002209 A TW 202002209A
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semiconductor substrate
semiconductor
substrate
circuit
electrically connected
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TW108101599A
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TWI688067B (zh
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築山慧至
青木秀夫
川戶雅敏
三浦正幸
福田昌利
本間荘一
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日商東芝記憶體股份有限公司
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Abstract

實施形態提供一種提高了半導體晶片間之接合可靠性之半導體裝置及其製造方法。 實施形態之半導體裝置具備：配線基板；第一半導體基板，其係設置於上述配線基板之上方，且於表面形成有第一半導體電路之記憶體基板；第二半導體基板，其係設置於上述第一半導體基板與上述配線基板之間，較上述第一半導體基板厚，且於表面形成有第二半導體電路之記憶體基板；凸塊，其設置於上述第一半導體基板與上述第二半導體基板間之間，將上述第一半導體基板與上述第二半導體基板電性連接；第一接著性樹脂，其設置於上述第一半導體基板與上述第二半導體基板之間，將上述第一半導體基板與第二半導體基板接著；及密封樹脂，其形成於上述第一半導體基板與第二半導體基板之間、上述第二半導體基板與上述配線基板之間、及上述第一半導體基板與第二半導體基板之周圍，將上述第一半導體基板與第二半導體基板密封。

Description

半導體裝置及其製造方法
本發明之實施形態係關於一種半導體裝置及其製造方法。
為了實現半導體裝置之小型化或高功能化，開發有將以貫通通孔與微凸塊相互連接之複數個半導體記憶體基板積層而成之半導體封裝。已知有一種半導體封裝，其於使形成有半導體元件之面朝向上方相互積層而成之半導體記憶體基板積層構造中，使最下層之記憶體基板之厚度大於其他記憶體基板之厚度。
實施形態提供一種提高了半導體基板間之接合可靠性之半導體裝置及其製造方法。
實施形態之半導體裝置具備：配線基板；第一半導體基板，其係設置於上述配線基板之上方，且於表面形成有第一半導體電路之記憶體基板；第二半導體基板，其係設置於上述第一半導體基板與上述配線基板之間，較上述第一半導體基板厚，且於表面形成有第二半導體電路之記憶體基板；凸塊，其設置於上述第一半導體基板與上述第二半導體基板間之間，將上述第一半導體基板與上述第二半導體基板電性連接；第一接著性樹脂，其設置於上述第一半導體基板與上述第二半導體基板之間，將上述第一半導體基板與第二半導體基板接著；及密封樹脂，其形成於上述第一半導體基板與第二半導體基板之間、上述第二半導體基板與上述配線基板之間、及上述第一半導體基板與第二半導體基板之周圍，將上述第一半導體基板與第二半導體基板密封。
又，另一實施形態之半導體裝置具備：配線基板；積層體，其設置於上述配線基板，包括形成有半導體電路之複數片半導體基板；第一半導體基板，其係上述積層體中距離上述配線基板最遠地設置，且於表面形成有第一半導體電路之記憶體基板；第二半導體基板，其係上述積層體中距離上述配線基板最近地設置，較上述第一半導體基板厚，且於表面形成有第二半導體電路之記憶體基板；凸塊，其將上述複數片半導體基板分別電性連接；接著性樹脂，其設置於上述複數片半導體基板之間，將上述複數片半導體基板分別接著；及密封樹脂，其形成於上述複數片半導體基板之間、及上述複數片半導體基板之周圍，將上述複數片半導體基板密封。
又，亦可進而具備第三半導體基板，該第三半導體基板設置於上述第二半導體基板與上述配線基板之間，較上述第一半導體基板厚，且於表面形成有第三半導體電路，上述第二半導體基板經由設置於上述第二半導體基板與第三半導體基板之間之凸塊而與上述第三半導體基板電性連接。
又，亦可為形成有上述第一半導體電路之面與形成有上述第二半導體電路之面朝向相同方向，且與形成有上述第三半導體電路之面相向。
又，上述第三半導體基板亦可為外形較上述第一半導體基板及上述第二半導體基板小之基板。
又，亦可為上述第二半導體基板具有：第二有機保護膜，其以覆蓋上述第二半導體電路之方式設置；第二再配線層，其形成於上述第二有機保護膜之內部且與上述第二半導體電路電性連接；及第二焊墊，其與上述第二再配線層電性連接，且設置於將上述第一半導體基板與上述第二半導體基板積層之方向設為第一方向時自上述第一方向觀察時不與上述第三半導體基板重疊之位置；並且具備將上述第二焊墊與上述配線基板電性連接且直徑較上述凸塊大之大凸塊。
又，亦可為上述第一半導體基板具有：第一有機保護膜，其以覆蓋上述第一半導體電路之方式設置；第一再配線層，其形成於上述第一有機保護膜之內部且與上述第一半導體電路電性連接；及第一焊墊，其與上述第一再配線層電性連接；上述第二半導體基板具有貫通上述第二半導體基板且與上述第二半導體電路電性連接之第一貫通通孔，且上述第一貫通通孔與上述第一焊墊經由凸塊電性連接。
又，亦可為上述第三半導體基板具有：第三有機保護膜，其以覆蓋上述第三半導體電路之方式設置；第三再配線層，其形成於上述第三有機保護膜之內部且與上述第三半導體電路電性連接；及第三焊墊，其與上述第三再配線層電性連接；上述第二半導體基板具有第四焊墊，該第四焊墊與上述第二再配線層電性連接，設置於自上述第一方向觀察時與上述第三半導體基板重疊之位置，且面積較上述第二焊墊小，並且具備將上述第三焊墊與上述第四焊墊電性連接之上述凸塊。
又，亦可具備：第二接著性樹脂，其設置於上述第一半導體基板之與形成有上述第一半導體電路之面為相反側之面；及支持體，其經由上述第二接著性樹脂與上述第一半導體基板接著，且外形較上述第一半導體基板之外形大。
根據實施形態，可提供一種提高了半導體基板間之接合可靠性之半導體裝置。
以下，對用以實施發明之實施形態進行說明。
參照圖1～3對本實施形態之半導體裝置進行說明。再者，於圖式之記載中，相同部分以相同符號表示。但是，圖式係厚度與平面尺寸之關係、比率等與實物不同之模式性之圖。
利用圖1對本實施形態之半導體裝置之構成進行說明。圖1係表示本實施形態之半導體裝置之構成之剖視圖。
如圖1所示，本實施形態之半導體裝置100具有第一半導體基板1、第二半導體基板2、第三半導體基板3、及第四半導體基板4分別積層而成之半導體基板之積層構造。此處，第一半導體基板1、第二半導體基板2、及第三半導體基板3分別為NAND(Not AND，反及)快閃記憶體等記憶體基板，第四半導體基板4為介面(IF)基板。IF基板具備用以於記憶體基板與外部器件之間進行資料通信之IF電路。
第一半導體基板1、第二半導體基板2、第三半導體基板3、及第四半導體基板4分別具有矽等半導體基板、以及設置於半導體基板上之半導體元件(省略圖示)、半導體電路配線(省略圖示)、層間絕緣膜(省略圖示)。
於圖5中表示半導體基板3之放大圖。
半導體電路16包含半導體元件、半導體電路配線、及層間絕緣膜。此處，若將半導體基板之設置有半導體元件之表面設為半導體電路面(電路面)，將相反側之表面設為背面，則第一半導體基板1、第二半導體基板2、及第三半導體基板3係以半導體基板之半導體電路面均朝向相同方向(上方)之方式積層，另一方面，第四半導體基板4以半導體基板之半導體電路面朝向相反方向(下方)之方式積層。第四半導體基板4之半導體電路面與第三半導體基板3之半導體電路面彼此相向。
第一半導體基板1之厚度較第二半導體基板2、第三半導體基板3、及第四半導體基板4之厚度薄。藉由以第一半導體基板1之半導體基板較第二半導體基板2、第三半導體基板3、及第四半導體基板4之各個半導體基板薄之方式進行薄膜加工，作為基板整體而第一半導體基板1較第二半導體基板2、第三半導體基板3、第四半導體基板4薄。薄膜加工可藉由半導體基板之研削等而實現。例如，將第一半導體基板1之厚度設為未達30 μm，將第二半導體基板2、第三半導體基板3、及第四半導體基板4之厚度設為30 μm～50 μm。
如圖5所示，於第一半導體基板1、第二半導體基板2、第三半導體基板3之半導體電路16之上分別形成有有機保護膜12。有機保護膜12可應用各種有機絕緣材料，例如可使用聚醯亞胺樹脂膜、酚樹脂膜、丙烯酸系樹脂膜、聚苯并㗁唑樹脂膜、聚苯并環丁烯樹脂膜等。有機保護膜12可為單層，亦可為複數層。有機保護膜12係用以保護半導體基板之內部電路配線之鈍化膜等。
有機保護膜12亦可於其中形成再配線層17。再配線層17與半導體電路16電性連接。再配線層17亦與設置於有機保護膜12之外部之焊墊18電性連接。即，焊墊18經由再配線層17與半導體電路16電性連接。
第一半導體基板1、第二半導體基板2、第三半導體基板3分別經由凸塊5及貫通通孔6而電性連接。第四半導體基板4經由凸塊5及第三半導體基板3之半導體電路面16上之有機保護膜12內所設置之再配線層17而與第三半導體基板3電性連接。作為凸塊5之材料，可使用Cu、Ag、Bi、In等與Sn之合金、或Cu、Ni、Au、Ag、Pd、Sn等。設置於各半導體基板間之凸塊5為微凸塊，凸塊間之間距為10～100 μm，凸塊之直徑為5～50 μm左右。貫通通孔6包含Cu、Ni或W等導電材料，且以分別貫通第二半導體基板2及第三半導體基板3之方式設置。半導體基板之半導體電路16中包含之電路配線或元件與貫通通孔6電性連接。又，貫通通孔6亦可貫通半導體電路16而直接連接於再配線層17。藉由貫通通孔6與凸塊5接合而將各半導體基板之電路配線或元件電性連接。再者，凸塊5接合於各半導體基板表面中設置於有機保護膜12之開口區域、例如焊墊18露出之表面。
於第一半導體基板1、第二半導體基板2、第三半導體基板3、及第四半導體基板4各自之間形成兼用作止動部之接著性樹脂7。兼用作止動部之接著性樹脂7作為保持所積層之各半導體基板之間隙之止動構件發揮功能，與此同時，作為於填充密封樹脂之前階段將半導體基板間接著之接著構件發揮功能。接著性樹脂7由具有感光性或熱固性之樹脂形成。作為感光性及熱固性樹脂之具體例，可列舉感光性接著劑樹脂之類之含有感光劑之熱固性樹脂，例如較佳為由使用環氧樹脂、聚醯亞胺樹脂、丙烯酸系樹脂、酚樹脂等之熱固性樹脂形成。接著性樹脂7之熱膨脹係數與半導體基板之用作半導體基板之矽基板或有機保護膜12不同。
第三半導體基板3經由電路面上之有機保護膜12內所設置之再配線層及大凸塊8而與配線基板9電性連接。第四半導體基板4亦經由凸塊5及再配線層而與配線基板9電性連接。大凸塊8與凸塊5相比直徑較大，使用與凸塊5相同之材料。配線基板9包含樹脂材料，且於內部實施銅等之配線。配線基板9係擴展至半導體基板3正下方之區域之外側之構造，亦能夠搭載半導體基板3以外之半導體基板。於配線基板9形成有焊球(BGA(Ball Grid Array，球狀柵格陣列))10。半導體基板經由大凸塊8、配線基板9之內部配線及焊球10而與外部器件電性連接。
圖5中，第三半導體基板3具有之焊墊19設置於自第一半導體基板1與第二半導體基板2積層之方向觀察時不與第四半導體基板4重疊之位置。焊墊19與焊墊18相比，與凸塊5接觸之面積較大。焊墊18與直徑5～50 μm左右之微凸塊連接。因此，焊墊18之直徑亦為5～50 μm左右。
第一半導體基板1、第二半導體基板2亦可具有焊墊18與焊墊19。第一半導體基板1、第二半導體基板2由於無須經由大凸塊8與配線基板9連接，故而亦可不具有焊墊19。
於配線基板9上之各半導體基板之間及其等之周圍，形成有環氧樹脂等密封樹脂11，以將半導體基板模塑。於各半導體基板間，密封樹脂11填充於有機保護膜12上未形成接著性樹脂7之區域。
接下來，參照圖2及3，對本實施形態之半導體裝置之製造方法進行說明。
首先，如圖2所示，準備於半導體基板上依次形成半導體電路、有機保護膜12而成之第一半導體基板1，並使半導體電路面朝向上方而將半導體基板1搭載於引線框架13上。於有機保護膜12之一部分設置開口，使半導體基板1之電路之一部分例如電極墊露出。第一半導體基板1之半導體基板藉由背面研削等而薄膜化。
繼而，如圖3所示，於第一半導體基板1上依次積層第二半導體基板2、第三半導體基板3、及第四半導體基板4。於第二半導體基板2及第三半導體基板3，預先設置有貫通半導體基板之貫通通孔6及位於貫通通孔6之前端之凸塊5，且於與凸塊5相同之基板背面設置有接著性樹脂7。於第四半導體基板4之電路面亦形成有凸塊5及接著性樹脂7。於第二半導體基板2及第三半導體基板3之半導體電路面上形成有機保護膜12，於有機保護膜12之一部分設置開口而使電路之一部分、例如焊墊露出。此處，第二半導體基板2、第三半導體基板3、及第四半導體基板4之厚度大於第一半導體基板1之厚度。
將第二半導體基板2積層於第一半導體基板1時，將第二半導體基板2之凸塊5以接合於第一半導體基板1之焊墊之方式對準之後，將兩基板熱壓接。熱壓接時之溫度例如為250度至280度。另一方面，第二半導體基板2之接著性樹脂7亦與第一半導體基板1接觸，並於凸塊加熱之前或同時進行加熱，藉此，可確保第二半導體基板2與第一半導體基板1之接著以及基板間距離。將第三半導體基板3積層於第二半導體基板2時，將第四半導體基板4積層於第三半導體基板3時，亦可利用相同之方法將基板彼此接合。再者，接著性樹脂7亦可形成於接合之下層之半導體基板，於該情形時，亦可於上層之半導體基板不設置接著性樹脂7。
於加熱半導體基板時，有時會因有機保護膜由熱引起形狀變化而導致半導體基板產生翹曲。半導體基板之矽基板之熱膨脹係數為3 ppm左右，與此相對，有機保護膜之熱膨脹係數相對較大，例如聚醯亞胺樹脂之熱膨脹係數為35 ppm左右。此處，於經積層之半導體基板之一部分、例如成為基板積層時之基底之最下層之半導體基板較其他基板厚之情形時，無法追隨其他半導體基板之翹曲。由於最下層之半導體基板與其上層之半導體基板之翹曲量不同，故而形成於其等半導體基板間之接著性樹脂會擴展，其結果，將兩基板接合之凸塊有斷裂之虞。尤其微凸塊等直徑較小之凸塊由於機械強度較弱，故而斷裂之可能性較高。另一方面，本實施形態之半導體裝置由於成為基板積層時之基底之最下層之第一半導體基板1之厚度較所積層之第二半導體基板2、第三半導體基板3、第四半導體基板4薄，故而追隨第二半導體基板2、第三半導體基板3、第四半導體基板4之翹曲，於第一半導體基板亦產生翹曲，從而可防止基板間之接著性樹脂7擴展，其結果，可防止將第一半導體基板1與其上層之第二半導體基板2接合之凸塊斷裂。
又，與將全部為相同厚度之半導體基板積層之情形相比，藉由預先使最下層之第一半導體基板1較其他半導體基板薄，可抑制第一至第三半導體基板積層體整體之翹曲量，例如能夠使翹曲量為數十μm以下。因此，可抑制將半導體基板積層體與配線基板9連接之大凸塊8所受之壓力，從而防止凸塊斷裂。於圖3及圖3之後之圖中，雖省略圖示，但可將經積層之半導體基板群以第三半導體基板3之電路形成面與配線基板9對向之方式經由大凸塊8接合於配線基板，並利用密封樹脂進行模塑，藉此製造本實施形態之半導體裝置。密封樹脂之加熱硬化溫度例如為180度左右。
(變化例)參照圖4對實施形態之半導體裝置之變化例進行說明。再者，於圖4之記載中，與圖1相同之部分以相同符號表示。但是，圖式係厚度與平面尺寸之關係、比率等與實物不同之模式性之圖。
本變化例之半導體裝置與實施形態之半導體裝置之不同之處在於第一半導體基板經由DAF(Die Attach Film，晶圓黏結膜)而形成於支持體。其他構成相同而省略說明。
如圖4所示，本變化例之半導體裝置200之第一半導體基板1經由DAF15而形成於支持體14上。支持體14係引線框架或矽基板等支持第一半導體基板1之基板。DAF係含有有機系樹脂材料之膜材，將支持體14與第一半導體基板接著。
本變化例中，第一半導體基板1之厚度亦小於第二、第三、第四半導體基板之厚度，因此，可防止基板加熱壓接時之伴隨基板之翹曲產生之第一半導體基板1與第二半導體基板2間之凸塊5之斷裂。
又，可於在支持體14上設置有複數個半導體基板之狀態下將半導體基板搭載於配線基板9，因此，積層基板之搬送、操作較容易。
半導體基板之積層數為4層，但並不限於此，積層數可為更多，亦可為更少。
以上，對本發明之實施形態進行了說明，但本實施形態係作為示例而提出，並不意圖限定發明之範圍。新穎之實施形態能以其他多種形態實施，能夠於不脫離發明主旨之範圍內進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍或主旨中，並且包含於申請專利範圍所記載之發明及其均等之範圍內。
[相關申請] 本申請享有以日本專利申請2018-118175號(申請日：2018年6月21日)為基礎申請之優先權。本申請藉由參照該基礎申請而包含基礎申請之全部內容。
1‧‧‧第一半導體基板 2‧‧‧第二半導體基板 3‧‧‧第三半導體基板 4‧‧‧第四半導體基板 5‧‧‧凸塊 6‧‧‧貫通通孔 7‧‧‧接著性樹脂 8‧‧‧大凸塊 9‧‧‧配線基板 10‧‧‧焊球 11‧‧‧密封樹脂 12‧‧‧有機保護膜 13‧‧‧引線框架 14‧‧‧支持體 15‧‧‧DAF 16‧‧‧半導體電路 17‧‧‧再配線層 18、19‧‧‧焊墊 100、200‧‧‧半導體裝置
圖1係說明實施形態之半導體裝置之構成之圖。 圖2係說明實施形態之半導體裝置之製造方法之圖。 圖3係說明實施形態之半導體裝置之製造方法之圖。 圖4係說明實施形態之變化例之半導體裝置之構成之圖。 圖5係說明半導體基板之圖。
1‧‧‧第一半導體基板
2‧‧‧第二半導體基板
3‧‧‧第三半導體基板
4‧‧‧第四半導體基板
5‧‧‧凸塊
6‧‧‧貫通通孔
7‧‧‧接著性樹脂
8‧‧‧大凸塊
9‧‧‧配線基板
10‧‧‧焊球
11‧‧‧密封樹脂
12‧‧‧有機保護膜
100‧‧‧半導體裝置

Claims (11)

  1. 一種半導體裝置，其具備： 配線基板； 第一半導體基板，其係設置於上述配線基板之上方，且於表面形成有第一半導體電路之記憶體基板； 第二半導體基板，其係設置於上述第一半導體基板與上述配線基板之間，較上述第一半導體基板厚，且於表面形成有第二半導體電路之記憶體基板； 凸塊，其設置於上述第一半導體基板與上述第二半導體基板間之間，將上述第一半導體基板與上述第二半導體基板電性連接； 第一接著性樹脂，其設置於上述第一半導體基板與上述第二半導體基板之間，將上述第一半導體基板與第二半導體基板接著；及 密封樹脂，其形成於上述第一半導體基板與第二半導體基板之間、上述第二半導體基板與上述配線基板之間、及上述第一半導體基板與第二半導體基板之周圍，將上述第一半導體基板與第二半導體基板密封。
  2. 一種半導體裝置，其具備： 配線基板； 積層體，其設置於上述配線基板，包括形成有半導體電路之複數片半導體基板； 第一半導體基板，其係上述積層體中距離上述配線基板最遠地設置，且於表面形成有第一半導體電路之記憶體基板； 第二半導體基板，其係上述積層體中距離上述配線基板最近地設置，較上述第一半導體基板厚，且於表面形成有第二半導體電路之記憶體基板； 凸塊，其將上述複數片半導體基板分別電性連接； 接著性樹脂，其設置於上述複數片半導體基板之間，將上述複數片半導體基板分別接著；及 密封樹脂，其形成於上述複數片半導體基板之間、及上述複數片半導體基板之周圍，將上述複數片半導體基板密封。
  3. 如請求項1或2之半導體裝置，其進而具備第三半導體基板，該第三半導體基板設置於上述第二半導體基板與上述配線基板之間，較上述第一半導體基板厚，且於表面形成有第三半導體電路，且 上述第二半導體基板經由設置於上述第二半導體基板與第三半導體基板之間之凸塊而與上述第三半導體基板電性連接。
  4. 如請求項3之半導體裝置，其中形成有上述第一半導體電路之面與形成有上述第二半導體電路之面朝向相同方向，且與形成有上述第三半導體電路之面相向。
  5. 如請求項4之半導體裝置，其中上述第三半導體基板係外形較上述第一半導體基板及上述第二半導體基板小之基板。
  6. 如請求項5之半導體裝置，其中上述第二半導體基板具有：第二有機保護膜，其以覆蓋上述第二半導體電路之方式設置；第二再配線層，其形成於上述第二有機保護膜之內部且與上述第二半導體電路電性連接；及第二焊墊，其與上述第二再配線層電性連接，且設置於將上述第一半導體基板與上述第二半導體基板積層之方向設為第一方向時自上述第一方向觀察時不與上述第三半導體基板重疊之位置；且 具備將上述第二焊墊與上述配線基板電性連接且直徑較上述凸塊大之大凸塊。
  7. 如請求項6之半導體裝置，其中上述第一半導體基板具有： 第一有機保護膜，其以覆蓋上述第一半導體電路之方式設置； 第一再配線層，其形成於上述第一有機保護膜之內部且與上述第一半導體電路電性連接；及 第一焊墊，其與上述第一再配線層電性連接； 上述第二半導體基板具有貫通上述第二半導體基板且與上述第二半導體電路電性連接之第一貫通通孔，且 上述第一貫通通孔與上述第一焊墊經由凸塊電性連接。
  8. 如請求項7之半導體裝置，其中上述第三半導體基板具有： 第三有機保護膜，其以覆蓋上述第三半導體電路之方式設置； 第三再配線層，其形成於上述第三有機保護膜之內部且與上述第三半導體電路電性連接；及 第三焊墊，其與上述第三再配線層電性連接； 上述第二半導體基板具有第四焊墊，該第四焊墊與上述第二再配線層電性連接，設置於自上述第一方向觀察時與上述第三半導體基板重疊之位置，且面積較上述第二焊墊小，且 具備將上述第三焊墊與上述第四焊墊電性連接之上述凸塊。
  9. 如請求項8之半導體裝置，其具備： 第二接著性樹脂，其設置於上述第一半導體基板之與形成有上述第一半導體電路之面為相反側之面；及 支持體，其經由上述第二接著性樹脂與上述第一半導體基板接著，且外形較上述第一半導體基板之外形大。
  10. 一種半導體裝置之製造方法，其包含如下步驟： 準備第一半導體基板及較上述第一半導體基板厚之第二半導體基板； 將介置於上述第一半導體基板與第二半導體基板間之凸塊及接著性樹脂加熱，對上述第一半導體基板與第二半導體基板進行熱壓接而形成積層體；及 於上述加熱後，於上述第一半導體基板與上述第二半導體基板之間、及上述第一半導體基板與第二半導體基板之周圍形成密封樹脂，將上述第一半導體基板及第二半導體基板密封。
  11. 如請求項10之半導體裝置之製造方法，其進而包含如下步驟： 準備配線基板、及外形較上述第二半導體基板小之第三半導體基板； 對上述積層體與上述第三半導體基板進行熱壓接；及 將上述積層體熱壓接於上述配線基板；且 上述密封樹脂亦形成於上述第二半導體基板與上述第三半導體基板之間、及上述第三半導體基板與上述配線基板之間。
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KR100467946B1 (ko) * 1997-01-24 2005-01-24 로무 가부시키가이샤 반도체 칩의 제조방법
JP2000243900A (ja) 1999-02-23 2000-09-08 Rohm Co Ltd 半導体チップおよびそれを用いた半導体装置、ならびに半導体チップの製造方法
JP2002076251A (ja) 2000-08-30 2002-03-15 Hitachi Ltd 半導体装置
JP2002176137A (ja) 2000-09-28 2002-06-21 Toshiba Corp 積層型半導体デバイス
JP4324768B2 (ja) 2003-07-10 2009-09-02 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
KR100880242B1 (ko) * 2007-01-16 2009-01-28 삼성전자주식회사 반도체 소자 적층 패키지 및 그 형성 방법
JP2010129958A (ja) 2008-12-01 2010-06-10 Seiko Epson Corp 半導体装置及び半導体装置の製造方法
JP2010258227A (ja) 2009-04-24 2010-11-11 Toshiba Corp 半導体装置の製造方法
US8114707B2 (en) * 2010-03-25 2012-02-14 International Business Machines Corporation Method of forming a multi-chip stacked structure including a thin interposer chip having a face-to-back bonding with another chip
JP2012015398A (ja) * 2010-07-02 2012-01-19 Toshiba Corp 半導体装置
JP5936968B2 (ja) * 2011-09-22 2016-06-22 株式会社東芝 半導体装置とその製造方法
KR20150066184A (ko) * 2013-12-06 2015-06-16 삼성전자주식회사 반도체 패키지 및 그 제조방법
JP6131875B2 (ja) 2014-02-18 2017-05-24 株式会社デンソー 半導体パッケージ
JP6276151B2 (ja) * 2014-09-17 2018-02-07 東芝メモリ株式会社 半導体装置
KR20170019676A (ko) * 2015-08-12 2017-02-22 삼성전자주식회사 반도체 장치의 제조 방법
JP2019220621A (ja) * 2018-06-21 2019-12-26 キオクシア株式会社 半導体装置及びその製造方法

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