JP2010129958A - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
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Abstract
【解決手段】複数の外部端子VDD、VSS、Pin1、Pin2を有し、複数の半導体基板10、20、30を積層して含む半導体装置であって、半導体基板のうち少なくとも1つを貫通し、半導体装置のいずれかの外部端子と電気的に接続する貫通電極51、52、53、54と、いずれか1つの半導体基板に設けた複数の静電放電保護回路41、42、43とを含み、貫通電極51、52、53、54は、複数の静電放電保護回路41、42、43のいずれかと電気的に接続され、複数の静電放電保護回路41、42、43は、貫通電極51、52、53、54のいずれかと電気的に接続されている静電放電保護回路41、42、43が設けられる半導体基板は、最下層又は最上層に積層された半導体基板であってもよい。
【選択図】図1
Description
複数の外部端子を有し、複数の半導体基板を積層して含む半導体装置であって、
前記半導体基板のうち少なくとも1つを貫通し、前記半導体装置のいずれかの外部端子と電気的に接続する貫通電極と、
いずれか1つの前記半導体基板に設けた複数の静電放電保護回路とを含み、
前記貫通電極は、前記複数の静電放電保護回路のいずれかと電気的に接続され、
前記複数の静電放電保護回路は、前記貫通電極と電気的に接続されていることを特徴とする。
前記貫通電極を複数含み、
前記複数の静電放電保護回路は、前記複数の貫通電極のいずれかと電気的に接続されていてもよい。
前記複数の静電放電保護回路が設けられている前記半導体基板は、最下層又は最上層に積層された半導体基板であってもよい。
前記複数の静電放電保護回路が設けられている前記半導体基板は、最も微細化されていない製造プロセスで製造されていてもよい。
前記複数の静電放電保護回路が設けられていない少なくとも1つの半導体基板に、少なくとも1つの前記貫通電極と電気的に接続し、前記静電放電保護回路よりも静電放電保護機能の低い簡易静電放電保護回路が設けられていてもよい。
複数の外部端子を有し、複数の半導体基板を積層して含む半導体装置の製造方法であって、
いずれか1つの前記半導体基板に複数の静電放電保護回路を設け、前記半導体基板のうち少なくとも1つを貫通し、前記半導体装置のいずれかの外部端子及び前記複数の静電放電保護回路のいずれかと電気的に接続する貫通電極を設けるとともに、前記複数の静電放電保護回路を前記貫通電極と電気的に接続することを特徴とする。
上述の実施の形態で説明した半導体装置の構成に加えて、静電放電保護回路が設けられていない少なくとも1つの半導体基板に、少なくとも1つの貫通電極と電気的に接続し、静電放電保護回路よりも静電放電保護機能の低い簡易静電放電保護回路を設けてもよい。
Claims (6)
- 複数の外部端子を有し、複数の半導体基板を積層して含む半導体装置であって、
前記半導体基板のうち少なくとも1つを貫通し、前記半導体装置のいずれかの外部端子と電気的に接続する貫通電極と、
いずれか1つの前記半導体基板に設けた複数の静電放電保護回路とを含み、
前記貫通電極は、前記複数の静電放電保護回路のいずれかと電気的に接続され、
前記複数の静電放電保護回路は、前記貫通電極と電気的に接続されていることを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記貫通電極を複数含み、
前記複数の静電放電保護回路は、前記複数の貫通電極のいずれかと電気的に接続されていることを特徴とする半導体装置。 - 請求項1及び2のいずれかに記載の半導体装置において、
前記複数の静電放電保護回路が設けられている前記半導体基板は、最下層又は最上層に積層された半導体基板であることを特徴とする半導体装置。 - 請求項1乃至3のいずれかに記載の半導体装置において、
前記複数の静電放電保護回路が設けられている前記半導体基板は、最も微細化されていない製造プロセスで製造されていることを特徴とする半導体装置。 - 請求項1乃至4のいずれかに記載の半導体装置において、
前記複数の静電放電保護回路が設けられていない少なくとも1つの半導体基板に、少なくとも1つの前記貫通電極と電気的に接続し、前記静電放電保護回路よりも静電放電保護機能の低い簡易静電放電保護回路が設けられていることを特徴とする半導体装置。 - 複数の外部端子を有し、複数の半導体基板を積層して含む半導体装置の製造方法であって、
いずれか1つの前記半導体基板に複数の静電放電保護回路を設け、前記半導体基板のうち少なくとも1つを貫通し、前記半導体装置のいずれかの外部端子及び前記複数の静電放電保護回路のいずれかと電気的に接続する貫通電極を設けるとともに、前記複数の静電放電保護回路を前記貫通電極と電気的に接続することを特徴とする半導体装置の製造方法。
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JP2008306228A JP2010129958A (ja) | 2008-12-01 | 2008-12-01 | 半導体装置及び半導体装置の製造方法 |
US12/627,652 US8338890B2 (en) | 2008-12-01 | 2009-11-30 | Semiconductor device and method for manufacturing semiconductor device |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010225701A (ja) * | 2009-03-19 | 2010-10-07 | Toshiba Corp | 三次元積層型半導体集積回路及びその製造方法 |
WO2012121255A1 (ja) * | 2011-03-09 | 2012-09-13 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR20150064117A (ko) * | 2012-10-05 | 2015-06-10 | 퀄컴 인코포레이티드 | 적층된 멀티-칩 집적 회로들을 위한 정전 보호 |
JP2017152648A (ja) * | 2016-02-26 | 2017-08-31 | 東芝メモリ株式会社 | 半導体装置 |
WO2023166674A1 (ja) * | 2022-03-03 | 2023-09-07 | 株式会社ソシオネクスト | 半導体集積回路装置 |
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KR101179268B1 (ko) * | 2010-08-05 | 2012-09-03 | 에스케이하이닉스 주식회사 | 관통 비아들을 통한 칩선택이 가능한 반도체 패키지 |
US9627337B2 (en) | 2011-03-31 | 2017-04-18 | Novatek Microelectronics Corp. | Integrated circuit device |
TWI424544B (zh) * | 2011-03-31 | 2014-01-21 | Novatek Microelectronics Corp | 積體電路裝置 |
CN104576580B (zh) * | 2011-04-12 | 2017-10-03 | 联咏科技股份有限公司 | 集成电路装置 |
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US10128215B1 (en) | 2016-02-16 | 2018-11-13 | Darryl G. Walker | Package including a plurality of stacked semiconductor devices having area efficient ESD protection |
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JP2010225701A (ja) * | 2009-03-19 | 2010-10-07 | Toshiba Corp | 三次元積層型半導体集積回路及びその製造方法 |
WO2012121255A1 (ja) * | 2011-03-09 | 2012-09-13 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP5583266B2 (ja) * | 2011-03-09 | 2014-09-03 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
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WO2023166674A1 (ja) * | 2022-03-03 | 2023-09-07 | 株式会社ソシオネクスト | 半導体集積回路装置 |
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