JP6131875B2 - 半導体パッケージ - Google Patents
半導体パッケージ Download PDFInfo
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- JP6131875B2 JP6131875B2 JP2014028358A JP2014028358A JP6131875B2 JP 6131875 B2 JP6131875 B2 JP 6131875B2 JP 2014028358 A JP2014028358 A JP 2014028358A JP 2014028358 A JP2014028358 A JP 2014028358A JP 6131875 B2 JP6131875 B2 JP 6131875B2
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- 239000004065 semiconductor Substances 0.000 title claims description 48
- 239000011347 resin Substances 0.000 claims description 71
- 229920005989 resin Polymers 0.000 claims description 71
- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 10
- 238000007789 sealing Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- 238000003825 pressing Methods 0.000 description 5
- 230000008602 contraction Effects 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- XEEYBQQBJWHFJM-UHFFFAOYSA-N iron Substances [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000000725 suspension Substances 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Images
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
下段チップの厚み(D1)は、上段チップの厚み(D3)以上であり、中段チップの厚み(D2)は、上段チップの厚み以上であり、中段チップの平面サイズ(H1)は、上段チップの平面サイズ(H2)よりも大きいものであり、アイランドの他面の直下に位置するモールド樹脂の厚み(D4)は、中段チップの上面(32)上に位置するモールド樹脂の厚み(D5)よりも大きいものであることを特徴とする。
なお、上記実施形態では、好ましい形態として、下段チップ20の平面サイズを中段チップ30の平面サイズH1よりも大きいものとしたが、下段チップ20の平面サイズが中段チップ30の平面サイズH1より小さいものであってもよい。その場合、下段チップ30と中段チップ30とをワイヤ80ではなく、たとえばフリップチップの如くバンプ接合等で接合すればよい。
20 下段チップ
30 中段チップ
30a 回路部
32 中段チップの上面
40 上段チップ
50 モールド樹脂
D1 下段チップの厚み
D2 中段チップの厚み
D3 上段チップの厚み
D4 アイランドの他面の直下に位置するモールド樹脂の厚み
D5 中段チップの上面上に位置するモールド樹脂の厚み
H1 中段チップの平面サイズ
H2 上段チップの平面サイズ
Claims (3)
- 一面(11)と他面(12)とが表裏の板面の関係にある金属製のアイランド(10)と、
前記アイランドの一面上に搭載された半導体よりなる下段チップ(20)と、
前記下段チップ上に積層された半導体よりなる中段チップ(30)と、
前記中段チップ上に積層された半導体よりなる上段チップ(40)と、
前記アイランドの一面側、前記アイランドの他面側、および前記3個のチップ(20〜40)を封止するモールド樹脂(50)と、を備え、
前記下段チップおよび前記中段チップのうち少なくとも前記中段チップは、回路部(30a)を有するものである半導体パッケージであって、
前記下段チップの厚み(D1)は、前記上段チップの厚み(D3)以上であり、
前記中段チップの厚み(D2)は、前記上段チップの厚み以上であり、
前記中段チップの平面サイズ(H1)は、前記上段チップの平面サイズ(H2)よりも大きいものであり、
前記アイランドの他面の直下に位置する前記モールド樹脂の厚み(D4)は、前記中段チップの上面(32)上に位置する前記モールド樹脂の厚み(D5)よりも大きいものであることを特徴とする半導体パッケージ。 - 前記下段チップの平面サイズは、前記中段チップの平面サイズよりも大きいことを特徴とする請求項1に記載の半導体パッケージ。
- 前記上段チップの平面サイズは、前記中段チップにおける前記回路部の平面サイズよりも大きいものであり、
前記回路部の全体が前記上段チップの外郭の内周に位置するように、前記回路部の全体が前記上段チップにて被覆されていることを特徴とする請求項1または2に記載の半導体パッケージ。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014028358A JP6131875B2 (ja) | 2014-02-18 | 2014-02-18 | 半導体パッケージ |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014028358A JP6131875B2 (ja) | 2014-02-18 | 2014-02-18 | 半導体パッケージ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015153985A JP2015153985A (ja) | 2015-08-24 |
JP6131875B2 true JP6131875B2 (ja) | 2017-05-24 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2014028358A Active JP6131875B2 (ja) | 2014-02-18 | 2014-02-18 | 半導体パッケージ |
Country Status (1)
Country | Link |
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JP (1) | JP6131875B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102009827B1 (ko) * | 2016-12-30 | 2019-08-12 | 스템코 주식회사 | 연성 회로 기판 및 이의 포함하는 전자 제품 제조 방법 |
JP2019220621A (ja) | 2018-06-21 | 2019-12-26 | キオクシア株式会社 | 半導体装置及びその製造方法 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5081475A (ja) * | 1973-11-19 | 1975-07-02 | ||
JP3737333B2 (ja) * | 2000-03-17 | 2006-01-18 | 沖電気工業株式会社 | 半導体装置 |
JP2002076251A (ja) * | 2000-08-30 | 2002-03-15 | Hitachi Ltd | 半導体装置 |
JP4031333B2 (ja) * | 2002-09-26 | 2008-01-09 | 株式会社ルネサステクノロジ | 半導体装置 |
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2014
- 2014-02-18 JP JP2014028358A patent/JP6131875B2/ja active Active
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