CN110634880A - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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Publication number
CN110634880A
CN110634880A CN201910093770.8A CN201910093770A CN110634880A CN 110634880 A CN110634880 A CN 110634880A CN 201910093770 A CN201910093770 A CN 201910093770A CN 110634880 A CN110634880 A CN 110634880A
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Prior art keywords
semiconductor substrate
semiconductor
substrate
circuit
wiring
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CN201910093770.8A
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筑山慧至
青木秀夫
川户雅敏
三浦正幸
福田昌利
本间庄一
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Kioxia Corp
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Toshiba Memory Corp
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Publication of CN110634880A publication Critical patent/CN110634880A/zh
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Abstract

实施方式提供一种半导体装置及其制造方法。半导体装置具备：布线衬底；第一半导体衬底设置在布线衬底的上方，且在表面形成着第一半导体电路的存储器衬底；第二半导体衬底设置在第一半导体衬底与布线衬底之间，比第一半导体衬底厚，且在表面形成着第二半导体电路的存储器衬底；凸块设置在第一半导体衬底与第二半导体衬底之间，将第一半导体衬底与第二半导体衬底电连接；第一粘接性树脂设置在第一半导体衬底与第二半导体衬底之间，粘接第一半导体衬底与第二半导体衬底；密封树脂形成在第一半导体衬底与第二半导体衬底之间、第二半导体衬底与布线衬底之间及第一半导体衬底与第二半导体衬底的周围，将第一半导体衬底与第二半导体衬底密封。

Description

半导体装置及其制造方法
[相关申请]
本申请享有以日本专利申请2018-118175号(申请日：2018年6月21日)为基础申请的优先权。本申请通过参照该基础申请而包含基础申请的全部内容。
技术领域
本发明的实施方式涉及一种半导体装置及其制造方法。
背景技术
为了实现半导体装置的小型化或高功能化，开发有将以贯通通孔与微凸块相互连接的多个半导体存储器衬底积层而成的半导体封装。已知有一种半导体封装，在使形成着半导体元件的面朝向上方相互积层而成的半导体存储器衬底积层构造中，使最下层的存储器衬底的厚度大于其它存储器衬底的厚度。
发明内容
实施方式提供一种提高了半导体衬底间的接合可靠性的半导体装置及其制造方法。
实施方式的半导体装置具备：布线衬底；第一半导体衬底，是设置在所述布线衬底的上方，且在表面形成着第一半导体电路的存储器衬底；第二半导体衬底，是设置在所述第一半导体衬底与所述布线衬底之间，比所述第一半导体衬底厚，且在表面形成着第二半导体电路的存储器衬底；凸块，设置在所述第一半导体衬底与所述第二半导体衬底间之间，将所述第一半导体衬底与所述第二半导体衬底电连接；第一粘接性树脂，设置在所述第一半导体衬底与所述第二半导体衬底之间，粘接所述第一半导体衬底与第二半导体衬底；及密封树脂，形成在所述第一半导体衬底与第二半导体衬底之间、所述第二半导体衬底与所述布线衬底之间、及所述第一半导体衬底与第二半导体衬底的周围，将所述第一半导体衬底与第二半导体衬底密封。
另外，另一实施方式的半导体装置具备：布线衬底；积层体，设置在所述布线衬底，包括形成着半导体电路的多片半导体衬底；第一半导体衬底，是所述积层体中距离所述布线衬底最远地设置，且在表面形成着第一半导体电路的存储器衬底；第二半导体衬底，是所述积层体中距离所述布线衬底最近地设置，比所述第一半导体衬底厚，且在表面形成着第二半导体电路的存储器衬底；凸块，将所述多片半导体衬底分别电连接；粘接性树脂，设置在所述多片半导体衬底之间，将所述多片半导体衬底分别粘接；及密封树脂，形成在所述多片半导体衬底之间、及所述多片半导体衬底的周围，将所述多片半导体衬底密封。
另外，也可还具备第三半导体衬底，所述第三半导体衬底设置在所述第二半导体衬底与所述布线衬底之间，比所述第一半导体衬底厚，且在表面形成着第三半导体电路，所述第二半导体衬底经由设置在所述第二半导体衬底与第三半导体衬底之间的凸块而与所述第三半导体衬底电连接。
另外，也可为形成着所述第一半导体电路的面与形成着所述第二半导体电路的面朝向相同方向，且与形成着所述第三半导体电路的面相向。
另外，所述第三半导体衬底也可为外形比所述第一半导体衬底及所述第二半导体衬底小的衬底。
另外，也可为所述第二半导体衬底具有：第二有机保护膜，以覆盖所述第二半导体电路的方式设置；第二再布线层，形成在所述第二有机保护膜的内部且与所述第二半导体电路电连接；及第二焊盘，与所述第二再布线层电连接，且设置在将所述第一半导体衬底与所述第二半导体衬底积层的方向设为第一方向时从所述第一方向观察时不与所述第三半导体衬底重叠的位置；并且具备将所述第二焊盘与所述布线衬底电连接且直径比所述凸块大的大凸块。
另外，也可为所述第一半导体衬底具有：第一有机保护膜，以覆盖所述第一半导体电路的方式设置；第一再布线层，形成在所述第一有机保护膜的内部且与所述第一半导体电路电连接；及第一焊盘，与所述第一再布线层电连接；所述第二半导体衬底具有贯通所述第二半导体衬底且与所述第二半导体电路电连接的第一贯通通孔，且所述第一贯通通孔与所述第一焊盘经由凸块电连接。
另外，也可为所述第三半导体衬底具有：第三有机保护膜，以覆盖所述第三半导体电路的方式设置；第三再布线层，形成在所述第三有机保护膜的内部且与所述第三半导体电路电连接；及第三焊盘，与所述第三再布线层电连接；所述第二半导体衬底具有第四焊盘，所述第四焊盘与所述第二再布线层电连接，设置在从所述第一方向观察时与所述第三半导体衬底重叠的位置，且面积比所述第二焊盘小，并且具备将所述第三焊盘与所述第四焊盘电连接的所述凸块。
另外，也可具备：第二粘接性树脂，设置在所述第一半导体衬底的与形成着所述第一半导体电路的面为相反侧的面；及支撑体，经由所述第二粘接性树脂与所述第一半导体衬底粘接，且外形比所述第一半导体衬底的外形大。
根据实施方式，可提供一种提高了半导体衬底间的接合可靠性的半导体装置。
附图说明
图1是说明实施方式的半导体装置的构成的图。
图2是说明实施方式的半导体装置的制造方法的图。
图3是说明实施方式的半导体装置的制造方法的图。
图4是说明实施方式的变化例的半导体装置的构成的图。
图5是说明半导体衬底的图。
具体实施方式
以下，对用来实施发明的实施方式进行说明。
参照图1～3对本实施方式的半导体装置进行说明。此外，在附图的记载中，相同部分以相同符号表示。但是，附图是厚度与平面尺寸的关系、比率等与实物不同的示意性的图。
利用图1对本实施方式的半导体装置的构成进行说明。图1是表示本实施方式的半导体装置的构成的剖视图。
如图1所示，本实施方式的半导体装置100具有第一半导体衬底1、第二半导体衬底2、第三半导体衬底3、及第四半导体衬底4分别积层而成的半导体衬底的积层构造。此处，第一半导体衬底1、第二半导体衬底2、及第三半导体衬底3分别为NAND(Not AND，与非)闪速存储器等存储器衬底，第四半导体衬底4为接口(IF)衬底。IF衬底具备用来在存储器衬底与外部器件之间进行数据通信的IF电路。
第一半导体衬底1、第二半导体衬底2、第三半导体衬底3、及第四半导体衬底4分别具有硅等半导体衬底、以及设置在半导体衬底上的半导体元件(省略图示)、半导体电路布线(省略图示)、层间绝缘膜(省略图示)。
在图5中表示半导体衬底3的放大图。
半导体电路16包含半导体元件、半导体电路布线、及层间绝缘膜。此处，如果将半导体衬底的设置着半导体元件的表面设为半导体电路面(电路面)，将相反侧的表面设为背面，则第一半导体衬底1、第二半导体衬底2、及第三半导体衬底3是以半导体衬底的半导体电路面均朝向相同方向(上方)的方式积层，另一方面，第四半导体衬底4以半导体衬底的半导体电路面朝向相反方向(下方)的方式积层。第四半导体衬底4的半导体电路面与第三半导体衬底3的半导体电路面彼此相向。
第一半导体衬底1的厚度比第二半导体衬底2、第三半导体衬底3、及第四半导体衬底4的厚度薄。通过以第一半导体衬底1的半导体衬底比第二半导体衬底2、第三半导体衬底3、及第四半导体衬底4的各个半导体衬底薄的方式进行薄膜加工，作为衬底整体而第一半导体衬底1比第二半导体衬底2、第三半导体衬底3、第四半导体衬底4薄。薄膜加工可通过半导体衬底的磨削等而实现。例如，将第一半导体衬底1的厚度设为小于30μm，将第二半导体衬底2、第三半导体衬底3、及第四半导体衬底4的厚度设为30μm～50μm。
如图5所示，在第一半导体衬底1、第二半导体衬底2、第三半导体衬底3的半导体电路16之上分别形成着有机保护膜12。有机保护膜12可应用各种有机绝缘材料，例如可使用聚酰亚胺树脂膜、酚树脂膜、丙烯酸系树脂膜、聚苯并恶唑树脂膜、聚苯并环丁烯树脂膜等。有机保护膜12可为单层，也可为多层。有机保护膜12是用来保护半导体衬底的内部电路布线的钝化膜等。
有机保护膜12也可在其中形成再布线层17。再布线层17与半导体电路16电连接。再布线层17也与设置在有机保护膜12的外部的焊盘18电连接。也就是说，焊盘18经由再布线层17与半导体电路16电连接。
第一半导体衬底1、第二半导体衬底2、第三半导体衬底3分别经由凸块5及贯通通孔6而电连接。第四半导体衬底4经由凸块5及第三半导体衬底3的半导体电路面16上的有机保护膜12内所设置的再布线层17而与第三半导体衬底3电连接。作为凸块5的材料，可使用Cu、Ag、Bi、In等与Sn的合金、或Cu、Ni、Au、Ag、Pd、Sn等。设置在各半导体衬底间的凸块5为微凸块，凸块间的间距为10～100μm，凸块的直径为5～50μm左右。贯通通孔6包含Cu、Ni或W等导电材料，且以分别贯通第二半导体衬底2及第三半导体衬底3的方式设置。半导体衬底的半导体电路16中包含的电路布线或元件与贯通通孔6电连接。另外，贯通通孔6也可贯通半导体电路16而直接连接于再布线层17。通过贯通通孔6与凸块5接合而将各半导体衬底的电路布线或元件电连接。此外，凸块5接合于各半导体衬底表面中设置在有机保护膜12的开口区域、例如焊盘18露出的表面。
在第一半导体衬底1、第二半导体衬底2、第三半导体衬底3、及第四半导体衬底4各自之间形成兼用作止动部的粘接性树脂7。兼用作止动部的粘接性树脂7作为保持所积层的各半导体衬底的间隙的止动部件发挥功能，与此同时，作为在填充密封树脂的前阶段将半导体衬底间粘接的粘接部件发挥功能。粘接性树脂7由具有感光性或热固性的树脂形成。作为感光性及热固性树脂的具体例，可列举感光性粘接剂树脂之类的含有感光剂的热固性树脂，例如优选由使用环氧树脂、聚酰亚胺树脂、丙烯酸系树脂、酚树脂等的热固性树脂形成。粘接性树脂7的热膨胀系数与半导体衬底的用作半导体衬底的硅衬底或有机保护膜12不同。
第三半导体衬底3经由电路面上的有机保护膜12内所设置的再布线层及大凸块8而与布线衬底9电连接。第四半导体衬底4也经由凸块5及再布线层而与布线衬底9电连接。大凸块8与凸块5相比直径较大，使用与凸块5相同的材料。布线衬底9包含树脂材料，且在内部实施铜等的布线。布线衬底9是扩展至半导体衬底3正下方的区域的外侧的构造，也能够搭载半导体衬底3以外的半导体衬底。在布线衬底9形成着焊球(BGA(Ball Grid Array，球栅阵列))10。半导体衬底经由大凸块8、布线衬底9的内部布线及焊球10而与外部器件电连接。
图5中，第三半导体衬底3具有的焊盘19设置在从第一半导体衬底1与第二半导体衬底2积层的方向观察时不与第四半导体衬底4重叠的位置。焊盘19与焊盘18相比，与凸块5接触的面积较大。焊盘18与直径5～50μm左右的微凸块连接。因此，焊盘18的直径也为5～50μm左右。
第一半导体衬底1、第二半导体衬底2也可具有焊盘18与焊盘19。第一半导体衬底1、第二半导体衬底2由于无须经由大凸块8与布线衬底9连接，所以也可不具有焊盘19。
在布线衬底9上的各半导体衬底之间及它们的周围，形成着环氧树脂等密封树脂11，以将半导体衬底模塑。在各半导体衬底间，密封树脂11填充在有机保护膜12上未形成粘接性树脂7的区域。
接下来，参照图2及3，对本实施方式的半导体装置的制造方法进行说明。
首先，如图2所示，准备在半导体衬底上依次形成半导体电路、有机保护膜12而成的第一半导体衬底1，并使半导体电路面朝向上方而将半导体衬底1搭载在引线框架13上。在有机保护膜12的一部分设置开口，使半导体衬底1的电路的一部分例如电极焊盘露出。第一半导体衬底1的半导体衬底通过背面磨削等而薄膜化。
接着，如图3所示，在第一半导体衬底1上依次积层第二半导体衬底2、第三半导体衬底3、及第四半导体衬底4。在第二半导体衬底2及第三半导体衬底3，预先设置着贯通半导体衬底的贯通通孔6及位于贯通通孔6的前端的凸块5，且在与凸块5相同的衬底背面设置着粘接性树脂7。在第四半导体衬底4的电路面也形成着凸块5及粘接性树脂7。在第二半导体衬底2及第三半导体衬底3的半导体电路面上形成有机保护膜12，在有机保护膜12的一部分设置开口而使电路的一部分、例如焊盘露出。此处，第二半导体衬底2、第三半导体衬底3、及第四半导体衬底4的厚度大于第一半导体衬底1的厚度。
将第二半导体衬底2积层在第一半导体衬底1时，将第二半导体衬底2的凸块5以接合于第一半导体衬底1的焊盘的方式对准之后，将两衬底热压接。热压接时的温度例如为250度至280度。另一方面，第二半导体衬底2的粘接性树脂7也与第一半导体衬底1接触，并在凸块加热之前或同时进行加热，由此，可确保第二半导体衬底2与第一半导体衬底1的粘接以及衬底间距离。将第三半导体衬底3积层在第二半导体衬底2时，将第四半导体衬底4积层在第三半导体衬底3时，也可利用相同的方法将衬底彼此接合。此外，粘接性树脂7也可形成在接合的下层的半导体衬底，这种情况下，也可在上层的半导体衬底不设置粘接性树脂7。
在加热半导体衬底时，有时会因有机保护膜由热引起形状变化而导致半导体衬底产生翘曲。半导体衬底的硅衬底的热膨胀系数为3ppm左右，与此相对，有机保护膜的热膨胀系数相对较大，例如聚酰亚胺树脂的热膨胀系数为35ppm左右。此处，在经积层的半导体衬底的一部分、例如成为衬底积层时的基底的最下层的半导体衬底比其它衬底厚的情况下，无法追随其它半导体衬底的翘曲。由于最下层的半导体衬底与其上层的半导体衬底的翘曲量不同，所以形成在所述半导体衬底间的粘接性树脂会扩展，结果，将两衬底接合的凸块有可能会断裂。尤其微凸块等直径较小的凸块由于机械强度较弱，所以断裂的可能性较高。另一方面，本实施方式的半导体装置由于成为衬底积层时的基底的最下层的第一半导体衬底1的厚度比所积层的第二半导体衬底2、第三半导体衬底3、第四半导体衬底4薄，所以追随第二半导体衬底2、第三半导体衬底3、第四半导体衬底4的翘曲，在第一半导体衬底也产生翘曲，从而可防止衬底间的粘接性树脂7扩展，结果，可防止将第一半导体衬底1与其上层的第二半导体衬底2接合的凸块断裂。
另外，与将全部为相同厚度的半导体衬底积层的情况相比，通过预先使最下层的第一半导体衬底1比其它半导体衬底薄，可抑制第一至第三半导体衬底积层体整体的翘曲量，例如能够使翘曲量为数十μm以下。因此，可抑制将半导体衬底积层体与布线衬底9连接的大凸块8所受的压力，从而防止凸块断裂。在图3及图3之后的图中，虽省略图示，但可将经积层的半导体衬底群以第三半导体衬底3的电路形成面与布线衬底9对向的方式经由大凸块8接合于布线衬底，并利用密封树脂进行模塑，由此制造本实施方式的半导体装置。密封树脂的加热硬化温度例如为180度左右。
(变化例)参照图4对实施方式的半导体装置的变化例进行说明。此外，在图4的记载中，与图1相同的部分以相同符号表示。但是，附图是厚度与平面尺寸的关系、比率等与实物不同的示意性的图。
本变化例的半导体装置与实施方式的半导体装置的不同之处在于第一半导体衬底经由DAF(Die Attach Film，芯片粘结膜)而形成在支撑体。其它构成相同而省略说明。
如图4所示，本变化例的半导体装置200的第一半导体衬底1经由DAF15而形成在支撑体14上。支撑体14是引线框架或硅衬底等支撑第一半导体衬底1的衬底。DAF是含有有机系树脂材料的膜材，粘接支撑体14与第一半导体衬底。
本变化例中，第一半导体衬底1的厚度也小于第二、第三、第四半导体衬底的厚度，因此，可防止衬底加热压接时的伴随衬底的翘曲产生的第一半导体衬底1与第二半导体衬底2间的凸块5的断裂。
另外，可于在支撑体14上设置着多个半导体衬底的状态下将半导体衬底搭载在布线衬底9，因此，积层衬底的搬送、操作较容易。
半导体衬底的积层数为4层，但并不限于此，积层数可为更多，也可为更少。
以上，对本发明的实施方式进行了说明，但本实施方式是作为例子而提出的，并不意图限定发明的范围。新颖的实施方式能以其它多种方式实施，能够在不脱离发明主旨的范围内进行各种省略、置换、变更。这些实施方式或其变化包含在发明的范围或主旨中，并且包含在权利要求书所记载的发明及其均等的范围内。
[符号的说明]
1 第一半导体衬底
2 第二半导体衬底
3 第三半导体衬底
4 第四半导体衬底
5 凸块
6 贯通通孔
7 粘接性树脂
8 大凸块
9 布线衬底
10 焊球
11 密封树脂
12 有机保护膜
13 引线框架
14 支撑体
15 DAF
16 半导体电路
17 再布线层
18、19 焊盘
100、200 半导体装置

Claims (11)

1.一种半导体装置，具备：
布线衬底；
第一半导体衬底，是设置在所述布线衬底的上方，且在表面形成着第一半导体电路的存储器衬底；
第二半导体衬底，是设置在所述第一半导体衬底与所述布线衬底之间，比所述第一半导体衬底厚，且在表面形成着第二半导体电路的存储器衬底；
凸块，设置在所述第一半导体衬底与所述第二半导体衬底间之间，将所述第一半导体衬底与所述第二半导体衬底电连接；
第一粘接性树脂，设置在所述第一半导体衬底与所述第二半导体衬底之间，粘接所述第一半导体衬底与第二半导体衬底；及
密封树脂，形成在所述第一半导体衬底与第二半导体衬底之间、所述第二半导体衬底与所述布线衬底之间、及所述第一半导体衬底与第二半导体衬底的周围，将所述第一半导体衬底与第二半导体衬底密封。
2.一种半导体装置，具备：
布线衬底；
积层体，设置在所述布线衬底，包括形成着半导体电路的多片半导体衬底；
第一半导体衬底，是所述积层体中距离所述布线衬底最远地设置，且在表面形成着第一半导体电路的存储器衬底；
第二半导体衬底，是所述积层体中距离所述布线衬底最近地设置，比所述第一半导体衬底厚，且在表面形成着第二半导体电路的存储器衬底；
凸块，将所述多片半导体衬底分别电连接；
粘接性树脂，设置在所述多片半导体衬底之间，将所述多片半导体衬底分别粘接；及
密封树脂，形成在所述多片半导体衬底之间、及所述多片半导体衬底的周围，将所述多片半导体衬底密封。
3.根据权利要求1或2所述的半导体装置，其特征在于：还具备第三半导体衬底，所述第三半导体衬底设置在所述第二半导体衬底与所述布线衬底之间，比所述第一半导体衬底厚，且在表面形成着第三半导体电路，且
所述第二半导体衬底经由设置在所述第二半导体衬底与第三半导体衬底之间的凸块而与所述第三半导体衬底电连接。
4.根据权利要求3所述的半导体装置，其特征在于：形成着所述第一半导体电路的面与形成着所述第二半导体电路的面朝向相同方向，且与形成着所述第三半导体电路的面相向。
5.根据权利要求4所述的半导体装置，其特征在于：所述第三半导体衬底是外形比所述第一半导体衬底及所述第二半导体衬底小的衬底。
6.根据权利要求5所述的半导体装置，其特征在于所述第二半导体衬底具有：第二有机保护膜，以覆盖所述第二半导体电路的方式设置；第二再布线层，形成在所述第二有机保护膜的内部且与所述第二半导体电路电连接；及第二焊盘，与所述第二再布线层电连接，且设置在将所述第一半导体衬底与所述第二半导体衬底积层的方向设为第一方向时从所述第一方向观察时不与所述第三半导体衬底重叠的位置；且
具备将所述第二焊盘与所述布线衬底电连接且直径比所述凸块大的大凸块。
7.根据权利要求6所述的半导体装置，其特征在于所述第一半导体衬底具有：第一有机保护膜，以覆盖所述第一半导体电路的方式设置；
第一再布线层，形成在所述第一有机保护膜的内部且与所述第一半导体电路电连接；及
第一焊盘，与所述第一再布线层电连接；
所述第二半导体衬底具有贯通所述第二半导体衬底且与所述第二半导体电路电连接的第一贯通通孔，且
所述第一贯通通孔与所述第一焊盘经由凸块电连接。
8.根据权利要求7所述的半导体装置，其特征在于所述第三半导体衬底具有：第三有机保护膜，以覆盖所述第三半导体电路的方式设置；
第三再布线层，形成在所述第三有机保护膜的内部且与所述第三半导体电路电连接；及
第三焊盘，与所述第三再布线层电连接；
所述第二半导体衬底具有第四焊盘，所述第四焊盘与所述第二再布线层电连接，设置在从所述第一方向观察时与所述第三半导体衬底重叠的位置，且面积比所述第二焊盘小，且
具备将所述第三焊盘与所述第四焊盘电连接的所述凸块。
9.根据权利要求8所述的半导体装置，具备：
第二粘接性树脂，设置在所述第一半导体衬底的与形成着所述第一半导体电路的面为相反侧的面；及
支撑体，经由所述第二粘接性树脂与所述第一半导体衬底粘接，且外形比所述第一半导体衬底的外形大。
10.一种半导体装置的制造方法，包含如下步骤：
准备第一半导体衬底及比所述第一半导体衬底厚的第二半导体衬底；
将介置在所述第一半导体衬底与第二半导体衬底间的凸块及粘接性树脂加热，对所述第一半导体衬底与第二半导体衬底进行热压接而形成积层体；及
在所述加热后，在所述第一半导体衬底与所述第二半导体衬底之间、及所述第一半导体衬底与第二半导体衬底的周围形成密封树脂，将所述第一半导体衬底及第二半导体衬底密封。
11.根据权利要求10所述的半导体装置的制造方法，其特征在于还包含如下步骤：
准备布线衬底、及外形比所述第二半导体衬底小的第三半导体衬底；
对所述积层体与所述第三半导体衬底进行热压接；及
将所述积层体热压接于所述布线衬底；且
所述密封树脂也形成在所述第二半导体衬底与所述第三半导体衬底之间、及所述第三半导体衬底与所述布线衬底之间。
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