CN103383921A - 半导体封装件及其形成方法 - Google Patents

半导体封装件及其形成方法 Download PDF

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Publication number
CN103383921A
CN103383921A CN2013101625636A CN201310162563A CN103383921A CN 103383921 A CN103383921 A CN 103383921A CN 2013101625636 A CN2013101625636 A CN 2013101625636A CN 201310162563 A CN201310162563 A CN 201310162563A CN 103383921 A CN103383921 A CN 103383921A
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semiconductor chip
semiconductor
encapsulation agent
conductive plate
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CN103383921B (zh
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伊万·尼基廷
爱德华·菲尔古特
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及半导体封装件及其形成方法。在一个实施例中，半导体封装件包括在第一主表面上具有第一接触区域和在相对的第二主表面上具有第二接触区域的半导体芯片。该半导体芯片被构造成调节从第一接触区域至第二接触区域的电流。封装剂设置在半导体芯片处。第一接触插塞设置在封装剂内并且联接至第一接触区域。第二侧导电层设置在第二主表面下方并且耦接至第二接触区域。通孔设置在封装剂内并耦接至第二侧导电层。第一接触插塞和通孔在第一主表面上方形成用于接触半导体封装件的端子。

Description

半导体封装件及其形成方法
技术领域
本发明总体涉及半导体封装件，并且更特别地涉及半导体封装件及其形成方法。
背景技术
半导体器件用在多种电子及其他应用中。半导体器件包括集成电路，或通过将多种材料的薄膜沉积在半导体晶片上方并使材料的薄膜图案化以集成电路而在半导体晶片上形成的分立器件。
半导体器件典型地封装在陶瓷或塑料本体内以保护其免受物理损坏和腐蚀。这种封装还支撑连接至所述器件所需的电触头。根据正在封装的晶圆的种类和旨在用途，可获得多种不同类型的封装。典型的封装（例如封装件的尺寸、引线数（pin count））可遵照诸如来自电子设备工程联合协会（Joint Electron Devices Engineering Council（JEDEC））的开放标准。封装也可称为半导体器件组件或者仅称组件。
由于将多个电接头连接至外部焊垫并同时保护这些电接头和位于下方的芯片的复杂性，封装可能为成本密集的工艺。
发明内容
通过本发明的示例性实施例，大体解决或者规避这些和其他问题，并且大体实现技术优点。
根据本发明的一个实施例，形成半导体封装件的方法包括将多个半导体芯片设置在载体上方。多个半导体芯片中的每个在第一侧和相对的第二侧上具有第一侧接触区域。多个半导体芯片中的每个具有邻近第一侧的活性区域。第二侧面向载体。该方法还包括通过在多个半导体芯片和载体处施加封装剂来形成再造晶片（reconstituted wafer）。在封装剂中形成穿透开口和接触开口。通过用导电填充材料填充穿透开口和接触开口而形成第一接触焊垫和第二接触焊垫。通过使再造晶片单一化来形成独立封装件。多个半导体芯片可包括被构造成调节从第一侧朝向第二侧的方向上的电流的芯片。
根据本发明的一个实施例，半导体封装件包括具有在第一主表面上具有第一接触区域和在相对的第二主表面上具有第二接触区域的半导体芯片。半导体芯片被构造成调节从第一接触区域至第二接触区域的电流。封装剂设置在半导体芯片处。第一接触插塞设置在封装剂内并且耦接至第一接触区域。第二侧导电层设置在第二主表面下方并且耦接至第二接触区域。通孔设置在封装剂内并耦接至第二侧导电层。第一接触插塞和通孔在第一主表面上方形成用于接触半导体封装件的端子。
上述已相当宽泛地概述了本发明实施例的特征，以便可更好地理解以下本发明的详细描述。下文中将描述本发明实施例的附加特征和优点，所述附加特征和优点构成本发明权利要求的主题。本领域技术人员应当认识到，所公开的概念和具体的实施例可容易地用作出于与本发明相同的目的而修改或设计其他结构或工艺的基础。本领域技术人员还应当认识到，这样的等同设计不背离如所附权利要求中所阐述的本发明的精神和范围。
附图说明
为了更彻底地理解本发明及其优点，现在参照以下结合附图进行的描述，附图中：
图1示出了根据本发明实施例的包括功率半导体的芯片级封装件；
图2（包括图2A-图2D）示出了根据本发明实施例的包括三端子半导体器件的封装件，其中，图2A和图2C至图2D示出了横截面视图，而图2B示出了顶视图；
图3示出了根据本发明实施例的在将单一化的晶圆设置在载体上方之后的制造过程中的半导体封装件；
图4示出了根据本发明实施例的在形成再造晶片之后的制造过程中的半导体封装件；
图5示出了根据本发明实施例的在形成用于接触焊垫的开口之后的制造过程中的半导体封装件；
图6示出了根据本发明实施例的在通过填充接触焊垫开口而形成接触焊垫之后的制造过程中的半导体封装件；
图7示出了根据本发明实施例的在将再造晶片与载体分离之后的制造过程中的半导体封装件；
图8（包括图8A和图8B）示出了根据本发明实施例的在对再造晶片进行减薄之后的制造过程中的半导体封装件，其中，图8B示出了图8A的放大横截面视图；
图9示出了根据本发明实施例的在再造晶片下方形成背面金属衬层之后的制造过程中的半导体封装件；
图10示出了根据本发明实施例的在金属衬层和再造晶片下方形成背面金属层之后的制造过程中的半导体封装件；
图11示出了根据本发明实施例的在将再造晶片的正面平面化之后的制造过程中的半导体封装件；
图12示出了根据本发明实施例的在构建背面金属层之后的制造过程中的半导体封装件；
图13示出了根据本发明实施例的在去除暴露的封装剂之后的制造过程中的半导体封装件；
图14示出了根据本发明实施例的在形成多个抗蚀结构之后的制造过程中的半导体封装件；
图15示出了根据本发明实施例的在沉积图案化的背面金属层之后的制造过程中的半导体封装件；
图16示出了根据本发明实施例的在去除所述多个抗蚀结构之后的制造过程中的半导体封装件；以及
图17（包括图17A和图17B）示出了利用本发明实施例形成的并且安装在电路板上方的半导体封装件。
除非另有陈述，否则不同附图中的对应标号和符号总体上表示对应的部分。绘制附图以清楚地示出本发明的相关方面，并且附图不必按比例绘制。
具体实施方式
以下详细讨论各个实施例的构成和使用。然而，应当认识到的是，本发明提供能够在多种具体背景下体现的可应用的多种发明概念。所讨论的具体实施例仅示出构成和使用本发明的具体方式，并不限制本发明的范围。
功率半导体晶圆具有特殊的要求（例如，由于高的电压和高的热量产生）并且要求良好的热管理。因此，用于功率半导体器件的封装件在对生产成本非常敏感的同时还具有额外的性能要求。由于引线数（输入/输出引线）数目较小，因此功率晶圆典型地被作为晶体管外形（TO）封装件来封装，但本发明不限于特定的封装类型。
将利用图1来描述具有竖直半导体芯片的半导体封装件的结构性实施例。将利用图2来描述可替换的结构性实施例。将利用图3至图13来描述形成根据本发明各个实施例的半导体封装件的方法。将利用图14至图16来描述形成半导体封装件的可替换方法。将利用图17来描述用于将封装件安装在电路板上的本发明的实施例。
图1示出了根据本发明实施例的包括功率半导体的芯片级封装件。
参照图1，半导体芯片20设置在封装剂50内。在一个或多个实施例中，由于竖直的电流（例如从顶面11至底面12），半导体芯片20为竖直半导体器件。因此，半导体芯片20不仅在顶面11上具有接触区域而且在底面12上也具有接触区域。在一些实施例中，半导体芯片20为具有横向电流的水平半导体器件。
在各个实施例中，半导体芯片20可形成在硅基板上。可替换地，半导体芯片20可为形成在SiC上的器件。在一个实施例中，半导体芯片20为至少部分地形成在GaN上的器件。
在各个实施例中，半导体芯片20包括功率半导体器件，该功率半导体器件在一个实施例中可为分立器件。在一个实施例中，半导体芯片20为两端子器件，诸如PIN二极管或肖特基二极管。在一个或多个实施例中，半导体芯片20为三端子器件，诸如功率金属绝缘体半导体场效应晶体管（MISFET）、结型场效应晶体管（JFET）、双极结晶体管（BJT）、绝缘栅双极晶体管（IGBT）或者闸流管。在各个实施例中，半导体芯片20构造成在大约1V至大约1000V下运行。在一个实施例中，半导体芯片20构造成在大约1V至大约20V下运行。在一个或多个实施例中，半导体芯片20构造成在大约20V至大约1000V下运行。在一个实施例中，半导体芯片20构造成在大约20V至大约100V下运行。在一个实施例中，半导体芯片20构造成在大约100V至大约500V下运行。在一个实施例中，半导体芯片20构造成在大约500V至大约1000V下运行。
在一个实施例中，半导体芯片20为NPN型晶体管。在一个实施例中，半导体芯片20为PNP型晶体管。在一个实施例中，半导体芯片20为n沟道MISFET。在另一实施例中，半导体芯片20为p沟道MISFET。在一个或多个实施例中，半导体芯片20可包括多个器件，诸如竖直MISFET和二极管，或者可替换地由隔离区隔开的两个MISFET器件。
在各个实施例中，半导体芯片20从顶面11到底面12的厚度可小于50μm。在各个实施例中，半导体芯片20从顶面11到底面12的厚度可小于20μm。在各个实施例中，半导体芯片20从顶面11到底面12的厚度可小于10μm。
在各个实施例中，半导体芯片20从顶面11到底面12的厚度可为大约1μm至大约1000μm。在各个实施例中，半导体芯片20从顶面11到底面12的厚度可为大约5μm至大约50μm。在一个实施例中，半导体芯片20从顶面11到底面12的厚度可为大约5μm至大约20μm。
在一个实施例中，半导体芯片20从顶面11到底面12的厚度可为大约10μm至大约20μm。小于25μm的厚度可有利地使电阻最小化并且改善导热性，以便在有效去除操作过程中在半导体芯片20内产生的热量的同时有助于改进电性能。然而，小于5μm的厚度可能在制造和/或操作过程中引入稳定性问题。
在各个实施例中，封装剂50包含介电材料，并且在一个实施例中可包含模塑化合物（mold compound）。在其他实施例中，封装剂50可包含聚合物、生物聚合物、纤维浸渍聚合物（例如碳纤维或玻璃纤维树脂）、颗粒填充聚合物、以及其他有机材料。在一个或多个实施例中，封装剂50包含并不是利用模塑化合物形成的密封剂、以及诸如环氧树脂和/或硅树脂的材料。在各个实施例中，封装剂50可由任何适当的硬塑性（duroplastic）、热塑性或热固性材料、或者层压件制成。在一些实施例中，封装剂50的材料可包括填充材料。在一个实施例中，封装剂50可包括环氧树脂材料以及填充材料，该填充材料包括小的玻璃颗粒或者其他电绝缘矿物填充材料（如氧化铝或有机填充材料）。
接触插塞120设置在半导体芯片20的顶面11上方。接触插塞120形成接触焊垫，该接触焊垫例如可安装到电路板上。接触插塞120提供至外部输入与输出信号以及用于使半导体芯片20起作用所需的其他信号的连接。在一个实施例中，接触插塞120可包括铜。在一个可替换实施例中，接触插塞120包括铝。在其他实施例中，接触插塞120可包括钨、钛、钽、钌、镍、钴、铂、金、银以及这样的其他材料。
半导体芯片20的顶面11可包括正面金属化层130，在各个实施例中，该正面金属化层可包括一种或多种金属衬层和通孔。在一个实施例中，金属化层130可在半导体芯片20内耦接各种器件。在另一实施例中，金属化层130对分立式半导体器件的不同区域形成接触点。
在一个或多个实施例中，穿过基板的通孔110设置在封装剂50内。穿过基板的通孔110具有传导性，从而为半导体芯片20的背面形成接触焊垫。在一个或多个实施例中，穿过基板的通孔110包括导电填充材料，诸如铜、铝以及这样的其他材料。在其他实施例中，填充材料可包括钨、钛、钽、钌、镍、钴、铂、金、银以及这样的其他材料。穿过基板的通孔110可包括外部阻碍层，在一些实施例中，该阻碍层可包括导电材料，诸如金属氮化物。穿过基板的通孔110的侧壁还可包括最外层，在一些实施例中，该最外层包含介电材料。
背面金属化层220设置在半导体芯片20的背面上。在一个实施例中，背面金属化层220可包括支承板221。在一个实施例中，背面金属化层220形成为位于半导体芯片20下方的覆盖层，即未结构化的层。背面金属化层220可包括接触半导体芯片20的扩散阻碍层222。扩散阻碍层222可防止背面金属化层220的原子扩散到半导体芯片20中。在一个或多个实施例中，扩散阻碍层222可包括氮化钛和/或氮化钽。在一个实施例中，扩散阻碍层222可包括Ta、TaN、TiW、Ti、TiN、Ru、W、WN、WCN或它们的组合。在一些实施例中，背面金属化层220还可包括设置在扩散阻碍层222上方的籽层。背面金属化层220的支承板221包括铜，但在其他实施例中，可使用其他导电材料，诸如掺杂的多晶硅、钨、铝、银、金、镍、钯或它们的组合。
图2（包括图2A-图2D）示出了根据本发明实施例的包括三端子半导体器件的封装件，其中，图2A示出了横截面视图并且图2B示出了顶视图，其中，图2C和图2D示出了可替换的横截面视图。
参照图2A，在一个或多个实施例中，该封装件包括如在之前的实施例中所述的半导体芯片20。此外，半导体芯片20为分立式三端子功率半导体器件。在一个实施例中，半导体芯片20为具有源极、栅极和漏极的三端子晶体管。在一个实施例中，源极和栅极形成为邻近顶面11，而漏极形成为邻近底面12。因此，顶面11具有源极接触区域21以及栅极接触区域22，而后表面13具有漏极接触区域23。在一个实施例中，源极接触区域21、栅极接触区域22、以及漏极接触区域23可包括硅化物区域。
在一个实施例中，接触插塞120的第一多个接触点121接触半导体芯片20的相同区域。例如，如图2A中所示，第一多个接触点121可直接地或间接地耦接至形成半导体芯片20的分立式晶体管的源极接触区域21。在一个实施例中，接触插塞120的第二多个接触点122接触栅极接触区域22。如图2B中所示，第一多个接触点121和第二多个接触点122形成接触焊垫，从而使半导体芯片20耦联接至外部信号。
图2C示出了一个可替换实施例，示出了三端子封装件，其中，第一多个接触点121中的一个、第二多个接触点122中的一个、以及穿过基板的通孔110形成三端子封装件的端子。
图2D示出了具有多个封装件的半导体模块的可替换实施例。如图2D中所示，该封装件可包括第一半导体芯片20A和第二半导体芯片20B。在一个实施例中，第一半导体芯片20A可为如在之前的实施例中所述的半导体芯片20。第二半导体芯片20B可为相同类型或不同类型的半导体芯片。在一个实施例中，第二半导体芯片20B可包括具有水平电流的水平半导体芯片。在各个实施例中，可包括不止一种不同类型的半导体芯片。举例来说，在一个实施例中，半导体封装件可包括两个功率半导体芯片和至少一个水平半导体芯片。
图3至图13示出了根据本发明实施例的在各个制造阶段过程中的半导体器件的横截面视图。
图3示出了根据本发明实施例的在将单一化的晶圆设置在载体上方之后的制造过程中的半导体封装件。
参照图3，将多个半导体芯片20设置在载体10上方。所述多个半导体芯片20可包括相同类型的芯片或者可包括不同类型的半导体芯片（例如，图2D中所示）。多个半导体芯片20具有相对于面向载体10的后表面13而言邻近顶面11的活性区域。多个半导体芯片20可使用传统工艺形成在例如晶片内，该晶片被切割以形成多个半导体芯片20。如上所述，多个半导体芯片20可形成在硅基板（诸如块状硅基板或绝缘体上硅基板）上。可替换地，半导体芯片20可为形成在SiC上的器件。本发明的实施例还可包括形成在化合物半导体基板上的器件并且可包括位于异质外延基板上的器件。在一个实施例中，半导体芯片20为至少部分地形成在GaN上的器件，该GaN可为位于蓝宝石或硅基板上的GaN。
然后，将多个半导体芯片20附接至载体10，该载体在加工过程中提供机械支撑和稳定性。在各个实施例中，载体10可为由刚性材料制成的板，所述刚性材料例如为金属（诸如镍、钢、或不锈钢）、层压件、膜、或者材料堆叠件。载体10可具有至少一个平坦表面，多个半导体芯片20可设置在该平坦表面上方。在一个或多个实施例中，载体10可为圆形或方形的，但是在各个实施例中，载体10可以为任何合适的形状。在各个实施例中，载体10可具有任何适当的尺寸。在一些实施例中，载体10可包括粘性带，例如层压到载体10上的双面粘性带。载体10可包括框架，在一个实施例中，该框架为具有粘性箔的环状结构（环形的）。在一个或多个实施例中，粘性箔可由框架沿着外边缘支撑。
在各个实施例中，可使用粘性层30来附接多个半导体芯片20。在各个实施例中，粘性层30可包括胶合材料或其他类型的粘性材料。在各个实施例中，粘性层30可较薄，例如，小于大约100μm，并且在另一实施例中，介于1μm到大约50μm之间。
在各个实施例中，多个半导体芯片20可包括功率芯片，所述功率芯片例如吸收大电流（例如，大于30安培）。在各个实施例中，多个半导体芯片20可包括分立式竖直器件，诸如两端子或三端子功率器件。半导体芯片20的实例包括PIN二极管或肖特基二极管、MISFET、JFET、BJT、IGBT、或闸流管。
图4示出了根据本发明实施例的在形成再造晶片之后的制造过程中的半导体封装件。
如图4中所示，将封装剂50施加在多个半导体芯片20上方。在一个实施例中，封装剂50利用压缩模塑工艺来施加。在压缩模塑中，封装剂50可设置到模塑空腔中，然后该晶圆空腔被封闭以压缩封装剂50。当对单个图案进行模塑时，可使用压缩模塑。在一个可替换实施例中，封装剂50利用传递模塑工艺来施加。在其他实施例中，封装剂50可利用注射模塑、造粒模塑、粉末模塑、或液态模塑来施加。可替换地，封装剂50可利用印刷工艺（诸如模板印刷或者丝网印刷）来施加。
在各个实施例中，封装剂50包含介电材料，并且在一个实施例中可包括模塑化合物。在其他实施例中，封装剂50可包含聚合物、生物聚合物、纤维浸渍聚合物（例如碳纤维或玻璃纤维树脂）、颗粒填充聚合物、以及其他有机材料。在一个或多个实施例中，封装剂50包含并不是利用模塑化合物形成的密封剂、以及诸如环氧树脂和/或硅树脂的材料。在各个实施例中，封装剂50可由任何适当的硬质塑性、热塑性或热固性材料、或者层压件制成。在一些实施例中，封装剂50的材料可包括填充材料。在一个实施例中，封装剂50的材料可包括环氧树脂材料以及填充材料，所述填充材料包括小的玻璃颗粒或者其他电绝缘矿物填充材料（如氧化铝或有机填充材料）。可使封装剂50固化，即，该封装剂经受热过程以便硬化，从而形成保护多个半导体芯片20的气密密封。固化过程使封装剂50硬化，从而形成保持多个半导体芯片20的单个基板。这样的基板称为再造晶片90。
图5示出了根据本发明实施例的在形成用于接触焊垫的开口之后的制造过程中的半导体封装件。
参照图5，在封装剂50内形成多个通孔开口60。在封装剂50内还形成多个接触开口70。在一个实施例中，使用激光工艺来形成所述多个通孔开口60和所述多个接触开口70。例如，可使用激光钻孔来构造封装剂50。在一个实施例中，可将二氧化碳激光器用于激光钻孔。在另一实施例中，激光钻孔可包括Nd:YAG激光器。在一个可替换实施例中，在传统的平版印刷工艺之后使用例如等离子体蚀刻工艺来形成所述多个通孔开口60和所述多个接触开口70。
在各个实施例中，所述多个通孔开口60包括小于500μm的最大直径。在一个或多个实施例中，所述多个通孔开口60包括小于400μm的最大直径。在一个实施例中，所述多个通孔开口60包括小于300μm的最大直径。在各个实施例中，所述多个通孔开口60包括在大约200μm到大约350μm的最大直径。
图6示出了根据本发明实施例的在通过填充接触焊垫开口而形成接触焊垫之后的制造过程中的半导体封装件。
如接下来的图6中所示，可在所述多个通孔开口60和所述多个接触开口70内形成金属衬层81。金属衬层81可包括扩散阻碍材料并且可包括用于后续电镀的籽层。举例来说，在一个实施例中，金属衬层81可包括金属氮化物（例如TiN、TaN）的堆叠并且随后是籽层（例如Cu）。在一个实施例中，金属衬层81可利用例如溅射沉积来沉积。在一个实施例中，金属衬层81可利用无线电频率（RF）磁控溅射来沉积。在可替换实施例中，金属衬层81可包括例如一层Ta、TaN、W、WN、WCN、WSi、Ti、TiN和/或Ru。例如使用等离子体气相沉积（PVD）溅射或金属有机物化学气相沉积（MOCVD）工艺，籽层可共形地沉积在扩散阻碍材料上方。在各个实施例中，籽层包含与待利用电镀工艺或化学沉积工艺来沉积的材料相同的材料。在一个实施例中，籽层包括铜。
将导电填充材料80填充在多个通孔开口60和多个接触开口70内。在各个实施例中，利用电化学沉积工艺（诸如电镀）来沉积导电填充材料80。可替换地，可利用化学沉积工艺来使沉积导电填充材料80。
因此，在沉积导电填充材料80之后，在多个通孔开口60内形成穿透基板的通孔110，同时在多个接触开口70内形成接触插塞120。
图7示出了根据本发明实施例的在将再造晶片与载体分离之后的制造过程中的半导体封装件。
参照图7，将载体10去除以分离再造晶片90或人造晶片。嵌入有多个半导体芯片20的封装剂50在后续加工过程中提供机械稳定性。去除载体10还使半导体芯片20的后表面13暴露。
图8（包括图8A和图8B）示出了根据本发明实施例的在对再造晶片进行减薄之后的制造过程中的半导体封装件，其中，图8B示出了图8A的放大横截面视图。
如接下来的图8A中所示，将再造晶片90减薄，使得多个半导体芯片20的厚度从第一厚度H1（图7）减小为第二厚度H2（图8），从而使底面12暴露。在各个实施例中，可利用机械加工（诸如研磨）来执行减薄。在一些实施例中，可利用化学加工或化学机械加工来减薄。
在各个实施例中，减薄之后的第二厚度H2为大约20μm到大约100μm，并且在一个实施例中，为80μm到大约120μm。在另一实施例中，减薄之后的第二厚度H2为大约50μm到大约100μm。在另一实施例中，减薄之后的第二厚度H2为大约20μm到大约50μm。在另一实施例中，减薄之后的第二厚度H2为大约10μm到大约20μm。在另一实施例中，减薄之后的第二厚度H2为至少10μm。
在另一实施例中，减薄之后的第二厚度H2为至少20μm。在另一实施例中，减薄之后的第二厚度H2为至少50μm。在另一实施例中，减薄之后的第二厚度H2小于100μm。在另一实施例中，减薄之后的第二厚度H2小于80μm。在另一实施例中，减薄之后的第二厚度H2小于50μm。在另一实施例中，减薄之后的第二厚度H2小于30μm。第二厚度H2可根据降低阻抗所需的机械稳定性以及其他方面来选择。
在一些实施例中，如图8B中所示，包括多个半导体芯片20的基板的结构可在减薄过程中改变。图8B示出了半导体芯片20在减薄前后的厚度。在减薄之前的半导体芯片20包括具有活性区域的第一层31和具有与第一层31的材料不同的材料的第二层32。在一个实施例中，当半导体芯片20制造在绝缘体上硅基板上时，第一层31包括硅并且第二层32包括氧化物层。在另一实施例中，当半导体芯片20制造在GaN/Si异质外延基板上时，第一层31包括化合物半导体材料（诸如GaN）并且第二层32包括硅。半导体芯片20在减薄之前的厚度为第一厚度H1，而在减薄之后的厚度为第二厚度H2。
例如，当多个半导体芯片20形成在绝缘体上硅基板上时，可在去除绝缘体层之后停止减薄工艺。
类似地，在异质外延基板（诸如位于硅基板上的GaN层）的情况中，可在去除硅基板且留下GaN层之后停止减薄工艺。可替换地，可留下一小部分的硅基板，其随后可转变为硅化物。例如，这可用于形成竖直GaN功率器件。
图9示出了根据本发明实施例的在再造晶片下方形成背面金属衬层之后的制造过程中的半导体封装件。
接下来参照图9，在再造晶片的暴露底面12下方形成背面金属衬层210。在一个或多个实施例中，背面金属衬层210可作为覆盖层来沉积。在各个实施例中，背面金属衬层210包含与待利用电镀工艺或化学沉积工艺来沉积的材料相同的材料（即籽层）。在一个实施例中，背面金属衬层210包含铜。在另一实施例中，背面金属衬层210包括铂、金、银、和/或锌。
背面金属衬层210可包括籽层和可选的扩散阻碍材料，使得籽层共形地沉积在可选的扩散阻碍材料上。在各个实施例中，可利用等离子体气相沉积（PVD）溅射或金属有机物化学气相沉积（MOCVD）工艺来沉积背面金属衬层210。在可替换实施例中，背面金属衬层210可包括例如一层Ta、TaN、W、WN、WCN、WSi、Ti、TiN和/或Ru。
图10示出了根据本发明实施例的在再造晶片下方形成背面金属层之后的制造过程中的半导体封装件。
如图10中所示，将背面金属层220形成在背面金属衬层210下方。在各个实施例中，可利用电化学沉积工艺（诸如电镀）来沉积背面金属层220。在另一实施例中，可利用化学沉积。在又一实施例中，可利用诸如溅射或MOCVD的沉积工艺来形成背面金属层220。在可替换实施例中，背面金属层220可包括例如一层Ta、TaN、W、WN、WCN、WSi、Ti、TiN和/或Ru。在一实例中，铜籽层作为背面金属衬层210而沉积，随后电镀铜以形成背面金属层220。在另一实例中，钛阻碍层作为背面金属衬层210而沉积，随后进行铝沉淀以形成背面金属层220。
图11示出了根据本发明实施例的在将再造晶片的正面平坦化之后的制造过程中的半导体封装件。
在一些实施例中，之前的电镀过程可能已使得正面接触点变短。因此，在一些实施例中，可从再造晶片的正面执行抛光，诸如化学抛光、机械抛光、或化学机械抛光。在其他实施例中，抛光步骤可以不同的工序来执行，例如在沉积导电填充材料80之后。
图12示出了根据本发明实施例的在构建背面金属层之后的制造过程中的半导体封装件。
可以对背面金属层220、背面金属衬层210、以及可选地位于正面上的导电填充材料80进行图案化，从而形成设置在切割区域230中的切割开口240。
图13示出了根据本发明实施例的在去除暴露的封装剂之后的制造过程中的半导体封装件。
然后，使再造晶片90单一化以形成独立封装件。在各个实施例中，可化学地（例如，利用等离子体工艺）执行单一化。在另一实施例中，可机械地（例如，利用切割锯）执行单一化。在一些实施例中，可利用化学工艺和机械工艺的组合来执行单一化。
图14至图16示出了形成具有竖直半导体芯片的半导体封装件的可替换实施例。
该实施例遵循如图3至图9中所述的之前的实施例。与之前的实施例不同，背面金属层220是图案化沉积的。
图14示出了根据本发明实施例的在形成多个抗蚀结构之后的制造过程中的半导体封装件。
如在图14中所示，在切割区域230上形成多个抗蚀结构250。可通过利用传统的平版印刷沉积抗蚀层并且对抗蚀层图案化来形成所述多个抗蚀结构。可替换地，在一些实施例中，可利用激光烧蚀工艺来形成多个抗蚀结构250。在其他实施例中，可利用印刷工艺（诸如模版印刷工艺）来形成多个抗蚀结构250。
图15示出了根据本发明实施例的在沉积图案化的背面金属层之后的制造过程中的半导体封装件。
沉积导电材料以形成背面金属层220。在各个实施例中，利用电化学沉积工艺来沉积导电材料。因此，导电材料不会沉积在多个抗蚀结构250上。
图16示出了根据本发明实施例的在去除所述多个抗蚀结构之后的制造过程中的半导体封装件。
可利用例如湿化学蚀刻工艺来去除多个抗蚀结构250。因此，切割开口240形成在切割区域230中。后续加工可遵循如图13中所述的。
图17（包括图17A和图17B）示出了利用本发明实施例形成的并且安装在电路板上方的半导体封装件。
在一个实施例中，利用本发明实施例形成的半导体封装件可安装在印刷电路板300上方。在一个实施例中，半导体封装件可面向下方地设置在印刷电路板300的主表面上。例如，可在穿透基板的通孔110和接触插塞120下方形成额外的焊球310，以耦接至印刷电路板300。在各个实施例中，可使用其他类型的安装。
此外，在各个实施例中，附加结构可附接至半导体封装件。例如，图17B示出了设置在半导体封装件上方的散热器350。可使用薄的粘合剂330来耦接散热器350，所述粘合剂可为热传导的，允许热从半导体芯片20传导出去。
尽管已参照示例性实施例描述了本发明，然而这种描述并不旨在以限制的方式来解释。对于本领域技术人员来说，在参阅本说明书之后，本发明的示例性实施例以及其他实施例的各种修改和组合将是显而易见的。举例来说，在图1、图2、图3-图13、图14-图16、以及图17中所描述的实施例可彼此组合。因此，所附权利要求旨在包含任何这样的修改或实施例。
尽管已详细描述了本发明及其优点，但应当理解的是，在不背离由所附权利要求限定的本发明的精神和范围的情况下，在此可做出各种改变、替换和变更。例如，本领域技术人员应当容易理解，在保持在本发明范围内的同时，可对在此描述的许多特征、功能、工艺和材料进行改变。
此外，本发明的范围不旨在限于本说明书中所描述的工艺、机器、制造、物质成分、装置、方法和步骤的特定实施例。正如本领域普通技术人员通过本发明公开会容易认识到的，可根据本发明来使用执行大致与在此所描述的对应实施例相同的功能或者实现大致与之相同的效果的现存或待后续发展的工艺、机器、制造、物质成分、装置、方法、或者步骤。因此，所附权利要求旨在将这样的工艺、机器、制造、物质成分、装置、方法、或者步骤包含在其范围内。

Claims (31)

1.一种形成半导体封装件的方法，所述方法包括：
将多个半导体芯片设置在载体上方，所述多个半导体芯片中的每个具有位于第一侧和相对的第二侧上的第一侧接触区域，所述多个半导体芯片中的每个具有邻近所述第一侧的活性区域，其中，所述第二侧面向所述载体；
通过在所述多个半导体芯片和所述载体处施加封装剂来形成再造晶片；
在所述封装剂中形成穿透开口和接触开口；
通过用导电填充材料填充所述穿透开口和所述接触开口来形成第一接触焊垫和第二接触焊垫；以及
通过使所述再造晶片单一化来形成独立封装件，其中，所述多个半导体芯片包括被构造成调节从所述第一侧朝向所述第二侧的方向上的电流的芯片。
2.根据权利要求1所述的方法，其中，将多个半导体芯片设置在载体上方包括设置多个功率芯片和多个器件，其中，所述独立封装件中的每个包括所述多个功率芯片中的一个功率芯片以及所述多个器件中的一个器件。
3.根据权利要求2所述的方法，其中，所述多个器件包括被构造成调节在沿着所述第一侧的平面中横向地流动的电流的水平半导体器件。
4.根据权利要求1所述的方法，其中，形成所述穿透开口包括利用激光钻孔工艺。
5.根据权利要求1所述的方法，其中，形成所述第一接触焊垫和所述第二接触焊垫包括利用电化学沉积工艺。
6.根据权利要求1所述的方法，进一步包括：
将所述再造晶片与所述载体分离；
对所述再造晶片进行减薄，以使所述多个半导体芯片从所述第二侧减薄；以及
在减薄之后，在第二侧接触区域下方形成第二侧导电板，其中，所述第二侧接触区域经由所述第二侧导电板耦接至所述第一接触焊垫。
7.根据权利要求6所述的方法，其中，所述多个半导体芯片中的每个被构造成调节从所述第一侧接触区域至所述第二侧接触区域的电流。
8.根据权利要求6所述的方法，其中，所述多个半导体芯片中的每个包括功率场效应晶体管，并且其中，所述第一侧接触区域为所述功率场效应晶体管的源极区域，并且所述第二侧接触区域为所述功率场效应晶体管的漏极区域。
9.根据权利要求8所述的方法，进一步包括：
在所述封装剂中形成第二接触开口；以及
通过用所述导电填充材料填充所述第二接触开口来形成用于所述功率场效应晶体管的栅极区域的第三接触焊垫。
10.根据权利要求6所述的方法，其中，形成所述第二侧导电板包括利用电化学沉积工艺来沉积结构化的第二侧导电板。
11.根据权利要求6所述的方法，其中，形成所述第二侧导电板包括沉积未结构化的第二侧导电板并且使所述未结构化的第二侧导电板结构化。
12.根据权利要求6所述的方法，其中，对所述多个半导体芯片进行减薄包括对具有位于硅基板上方的异质外延层的工件进行减薄，并且其中，所述减薄去除所述硅基板。
13.根据权利要求1所述的方法，其中，所述多个半导体芯片中的每个包括n沟道金属绝缘半导体场效应晶体管或p沟道金属绝缘半导体场效应晶体管。
14.根据权利要求1所述的方法，其中，所述半导体封装件具有的端子少于十个。
15.一种形成半导体封装件的方法，所述方法包括：
将多个功率半导体芯片设置在载体上方，所述多个功率半导体芯片中的每个具有位于第一侧和相对的第二侧上的源极接触区域和栅极接触区域，所述多个功率半导体芯片中的每个具有邻近所述第一侧的活性区域，其中，所述多个功率半导体芯片包括被构造成调节从所述第一侧朝向所述第二侧的方向上的竖直电流的芯片；
通过在所述多个功率半导体芯片和所述载体上方施加封装剂来形成再造晶片；
在所述封装剂中形成穿透开口；以及
在所述源极接触区域上方的所述封装剂中形成第一接触开口以及在所述栅极接触区域上方的所述封装剂中形成第二接触开口。
16.根据权利要求15所述的方法，进一步包括，通过使所述再造晶片单一化来形成独立封装件。
17.根据权利要求15所述的方法，其中，形成所述穿透开口包括利用激光钻孔工艺。
18.根据权利要求15所述的方法，其中，利用普通的工艺来形成所述穿透开口和所述第一接触开口。
19.根据权利要求15所述的方法，进一步包括：
通过用导电填充材料填充所述穿透开口来形成第一接触焊垫；
以及
通过用所述导电填充材料填充所述第一接触开口和所述第二接触开口来形成第二接触焊垫和第三接触焊垫。
20.根据权利要求19所述的方法，进一步包括，在形成所述第一接触焊垫、所述第二接触焊垫和所述第三接触焊垫之后，使所述再造晶片与所述载体分离。
21.根据权利要求19所述的方法，进一步包括：
通过研磨所述再造晶片对所述多个功率半导体芯片进行减薄；
以及
在减薄之后，在漏极接触区域下方形成第二侧导电板，其中，所述漏极接触区域经由所述第二侧导电板耦接至所述第一接触焊垫。
22.根据权利要求21所述的方法，其中，形成所述第二侧导电板包括利用电化学沉积工艺来沉积结构化的第二侧导电板。
23.根据权利要求21所述的方法，其中，形成所述第二侧导电板包括沉积未结构化的第二侧导电板并且使所述未结构化的第二侧导电板结构化。
24.一种形成半导体封装件的方法，所述方法包括：
形成半导体芯片，所述半导体芯片包括位于第一主表面上的第一接触区域和位于相对的第二主表面上的第二接触区域，其中，所述半导体芯片被构造成调节从所述第一接触区域至所述第二接触区域的电流；
在所述半导体芯片处形成封装剂；
在所述封装剂内形成第一接触插塞并且耦接至第一接触区域；
在所述第二主表面下方形成第二侧导电层并且耦接至所述第二接触区域；以及
在所述封装剂内形成通孔并耦接至所述第二侧导电层，其中，所述第一接触插塞和所述通孔在所述第一主表面上方形成用于接触所述半导体封装件的端子。
25.根据权利要求24所述的方法，进一步包括在所述封装剂内形成第二接触插塞并且在所述第一主表面上耦接至第三接触区域，其中，所述半导体封装件是三端子封装件。
26.根据权利要求24所述的方法，其中，所述半导体芯片是分立式三端子功率场效应晶体管。
27.根据权利要求24所述的方法，进一步包括在所述第二侧导电层下方形成散热器。
28.根据权利要求24所述的方法，其中，所述半导体封装件具有的端子少于十个。
29.根据权利要求24所述的方法，其中，所述半导体芯片包含硅。
30.根据权利要求24所述的方法，其中，所述半导体芯片包含氮化镓。
31.根据权利要求24所述的方法，进一步包括
在所述封装剂内形成第二半导体芯片，并且所述第二半导体芯片具有位于主表面上的第三接触区域和第四接触区域，其中，所述第二半导体芯片被构造成调节从所述第三接触区域至所述第四接触区域的电流；以及
在所述封装剂内形成第二接触插塞并且耦接至所述第三接触区域。
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