CN104347562A - 分段键合焊盘及其制造方法 - Google Patents

分段键合焊盘及其制造方法 Download PDF

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Publication number
CN104347562A
CN104347562A CN201410377224.4A CN201410377224A CN104347562A CN 104347562 A CN104347562 A CN 104347562A CN 201410377224 A CN201410377224 A CN 201410377224A CN 104347562 A CN104347562 A CN 104347562A
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China
Prior art keywords
pad
bonding welding
pad section
section
bonding
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CN201410377224.4A
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English (en)
Inventor
A·布里纳
H·布里施
M·齐格尔德鲁姆
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Infineon Technologies AG
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Infineon Technologies AG
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Publication of CN104347562A publication Critical patent/CN104347562A/zh
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Abstract

本发明公开了一种分段键合焊盘及其制造方法。根据本发明的实施例，一种半导体器件包括设置在衬底的第一侧处的第一键合焊盘。第一键合焊盘包括第一多个焊盘区段。第一多个焊盘区段中的至少一个焊盘区段与第一多个焊盘区段中的其余焊盘区段电隔离。

Description

分段键合焊盘及其制造方法
技术领域
本发明总体涉及一种半导体器件，并且更具体地涉及分段键合焊盘及其制造方法。
背景技术
半导体器件用于多种电子应用和其他应用中。半导体器件除了其他之外包括集成电路或分立器件，其通过在半导体晶片之上沉积一种或多种类型的材料薄膜、并且图案化材料薄膜以形成集成电路而形成在半导体晶片上。
半导体器件通常被封装在陶瓷或塑料本体内以保护半导体器件免受物理损伤或腐蚀。封装也支撑了将也称作裸片或芯片的半导体器件连接至封装外部的其他器件所需的电接触。取决于半导体器件的类型以及被封装的半导体器件的预期用途，许多不同类型的封装是可用的。
使用一个或多个接触焊盘或键合焊盘形成在半导体器件与其他器件之间的电连接。这些键合焊盘布置在半导体器件上。引线键合可以用于将半导体器件的键合焊盘电连接至芯片外部的部件。例如，在一些应用中，引线键合用于将半导体器件的键合焊盘连接至引线框架或衬底，除了其他之外。
取决于所实施的半导体器件的类型，许多不同类型的接线键合技术可以用于在部件之间建立这些电连接。可以使用球形键合、超声键合(例如楔形键合)或其他类型接线键合。
发明内容
根据本发明的实施例，一种半导体器件包括设置在衬底的第一侧处的第一键合焊盘。第一键合焊盘包括第一多个焊盘区段。第一多个焊盘区段中的至少一个焊盘区段与第一多个焊盘区段中的其余焊盘区段电隔离。
根据本发明的备选实施例，一种半导体器件包括设置在衬底的第一侧处的第一键合焊盘。第一键合焊盘包括第一部分和第二部分。第一键合焊盘的第一部分电耦合至衬底，并且第一键合焊盘的第二部分与衬底电隔离。
根据本发明的另一备选实施例，一种半导体器件包括具有第一侧的半导体芯片，以及设置在半导体芯片的第一侧处的第一键合焊盘。第一键合焊盘包括包含第一多个焊盘区段的第一部分和第二部分。第一多个焊盘区段中的焊盘区段与第一多个焊盘区段中的其余焊盘区段电隔离。第一外部互连接触第一键合焊盘的第一部分。
根据本发明的又一备选实施例，一种半导体器件包括具有第一侧的半导体芯片，以及设置在半导体芯片的第一侧处的第一键合焊盘。第一键合焊盘包括第一部分、以及与第一部分分隔开的第二部分。第一键合焊盘的第一部分电耦合至衬底，并且第一键合焊盘的第二部分与衬底电隔离。第一外部互连接触第一部分。
根据本发明的又一备选实施例，一种形成半导体器件的方法包括：在衬底之上形成隔离层，图案化隔离层以形成第一多个开口，以及通过采用导电材料至少部分地填充第一多个开口而形成包括多个键合焊盘区段的键合焊盘。
附图说明
为了更完整地理解本发明及其优点，现在参考结合了附图的以下描述，其中：
图1包括图1A和图1B，其中图1A示出了根据本发明实施例的半导体器件，而图1B示出了半导体器件性能的改进；
图2包括图2A和图2B，示出了根据本发明的实施例的半导体器件，其中图2A示出了具有键合焊盘的半导体芯片的顶视图，而图2B示出了具有键合焊盘的有源和无源区域的顶视图；
图3示出了根据本发明实施例的另一半导体器件；
图4包括图4A至图4C，示出了根据本发明实施例的半导体器件。图4A和图4B示出了半导体芯片的截面图，而图4C示出了半导体芯片的顶视图。
图5示出了根据本发明备选实施例的又一半导体器件；
图6示出了根据本发明备选实施例的又一半导体器件；
图7示出了根据本发明备选实施例的又一半导体器件；
图8包括图8A至图8F，示出了根据本发明实施例的用于制造半导体结构的一种方法；
图9包括图9A至图9D，示出了根据本发明实施例的用于制造半导体结构的另一方法；
图10包括图10A至图10D，示出了根据本发明实施例的半导体器件的键合焊盘的不同配置；
图11包括图11A和图11B，示出了根据本发明实施例的显示了夹具互连的半导体器件；
图12示出了根据本发明备选实施例的晶片级半导体封装；
图13包括图13A至图13D，示出了根据本发明实施例的用作半导体器件的焊料焊盘的键合焊盘的备选配置。
不同附图中对应的数字和符号通常指代对应的部件，除非另外说明。绘制附图以清晰的显示实施例的相关方面并且未必按照比率绘制。
具体实施方式
以下详细讨论各个实施例的制造和使用。然而应该知晓的是，本发明提供了可以在广泛多种具体环境中体现的许多可用的创新性概念。所描述的具体实施例仅仅是制造和使用本发明的具体方式的说明示例，并且并非限定本发明的范围。
在半导体器件技术中，寄生效应可以导致半导体芯片的电性能退化。这样的寄生效应可以由封装以及内部半导体芯片的部件所导致。一种这样的寄生效应来源于用于将半导体芯片耦合至外部电路的键合焊盘。作为示例，高性能器件的电性能可以受到源自键合焊盘的寄生电容的影响。例如，射频晶体管的特性随着漏极-源极或输出至接地电容增大而剧烈退化。类似地，电性能也可以随着栅极电容增大而退化。为了解决该问题，在一些应用中，降低了键合焊盘对于该电容值的贡献。特别地，通过最大化下层电介质堆叠的厚度或者通过采用低k材料最小化该材料的介电常数来降低键合焊盘电容。然而，仍残存重大缺点。例如，随着介电常数接近3.0或以下，接线键合的机械稳定性成为关注点。此外，电介质层的厚度可以在由后段制程金属化堆叠所确定的特定范围内改变。
本发明的各个实施例提供了一种具有分段键合焊盘的半导体器件，分段键合焊盘限制了键合焊盘的电有源区域。键合焊盘的第一部分是以连续方式而电有源的，而键合焊盘的第二部分被制造以使其提供机械支撑但是与接线键合隔离，由此减小了对键合焊盘电容作出贡献的焊盘面积。因此，无需改变电介质堆叠的厚度或介电常数，就可以减小由于键合焊盘而引起的寄生电容。
将使用图1描述本发明的结构性实施例。将使用图2至图5、图9和图10描述本发明的备选结构性实施例。将使用图6描述制造半导体器件的方法。将使用图7和图8描述制造半导体器件的备选实施例。
图1包括图1A和图1B，示出了本发明的实施例。图1A示出了根据本发明实施例的半导体器件，而图1B示出了半导体器件性能的对应改进。
参照图1A，半导体芯片10布置在衬底20上。在各个实施例中，半导体芯片10可以包括集成电路芯片或分立器件。在一个或多个实施例中，半导体芯片10可以包括逻辑芯片、存储器芯片、模拟芯片、混合信号芯片、分立器件、以及其组合，诸如芯片上系统，或者任何合适类型器件。半导体芯片10可以包括各种类型的有源和无源器件，诸如二极管、晶体管、晶闸管、电容器、电感器、电阻器、光电器件、传感器、微机电系统等。
在该说明性示例中，半导体芯片10附接至衬底20。衬底20在一些示例中可以是导电衬底。例如，衬底20在一个实施例中可以包括铜。在其他实施例中，衬底20包括金属材料，该金属材料可以包括导电金属及其合金。衬底20也可以包括金属间化合材料。
衬底20在一个实施例中可以包括引线框架。例如，在一个实施例中，衬底20可以包括裸片板(die paddle)，半导体芯片10可以附接在裸片板之上。第一和第二引线30和35也可以存在于该示例中。包括源极引线30A和漏极引线30B的第一引线30可以提供源极连接和/或漏极连接，而第二引线35可以在该实施例中提供栅极连接。在其他实施例中，衬底20可以包括在其之上可以附接一个或多个芯片的一个或多个裸片板。
在另一备选实施例中，衬底20可以不是导电的。在又一实施例中，若干不同或相同的半导体芯片10可以通过不同技术附接在衬底20上。
各个实施例在硅衬底上形成半导体芯片10。备选地，在其他实施例中，半导体芯片10可以已经形成在碳化硅(SiC)上，或者可以已经至少部分地形成在诸如氮化镓(GaN)之类的化合物半导体上。
在一些示例性示例中，半导体芯片可以包括功率半导体器件，其在一个实施例中可以是分立器件。在一个示例中，半导体芯片10是双端子器件，诸如PIN二极管或肖特基二极管。在其他示例中，半导体芯片10是三端子器件，诸如功率金属绝缘体半导体场效应晶体管(MISFET)、结型场效应晶体管(JFET)、双极结型晶体管(BJT)、绝缘栅双极型晶体管(IGBT)或晶闸管。在另外其他示例中，半导体芯片10可以是横向扩散金属氧化物半导体(LDMOS)。
如所述，半导体芯片10包括键合焊盘40(也称作接触焊盘或简单地焊盘)。在该示例性示例中，键合焊盘40沉积在半导体芯片10的上表面上。在其他示例中，半导体芯片10可以包括在一个或多个其他表面上的额外的键合焊盘。例如，半导体芯片10可以包括在其底表面上的键合焊盘。
在该实施例中，半导体芯片10上的每个键合焊盘40具有与第二部分60分隔开的第一部分50。多个接线70将键合焊盘40的第一部分50电连接至第一和第二引线30和35。键合焊盘40的第一部分50和第二部分60中的一个或多个可以是分段的，如参照图2至图5详细所示。在一些实施例中，仅仅在半导体芯片10上的一些键合焊盘40具有第一部分50和第二部分60。例如在一些实施例中，键合焊盘40可以包括第一键合焊盘40A、第二键合焊盘40B以及第三键合焊盘40C。
在一个实施例中，接线70形成作为楔形键合。在楔形键合期间，向接线施加压力和超声力以在半导体芯片10的键合焊盘40上形成楔形键合。接线延伸至外部接触，诸如第一引线30，从而在键合焊盘和引线指之间形成了渐进的接线弧。再次向接线施加压力和超声力，从而在引线指上形成楔形键合，并且随后使用夹持装置断裂接线。该技术可以用于形成如图1所示的楔形键合。在各个实施例中，每个接线70的楔形部分被称为键合足部。例如，在该实施例中，示出了键合足部75。自然，可以使用其他技术以沉积接线70。
在备选实施例中，球形键合可以用于接线70。采用球形键合，首先通过熔化引线的端部形成金属球。球放置在键合焊盘上，并且向球施加压力、热量和超声力持续特定时间量。结果，在球与键合焊盘之间形成了冶金学焊接。类似于楔形键合，接线延伸至其中形成了另一键合的外部接触，接线被切断，并且针对用于对半导体器件的额外引线键合工艺自身重复。第二键合可以是楔形键合、针脚式键合或一些其他类型键合。
在一个或多个实施例中，用于接线70的接线键合材料除了其他之外还可以包括铜、铝、和金。在其他实施例中，接线键合材料可以包括钨、钛、钽、钌、镍、钴、铂、银以及其他材料。在各个实施例中，键合焊盘40可以包括前述材料的一种或多种。在该示例中，键合焊盘40包括金。
半导体芯片10、衬底20、接线70以及互连71均可以嵌入在包封剂25中。在各个实施例中，包封剂25包括电介质材料并且在一个实施例中可以包括模塑化合物。在一个或多个实施例中，包封剂25可以包括聚合物、共聚物、生物高聚物、纤维浸渍聚合物(例如树脂中的碳或玻璃纤维)、颗粒填充聚合物、以及其他有机材料的一种或多种。在另外其他示例性示例中，包封剂25可以包括不使用模塑化合物形成的包封剂，以及诸如环氧树脂和/或硅树脂之类的材料。在各个实施例中，包封剂25可以由任何合适的硬质塑料、热塑塑料、热固塑料、或叠层制成，并且在一些实施例中可以包括填充物材料。在其他实施例中，包封剂25可以包括环氧材料，以及包括小玻璃颗粒或类似氧化铝或有机填充材料的其他电绝缘矿物填充物材料的填充材料。
键合足部75可以具有如下长度(Lbf)，该长度为键合焊盘40的长度(Lbp)的约0.2至约0.7倍，例如在一个实施例中约0.5Lbp。在各个实施例中，键合足部75尽可能形成小，也即处于对于技术而言的最小特征尺寸。在各个实施例中，选择第一部分50与第二部分60的比率以最大化半导体芯片10的性能。这使用图1B进一步描述。
参照图1B，该曲线图示意性地示出了，改变第一部分50的面积与第二部分60的面积的效应。因为第一部分50的面积直接电连接至下层部件，所以增大第一部分50的面积导致在接线70和键合焊盘40之间的界面处的电阻减小。然而，该电阻下降相当快速。为了显示该效应，在图1B中示出了第一部分50的宽度W相对于键合焊盘40的长度(Lbp)的比率。然而，增大第一部分50也增大了键合焊盘40的寄生电容。因此，存在最优工作范围，在该范围下电阻和电容被最小化。因此，在各个实施例中，比率W:Lbp至少为0.1:1以最小化电阻。然而，在各个实施例中，比率W:Lbp不大于0.7:1以最小化寄生电容。在各个实施例中，降低了焊盘电容而不牺牲接触电阻。
图2包括图2A和图2B，示出了根据本发明实施例的半导体器件。特别地，图2A示出了具有键合焊盘的半导体芯片的放大顶视图，而图2B示出了突出键合焊盘的有源和无源区域的顶视图。在一个实施例中，图2示出了图1所示半导体芯片10的放大图。
参照图2A，示出了具有键合焊盘40的半导体芯片10的顶视图。如该实施例中所示，键合焊盘40包括第一部分50和第二部分60。在各个实施例中，键合焊盘40的直径可以为50－250μm，取决于用于半导体芯片10的接线键合类型。在一些实施例中，可能需要最小化键合焊盘的尺寸以进一步减小键合焊盘至衬底的电容。键合焊盘40的尺寸可以取决于各种因素，诸如键合焊盘节距和键合焊盘足部宽度，除了其他因素之外。
在这些示例中，第一部分50可以是连续部分，而第二部分60被分段为多个焊盘区段80。沟槽90存在于每个焊盘区段80之间。在键合焊盘40的第二部分60中的沟槽90分隔了焊盘区段80并且使得隔离的焊盘区段80无源，而仍然机械地存在于这些示意性示例中。在各个实施例中，沟槽90宽度可以是0.2－5μm。特别地，在一些实施例中沟槽90宽度可以是2－3μm以进一步最小化键合焊盘40的尺寸。在各个实施例中，沟槽90宽度与多个焊盘区段80的每一个的长度(或宽度)的比率约1:2至约1:50，并且在一个实施例中是1:10。
如从该示意性示例所见，在一些实施例中，形成沟槽90以使得焊盘区段80看起来从接线的方向(“D1”)旋转了45度。在该配置中，焊盘区段80可以在接线键合工艺期间对于剪切应力具有更大的容限。在备选实施例中，可以不同地配置沟槽90以帮助增大键合焊盘40的第二部分60的剪切强度。
在各个实施例中，可以采用诸如电介质材料之类的隔离材料填充一个或多个沟槽90。电介质材料在一个或多个实施例中可以包括氮化物。在其他实施例中，电介质材料可以包括氧化物、碳化硅、氮氧化硅、氧化铪、氧化铝、其他介电常数材料、聚酰亚胺、以及其他有机材料。在另外其他示例性实施例中，电介质材料可以包括可以采用空气填充的间隙。
如所示，键合焊盘40的第一部分50沿着方向D1具有80μm的宽度(“W”)。在其他实施例中，键合焊盘40的第一部分50可以具有其他宽度，诸如60μm、100μm、120μm以及其他合适宽度。
具有第一键合足部100的第一接线布置在键合焊盘40之上。特别地，第一键合足部100的一个部分布置在第一部分50上，而第一键合足部100的另一部分布置在键合焊盘40的第二部分60上。第一键合足部100是图1所示楔形接线键合的键合足部75的一个示例。在其中使用球形键合的备选实施例中，第一键合足部100的形状可以是圆形，或者取决于其中金属接线熔化至键合焊盘40的方式而可以具有可变形状。
在各个实施例中，第一键合足部100可以使用许多对准工具布置在键合焊盘40上。在一个示例中，第一键合足部100长度约为60μm，而40μm布置在键合焊盘40的第一部分50上。
具有第二键合足部105的第二接线键合与第一键合足部100间隔开。第二键合足部105长度也约为60μm，而约40μm布置在键合焊盘40的第一部分50上。额外的接线键合在各个实施例中也可以布置在键合焊盘40上。在各个实施例中，第一键合足部100和第二键合足部105由金、铜或铝制成。在一个实施例中，第一键合足部100和第二键合足部105由金制成，并且具有120μm的接线节距，该节距是第一键合足部100和第二键合足部105的中心之间的距离。
注意的是，仅为了解释说明，并未示出直接位于第一键合足部100或第二键合足部105之下或者与其重叠的焊盘区段。
在备选实施例中，具有键合焊盘40的半导体芯片10包括由铜构成的第一键合足部100和第二键合足部105。在该备选实施例中，第一键合足部100和第二键合足部105可以具有160μm的最小节距。在各个实施例中，因为较厚的接线，铜接线键合的尺寸大于金接线键合。因此，第一部分50的尺寸和/或接线与第一部分50之间的重叠可以改变。在该示例中，上部部分60具有80μm的宽度。如果接线与第一部分50的重叠被维持为如之前实施例(例如约40μm)那样，由于与较厚接线相关联的长键合足部，与第二部分60的重叠增大。因此，在各个实施例中，重叠了第一部分50的键合足部的长度、与重叠了第二部分60的键合足部的长度的比率是约5:1至约1:5，并且在一个实施例中是约2:3。
在又一实施例中，第一键合足部100和第二键合足部105由具有例如160μm最小节距的铜构成。如所示，第一部分50具有约100μm的宽度W，并且因此键合焊盘40的比之前实施例更多的部分被包括在有源区域110中。因此，在各个实施例中，重叠了第一部分50的键合足部的长度、与重叠了第二部分60的键合足部的长度的比率在所示中约3:2。
图2B示出了具有有源区域110和无源区域120的半导体芯片10。在该实施例中，有源区域110对应于电活性的键合焊盘40的区域。
如所示，有源区域110包括第一部分50和直接连接至第一键合足部100和第二键合足部105的焊盘区段80。直接位于第一和第二键合足部100和105下方的焊盘区段80是有源区域110的一部分。并未直接连接至第一和第二键合足部100和105的焊盘区段80形成了无源区域120，并且在该示例性示例中与有源焊盘区段80电隔离。
焊盘区段80之间的沟槽90用于将无源区段与有源区段隔离。因此，沟槽90具有足以隔离每个区段的宽度。该宽度可以取决于所使用的半导体芯片的类型而改变。
在各个实施例中，重叠了第一部分50的键合足部的长度、与重叠了第二部分60的键合足部的长度的比率是约5:1至约1:5，例如1:1。在其他示例中，比率可以是2:1至约1:2，或者一些其他合适比率。
采用包括无源焊盘区段80的示例性实施例，可以通过减小键合焊盘40的有源区域110而减小寄生键合焊盘电容。结果，半导体芯片10可以更有效果地和有效率地工作。
图3示出了根据本发明实施例的半导体器件。在该示例中，第一键合足部100和第二键合足部105可以包括诸如金的导电材料，并且具有120μm的最小接线节距。第一键合足部100和第二键合足部105被布置以使得约60μm连接至键合焊盘40的第一部分50，而约20μm连接至键合焊盘40的第二部分60中的焊盘区段80。因此，在该示例中，重叠了第一部分50的键合足部的长度、与重叠了第二部分60的键合足部的长度的比率约为3:1。
在该实施例中，示出了键合焊盘40的有源区域110。有源区域110包括第一部分50，以及直接连接至第一键合足部100和第二足部105的焊盘区段80。
类似于图2B中所示实施例，在该实施例中的沟槽90将并未直接接触第一和第二键合足部100和105的焊盘区段80与键合焊盘40的有源区域110电隔离。结果，形成了无源区域120。因此，仅有源区域110在该示例性实施例中对于寄生键合焊盘电容有贡献。额外地，并未包括在区域120中的区域60的一部分提供了机械支撑，并且增大了接线键合的剪切强度。
图4包括图4A至图4C，示出了根据本发明实施例的半导体器件。图4A示出了沿着图4C中的线4A-4A截取的半导体芯片10的截面图，图4B示出了沿着图4C中的线4B-4B截取的半导体芯片10的截面图，而图4C示出了半导体芯片10的顶视图。
参照图4A和图4B，键合焊盘40形成在衬底20之上。衬底20可以包括形成在其内的有源器件。一组金属化层130设置在衬底20之上，其在各个实施例中可以包括一层或多层金属引线以及过孔。例如，金属化层130在一个实施例中可以包括十个或更多金属层。在另一实施例中，金属化层130可以包括三个金属层。在另一实施例中，金属化层130可以包括两层。
金属化层130在一个实施例中可以耦合半导体芯片内的各个器件。在另一实施例中，金属化层130形成了至分立半导体器件的不同区域的接触。
在各个实施例中，键合焊盘40耦合至衬底20中的有源器件，诸如第一器件140。第一器件140在各个实施例中可以是晶体管、电容器、二极管、晶闸管和其他器件。键合焊盘40在一个实施例中可以是多层金属化层的顶部金属化层。设置在金属化层130内的多个金属引线和过孔可以将衬底20中的有源器件与键合焊盘40耦合。
为了简明，图4A和图4B示出了两层金属化层。金属化层130具有第一过孔层V1，第一金属层M1，以及耦合至键合焊盘40的第二过孔层V2。在一个实施例中，键合焊盘40是形成在半导体芯片10的最顶部金属层上的金属层。
每个金属化层可以包括层间电介质层。例如，第一层间电介质层150沉积在衬底20之上。第二层间电介质层155沉积在第一层间电介质层150之上。
层间电介质层可以由刻蚀停止衬垫分隔开。例如，第一刻蚀停止衬垫160沉积在第一和第二层间电介质层150和155之间。第二刻蚀停止衬垫165沉积在第二层间电介质层155与键合焊盘40之间。
在所示实施例中，使用双大马士革工艺形成构成了金属引线和过孔的导电特征(例如在M1、V1、V2中)。在备选实施例中，可以使用大马士革工艺或者单大马士革和双大马士革工艺的组合来形成导电特征。
每个导电特征可以包括金属衬垫，其可以包括多个层。例如，金属衬垫在一些实施例中可以包括第一金属衬垫170和第二金属衬垫175。第一金属衬垫170可以是扩散阻挡层，而第二金属衬垫175可以是种子层。如图4A所示，键合焊盘40包括多个沟槽90。
在图4A和图4B中，填充物材料180可以至少部分地填充沟槽90。填充物材料180可以是电介质材料，诸如氧化物或者参照图2所讨论的其他材料。
在其他示例中，填充物材料180可以包括包封剂。在各个实施例中，包封剂包括如上所述的电介质材料。
如所示，第一键合足部100形成了至两个焊盘区段80的电连接。由含有填充物材料180的沟槽90将其他焊盘区段80与第一键合足部100电隔离。如此方式，仅键合焊盘40的电有源区域对于寄生键合焊盘电容有贡献，但是其余的焊盘区段80有助于接线键合的机械稳定性而同时保持电无源。结果，寄生键合焊盘电容可以减小例如40－60％。为了示意说明，仅示出了键合焊盘40的一部分。因此，图4所示焊盘区段的数目可以不代表真实的截面。
图4C示出了顶视图，并且示出了沟槽90散布在键合焊盘40内。每个键合焊盘40可以包括沟槽90的阵列，其形成了如图1至图5所示的焊盘区段80。图4C作为示例仅示出了五行和六列。
图5示出了根据本发明备选实施例的又一半导体器件。图5是类似于图4A的截面图。在该实施例中，填充物材料180仅填充了键合焊盘40的焊盘区段80之间的一部分沟槽90。例如，填充物材料180可以填充沟槽90的50％。备选地，填充物材料180可以填充更多或者更少沟槽90，取决于涉及的功能。在另外其他示例中，一些沟槽90可以包括填充物材料180，而其他沟槽90包括较少或者不包括填充物材料180。
图6示出了根据本发明备选实施例的又一半导体器件。图6是类似于图4A的截面图。在该实施例中，并未采用绝缘材料填充在键合焊盘40的焊盘区段80之间的沟槽90。
图7示出了根据本发明备选实施例的又一半导体器件。图7是类似于图4B的截面图。图7示出了不使用大马士革工艺形成的键合焊盘。因此，图7中的键合焊盘可以不具有如图4至图6所示的连续填充材料。在一个实施例中，图7中的键合焊盘40包括铝焊盘，其可以使用诸如氮化钛或氮化钨的阻挡衬垫保护。备选地，在另一实施例中，键合焊盘40可以包括金焊盘，并且可以不包括额外的阻挡层或保护衬垫。
图8包括图8A至图8F，示出了根据本发明实施例的用于制造半导体结构的一种方法。图8A示出了在形成分段键合焊盘之前的图4至图6的半导体器件。在该实施例中，第三层间电介质层157形成在第二刻蚀停止衬垫165之上。第一掩模层190形成在第三层间电介质层157之上。第一掩模层190可以例如是光刻胶层。在一个实施例中，穿过第一掩模层190形成开口195以暴露第三层间电介质层157。
在附图8B中，开口195延伸穿过第三层间电介质层157并且停止在第二刻蚀停止衬垫165处。第一掩模层190在该实施例中已经移除。
在附图8C中，开口195进一步延伸穿入第二层间电介质层155中并且穿过第二刻蚀停止衬垫165。在该实施例中随后采用第二掩模层200填充开口195。
如图8D所示图案化第二掩模层200。图案化第二掩模层200以使得可以形成一个或多个开口202。
在附图8E中，开口202延伸穿过第三层间电介质层157。开口202在该示例中将变成焊盘区段80。
如所示，图案化的第二掩模层200用作掩模与刻蚀工艺组合以刻蚀第三层间电介质层157。完成各个实施例中的刻蚀以形成所需的几何形状。例如，可以完成刻蚀以对于焊盘区段80形成形状为三角形、四边形、圆形、六边形或一些其他配置的第二开口202，例如如图9所示。在一些实施例中，也可以刻蚀第二刻蚀停止衬垫165、第二层间电介质层155、以及第一刻蚀停止衬垫160的一个或多个。
图8F示出了已经在半导体芯片10之上形成阻挡层和/或种子层并且导电材料已经沉积在每个开口202中之后的半导体芯片10。采用导电材料填充的开口202形成了用于键合焊盘40的焊盘区段80。导电材料可以包括金属或金属合金，如参照图1所述。
在备选实施例中，刻蚀工艺可以移除沟槽90中的电介质材料。接着，可以采用填充物材料180部分或者完全填充沟槽90。换言之，可以通过在开口202中生长种子层和/或沉积导电材料形成焊盘区段80。备选地，可以沉积并且刻蚀连续的金属层以使得形成沟槽90。可以采用填充物材料180填充沟槽90。
在已经根据需要形成沟槽90和焊盘区段80之后，一个或多个接线键合可以沉积在键合焊盘40的表面上。与接线键合直接接触的焊盘区段80可以是电有源的，而不与接线键合直接接触的焊盘区段80保持无源。
图9包括图9A至图9D，示出了根据本发明实施例的用于制造半导体结构的另一方法。图9A示出了在形成分段键合焊盘之前的图7的半导体器件。
参照图9A，在形成了金属化层130的金属引线和过孔之后，沉积导电层310。导电层310包括在各个实施例中使用减式刻蚀技术而可图案化的金属。例如，在一个实施例中，可以在沉积铝层之后沉积包括诸如氮化钛之类的第一保护衬垫的层堆叠。额外的氮化钛层可以沉积在铝层之上。导电层310被沉积为在衬底20之上的毯式层。在各个实施例中，可以使用任何合适的沉积工艺沉积导电层310，诸如溅射、气相沉积等等。
参照图9B，抗蚀剂层320形成在未结构化的导电层310之上并且图案化。抗蚀剂层320在一个实施例中可以包括硬掩模层。在一个实施例中可以使用传统的光刻技术图案化抗蚀剂层320。在其他实施例中，其他方法可以用于形成结构化的抗蚀剂层320，例如丝网印刷、模压、印刷等等。
接着如图9C所示，使用抗蚀剂层320作为刻蚀掩模，图案化导电层310。在一个实施例中可以使用反应离子刻蚀图案化导电层310。在其他实施例中，可以使用其他类型的刻蚀或者剥离工艺。
接着参照图9D，在一些实施例中，诸如填充物材料180之类的另一电介质材料可以可选地引入焊盘区段80之间的沟槽90中。如果需要的话可以进行如前所述的进一步处理。
图10包括图10A至图10D，示出了根据本发明实施例的半导体器件的键合焊盘的不同配置。图10A示出了四边形焊盘区段设计，而图10B示出了蜂巢式焊盘区段设计。图10C示出了蜂巢式焊盘区段，其中焊盘区段的第一行已经与焊盘区段的未结构化部分合并。图10D示出了用于球形键合的焊盘区段配置。
参照图10A，焊盘区段80的部分204具有四边形形状。在一些实施例中，焊盘区段的每条侧边的长度可以约为20μm。在该示例中每个焊盘区段80之间的沟槽90可以约为3μm宽。在其他实施例中，焊盘区段80的侧边长度和/或沟槽90的宽度可以是不同尺寸，取决于实施方式。例如，沟槽90之间的节距可以是2μm、4μm、5μm，或者一些其他合适的距离。
如从该示例性示例可见，焊盘区段80从水平旋转45度。换言之，沟槽90对角地形成在键合焊盘40上以使得焊盘区段80可以例如在楔形键合期间对于横向剪切应力不敏感。因此，在该实施例中的焊盘区段80抵抗键合期间的剪切应力并且提供了用于接线键合的坚固的机械连接。
在图10B中，键合焊盘40的第二部分60的部分204示出具有蜂巢式配置。采用该配置，每个焊盘区段80可以包括具有例如20μm直径的六边形。
如所示，围绕每个焊盘区段80的所有六个侧边形成沟槽90。在该实施例中沟槽90可以比图10A中的沟槽90更小、更大、或者相同尺寸。类似于图10A中的四边形形状，图10B中的焊盘区段80的六边形形状可以提供机械稳定性并且限制了在接线键合期间横向剪切应力的效应。
参照图10C，在一个或一些实施例中，第一部分50也可以被图案化以便包括与第二部分60的图案对准的边缘和侧壁。因此，在该实施例中，六边形部分从第一部分50朝向其他焊盘区段80延伸。
在备选实施例中，在图10D中示出了用于焊盘区段80的球形键合配置。该配置可以用于球形键合逻辑芯片或一些其他低功耗器件的键合焊盘40。在该实施例中，焊盘区段80被划分成布置在第一部分50周围在部分204中的圆形区段。
在该示例中，球形键合的有源区域110是键合焊盘40的中心圆形部分，其对应于第一部分50。无源区域120在该示例性实施例中包括基本上所有焊盘区段80。换言之，球形键合在各个实施例中可以布置为仅电连接键合焊盘40的第一部分50。
沟槽90围绕每个焊盘区段80并且连续地在有源区域110周围延伸以提供焊盘区段80与无源区域110的电隔离。焊盘区段80的该实施例也可以提供所需的剪切强度，而同时限制了器件的寄生键合焊盘电容。
可以参照其他示例性实施例实现焊盘区段80的其他变形和配置。例如，焊盘区段80可以是圆柱形、八边形、圆形、三角形、或者布置在一些其他配置中。此外，在一些实施例中，焊盘区段80的直径可以大于或者小于20μm。在另外其他实施例中，一些焊盘区段80可以具有相互不同的直径或者可以相互不同地间隔开。自然，受教于本公开的本领域技术人员可以取决于特定实施方式而设计这些焊盘区段80以符合所需的规范。
图11包括图11A和图11B，示出了根据本发明实施例的示出了夹具互连的半导体器件。图11A示出了顶视图，而图11B示出了截面图。
在该实施例中，例如耦合至源极节点的第一键合焊盘40A可以通过在一个实施例中为夹具的互连71而耦合至第一引线30。在另一实施例中，互连71可以是条带或板。互连71可以是具有比接线键合更低电阻的板状结构。因此，在一些实施例中，高电流路径可以使用夹具互连，而低电流路径可以使用接线键合。例如耦合至栅极节点的诸如第二键合焊盘40B之类的其他键合焊盘可以耦合至第二引线35。如所示，漏极引线30B可以直接通过衬底20的裸片板而耦合至半导体芯片10上的漏极键合焊盘，例如，漏极键合焊盘可以设置在半导体芯片10的朝向裸片板的相对侧边上。
如之前实施例所示，互连71耦合至第一键合焊盘40A以使其与第一部分50重叠，并且也与包括焊盘区段80的第二部分60重叠。位于键合足部75下方的该重叠区域是电耦合的并且有源，但是与第一键合焊盘40A的其他焊盘区段80隔离。如之前实施例中，半导体芯片10、衬底20、接线70以及互连71均可以嵌入在包封剂25中。
图12示出了根据本发明备选实施例的晶片级半导体封装。
本发明的实施例也可以应用于诸如晶片级处理(WLP)封装之类的半导体封装中的键合焊盘。例如，图12示出了包括多个键合焊盘的扇出半导体封装。半导体封装的多个键合焊盘40的一个或多个可以包括如根据本发明各个实施例中所述的焊盘区段80。键合焊盘40可以设置在包封剂25中，其可以通过重分布引线耦合至衬底10。
图13包括图13A至图13D，示出了根据本发明实施例的用于半导体器件的焊料焊盘的键合焊盘的备选配置。
与之前实施例不同，在该实施例中，焊接分段键合焊盘。因此，在该实施例中，可以跨键合焊盘的许多区域划分固体部分。图13A示出了如之前所述由可选的填充物材料180围绕的键合焊盘40的顶视图。然而在该实施例中，作为焊盘区段40的有源焊盘区段81的区域耦合至下方的衬底20。作为焊盘区段40的隔离焊盘区段82的剩余区域与有源焊盘区段81隔离。因此，一个或多个焊料球键合290可以形成在键合焊盘40之上。通过改变有源焊盘区段81的设计和图案，可以建立合适的接触，也即可以将键合焊盘的接触电阻控制在可接受限制内。图13A示出了其中由隔离焊盘区段82分隔有源焊盘区段81的图案。在各个实施例中，有源焊盘区段相对于焊料球间距的相对节距可以随着有源焊盘区段的密度(尺寸)而改变。在一个或多个实施例中，有源焊盘区段Ap的节距可以小于焊料球键合Sp的节距。这确保了每个焊料球键合焊盘290在下方具有至少一个有源焊盘区段81。在各个实施例中，一个或多个有源焊盘区段81可以存在于每个焊料球下方。在形成焊料球键合290之后，包括在焊料球键合290下方的一些隔离焊盘区段82的所有焊盘区段80电耦合。在图13B中，有源焊盘区段81形成为细长的区段。在不同的备选实施例中，每个有源焊盘区段81具有一个焊料球键合290。例如，该实施例可以用于确保每个焊料球与相同接触电阻耦合。
本发明的实施例也包括用于有源焊盘区段的其他设计。例如，在另一实施例中，在图13D中，星状配置用于改进接触电阻。在该实施例中，四个有源焊盘区段81设置在每个焊料球键合290之下。
此外，焊盘区段80在各个实施例中可以形成为各种形状和图案。在一个或多个实施例中，焊盘区段80可以是方形、六边形、任意形，例如如图10D中所示焊料焊盘区段80的围绕焊料球至键合焊盘40的接触点中心的同心布置。在各个实施例中，图10的设计可以与图13组合。
本发明各个实施例提供了键合焊盘和通过对键合焊盘的一部分分段而大大减小键合焊盘至衬底电容的制造半导体芯片的方法。示例性实施例可以用于在各种应用中的键合焊盘。例如，分段键合焊盘可以用于半导体工业中的高频(例如0.1－100GHz或更高)低功耗和高功耗产品。
示例性实施例提供了在分立芯片和逻辑芯片上源极、漏极或栅电极的一个或多个上的键合至衬底电容中的优点，除了其他之外。采用低功耗应用，示例性实施例增大了信号性能。采用高功耗应用，示例性实施例改进了功率效率。
此外，示例性实施例可以用于各个类型键合。例如，采用高功耗应用，使用超声键合，也即楔形键合。在诸如具有逻辑芯片的低功耗应用中，可以使用球形键合。各个实施例提供了对于球形键合、楔形键合和其他合适的接线键合技术的优点，以减小键合焊盘至衬底电容，而同时维持了合适的电连接和机械连接。
如各个实施例中所述，包括金属的材料可以例如是纯金属、金属合金、金属化合物、金属间化合物等等，也即包括金属原子的任何材料。例如，铜可以是纯铜或者包括铜的任何材料，诸如但不限于铜合金、铜化合物、或铜金属间化合物。
尽管已经参照示例性实施例描述了本发明，但是该说明书并不旨在以限制性疑义进行解释。一旦参照了说明书，示例性实施例的各种修改和组合以及本发明其他实施例对于本领域技术人员而言是明显的。作为示例，图1至图13中所述实施例可以在备选实施例中相互组合。因此意在使得所附权利要求包括任何这些修改例或实施例。
尽管已经详细描述了本发明及其优点，但是应该理解的是在本文中可以不脱离由所附权利要求限定的本发明的精神和范围而做出各种改变、替换和变更。例如，对于本领域技术人员而言易于理解的是，可以改变在此所述的许多特征、功能、工艺和材料而同时保持在本发明的范围内。

Claims (27)

1.一种半导体器件，包括：
设置在衬底的第一侧处的第一键合焊盘，所述第一键合焊盘包括第一多个焊盘区段，其中所述第一多个焊盘区段中的至少一个焊盘区段与所述第一多个焊盘区段中的其余焊盘区段电隔离。
2.根据权利要求1所述的器件，进一步包括与设置在所述第一侧处的所述第一键合焊盘间隔开的第二键合焊盘，所述第二键合焊盘包括第二多个焊盘区段，其中所述第二多个焊盘区段中的至少一个焊盘区段与所述第二多个焊盘区段中的其余焊盘区段电隔离。
3.根据权利要求2所述的器件，其中所述第一键合焊盘耦合至晶体管的源极节点，并且其中所述第二键合焊盘耦合至所述晶体管的栅极节点。
4.根据权利要求2所述的器件，其中所述第一键合焊盘耦合至晶体管的漏极节点，并且其中所述第二键合焊盘耦合至所述晶体管的栅极节点。
5.根据权利要求1所述的器件，其中所述第一多个焊盘区段中的每个焊盘区段通过多个开口与所述第一多个焊盘区段中的相邻焊盘区段分隔开。
6.根据权利要求5所述的器件，其中所述多个开口包括电介质材料。
7.根据权利要求1所述的器件，其中所述半导体器件包括分立半导体器件。
8.根据权利要求1所述的器件，其中所述半导体器件包括集成电路。
9.根据权利要求1所述的器件，其中所述第一键合焊盘是焊料焊盘。
10.一种半导体器件，包括：
设置在衬底的第一侧处的第一键合焊盘，所述第一键合焊盘包括第一部分和第二部分，其中所述第一键合焊盘的所述第一部分电耦合至所述衬底，以及其中所述第一键合焊盘的所述第二部分与所述衬底电隔离。
11.根据权利要求10所述的器件，其中所述第一键合焊盘的所述第一部分和所述第二部分被配置为耦合至第一共用外部互连。
12.根据权利要求10所述的器件，其中所述第二部分包括多个焊盘区段，其中所述多个焊盘区段中的至少一个焊盘区段与所述多个焊盘区段中的其余焊盘区段电隔离。
13.根据权利要求12所述的器件，其中所述多个焊盘区段中的每个焊盘区段通过多个开口与所述多个焊盘区段中的相邻焊盘区段分隔开。
14.根据权利要求13所述的器件，其中所述多个开口包括电介质材料。
15.根据权利要求10所述的器件，进一步包括，与设置在所述第一侧处的所述第一键合焊盘间隔开的第二键合焊盘，所述第二键合焊盘包括第一部分和第二部分，其中所述第二键合焊盘的所述第一部分电耦合至所述衬底，以及其中所述第二键合焊盘的所述第二部分与所述衬底电隔离。
16.根据权利要求15所述的器件，其中所述第一键合焊盘的所述第二部分包括第一多个焊盘区段，其中所述第一多个焊盘区段中的至少一个焊盘区段与所述第一多个焊盘区段中的其余焊盘区段电隔离，其中所述第二键合焊盘的所述第二部分包括第二多个焊盘区段，其中所述第二多个焊盘区段中的至少一个焊盘区段与所述第二多个焊盘区段中的其余焊盘区段电隔离。
17.一种半导体器件，包括：
具有第一侧的半导体芯片；
设置在所述第一半导体芯片的所述第一侧处的第一键合焊盘，所述第一键合焊盘包括第一部分和第二部分，所述第二部分包括第一多个焊盘区段，其中所述第一多个焊盘区段中的焊盘区段与所述第一多个焊盘区段中的其余焊盘区段电隔离；以及
接触所述第一键合焊盘的所述第一部分的第一外部互连。
18.根据权利要求17所述的器件，其中所述第一外部互连接触所述第一多个焊盘区段中的焊盘区段。
19.根据权利要求17所述的器件，其中所述第一外部互连包括接线键合、夹具或条带。
20.根据权利要求17所述的器件，进一步包括：
与设置在所述第一侧处的所述第一键合焊盘间隔开的第二键合焊盘，所述第二键合焊盘包括第一部分和第二部分，所述第二部分包括第二多个焊盘区段，其中所述第二多个焊盘区段中的至少一个焊盘区段与所述第二多个焊盘区段中的其余焊盘区段电隔离；以及
接触所述第二键合焊盘的所述第一部分的第二外部互连。
21.根据权利要求20所述的器件，其中，所述第一外部互连包括接线键合并且所述第二外部互连包括夹具。
22.一种半导体器件，包括：
包括衬底并且具有第一侧的半导体芯片；
设置在所述半导体芯片的所述第一侧处的第一键合焊盘，所述第一键合焊盘包括第一部分以及与所述第一部分分隔开的第二部分，其中所述第一键合焊盘的所述第一部分电耦合至所述衬底，并且其中所述第一键合焊盘的所述第二部分与所述衬底电隔离；以及
接触所述第一部分的第一互连。
23.根据权利要求22所述的器件，其中所述第二部分包括多个焊盘区段，其中所述多个焊盘区段中的至少一个焊盘区段与所述多个焊盘区段中的其余焊盘区段电隔离。
24.根据权利要求23所述的器件，其中所述多个焊盘区段中的每个焊盘区段通过多个开口与所述多个焊盘区段中的相邻焊盘区段分隔开。
25.一种形成半导体器件的方法，所述方法包括：
在衬底之上形成导电层；以及
通过图案化所述导电层形成包括多个键合焊盘区段的键合焊盘，其中所述多个焊盘区段中的至少一个焊盘区段与所述多个焊盘区段中的其余焊盘区段电隔离。
26.根据权利要求25所述的方法，进一步包括将外部互连附接至所述键合焊盘，其中在所述键合焊盘与所述外部互连之间的接触区域与所述多个键合焊盘区段中的一个或多个键合焊盘区段重叠。
27.根据权利要求25所述的方法，进一步包括：
采用电介质材料填充在所述多个键合焊盘区段中的每个键合焊盘区段之间的开口。
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