CN1773699A - 具有环形硅退耦电容器的集成电路芯片封装及其制造方法 - Google Patents

具有环形硅退耦电容器的集成电路芯片封装及其制造方法 Download PDF

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CN1773699A
CN1773699A CNA2005101203004A CN200510120300A CN1773699A CN 1773699 A CN1773699 A CN 1773699A CN A2005101203004 A CNA2005101203004 A CN A2005101203004A CN 200510120300 A CN200510120300 A CN 200510120300A CN 1773699 A CN1773699 A CN 1773699A
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decoupling capacitor
bonding
chip
encapsulation
circuit substrate
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CNA2005101203004A
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宋垠锡
李稀裼
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN1773699A publication Critical patent/CN1773699A/zh
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Abstract

本发明提供一种半导体封装及其制造方法，其特征在于减小同时开关噪声的环形硅退耦电容器。该退耦电容器利用晶片制造工艺由硅制造在基板上且采用环形电容结构的形式，该环形电容结构围绕基板上安装的集成电路(IC)的周边延伸。该退耦电容器具有芯片级或低于芯片级的减小的厚度且代替传统电源/接地环。因此，该退耦电容器能够设置在封装内而不增加该封装的厚度和尺寸。该退耦电容器可连接到各种电源引脚，允许优化的导线键合、缩短的电连接、及减小的电感。连接到退耦电容器的键合导线具有较高的电阻率，降低了共振频率的峰且因此减小了同时开关噪声。

Description

具有环形硅退耦电容器的集成电路 芯片封装及其制造方法
技术领域
本发明总体涉及半导体封装技术，更特别地，涉及具有设置在其中以减小同时开关噪声(simultaneous switching noise，SSN)的退耦电容器(decoupling capacitor)的集成电路芯片封装及其制造方法。
背景技术
集成电路(IC)技术的快速和不断进展已经给互连封装设计带来了很多新的挑战。集成在单个芯片上的器件的数量显著增长，同时器件变得对电源/地噪声(power-ground noise)更加敏感。
当多个输出驱动器同时开关时，它们在芯片/封装电源分配中诱发电压降。同时开关使器件内的接地电压相对于系统接地瞬间升高。该接地电势到非零值的偏移称为同时开关噪声。同时开关噪声能导致逻辑电路错误地转换状态，而信号/电源完整性问题对高速系统的性能有显著影响。同时开关还能导致信号时序和品质方面的问题，例如上升时间中信号的衰减、信号通道传输延迟变形、以及信号过冲的增大。
退耦电容器的使用是减小不良同时开关噪声的影响的一种公知技术。通常，退耦电容器以分立元件的形式安装在母板上，同时与(IC)芯片封装分隔开。然而，在高速、高频系统中，退耦电容器设置在IC芯片封装内从而减小由较长连接路径引起的寄生参数，由此改善电性能。
图1在平面图中示出传统IC芯片封装10的内部结构，其中设置有退耦电容器13。图2是沿图1的II-II线截取的横截面图。
参照图1和2，封装10具有并排附着在电路基板11上的IC芯片12和退耦电容器13。退耦电容器13经键合导线(bonding wire)14电连接到IC芯片12且电连接到电路基板11。电源/接地环(power/ground ring)15形成在电路基板11上，围绕IC芯片12。电源/接地环15用于电连接或合并多个电源/接地引脚(pin)。尽管通常形成其它键合导线来在IC芯片12和电路基板11之间直接连接信号引脚，但是为了说明清楚，图中没有绘出。
通常，传统封装10可使用块电容器(bulk capacitor)，例如宽、长和高分别为约1mm、1mm和2mm的退耦电容器13。这样，块电容器13在封装10中占用过多的内部空间，导致封装10的尺寸的增加，尤其是其厚度或高度。另外，传统退耦电容器13连接到单一类型的电源引脚，因此根据电源引脚的类型需要数个电容器13。此外，电容器13在基板上的安装位置根据IC芯片12的电源/接地引脚的位置而受到限制。
如上所述，传统退耦电容器13使用键合导线14用于到IC芯片12和电路基板11两者的电连接，由此需要双导线键合。另外，电容器13通常在高度上大于IC芯片12，因此连接到电容器13的键合导线14在长度和不期望的电感上增加。另外，由金制成的键合导线14具有较大的共振峰，引起麻烦的同时开关噪声。
发明内容
本发明的示例性、非限制性实施例提供集成电路(IC)芯片封装，其具有利用晶片(wafer)制造工艺由硅制成的环形(ring-shaped)退耦电容器。
根据本发明的一示例性实施例，该封装包括具有上表面、下表面的电路基板和形成在该上表面上的多个键合指(bond finger)。该封装还包括设置在该电路基板的上表面上且具有多个第一输入/输出(I/O)端子和多个第二I/O端子的至少一个IC芯片。此外，该封装包括在该电路基板的上表面上沿围绕所述IC芯片的确定周边延伸的退耦电容器。该封装还包括：多个第一键合导线，其将所述IC芯片的所述第一I/O端子电连接到所述电路基板的所述键合指；以及多个第二键合导线，其将所述IC芯片的所述第二I/O端子电连接到所述退耦电容器。在该封装中，退耦电容器具有形成在其上的多个键合焊盘(bonding pad)和形成在其中的多个连接通路。所述键合焊盘连接到所述第二键合导线，所述连接通路将所述键合焊盘电连接到所述电路基板的所述上表面。
在该封装中，所述退耦电容器的所述键合焊盘通常具有至少一个电源焊盘和接地焊盘。另外，所述键合焊盘通常具有多个分开的电源焊盘和多个分开的接地焊盘，或者供选地，具有长的单个电源焊盘和长的单个接地焊盘。
在该封装中，所述第二I/O端子通常具有多个电源引脚和多个接地引脚。所述第二键合导线可以比所述第一键合导线具有相对更高的电阻率。所述第二键合导线可以由金和铝的合金制成。
所述退耦电容器通常具有环状形状且可以沿着所述IC芯片的周边连续延伸。供选地，所述退耦电容器可具有环状配置且可分成数个单元或者直线或曲线的段，沿着围绕IC芯片的确定周边仅部分延伸。
所述退耦电容器的厚度通常小于或等于所述IC芯片的厚度。所述退耦电容器可通过利用晶片制造工艺由硅制成。所述退耦电容器可具有两个或更多个多晶硅层以及置于所述多晶硅层之间的一个或更多氧化物-氮化物-氧化物层。
另外，所述IC芯片可包括以堆叠设置的两个或更多单独IC芯片。所述封装还能包括形成在所述电路基板的所述下表面上的多个导电球。
根据本发明的另一示例性实施例，该封装包括：电路基板，其具有上表面、下表面、以及形成在所述上表面上的多个键合指；至少一个IC芯片，其设置在所述电路基板的所述上表面上且具有多个第一输入/输出(I/O)端子和多个第二I/O端子；以及退耦电容器，其具有形成在其上的多个键合焊盘且在所述电路基板的所述上表面上沿着围绕所述IC芯片的确定周边延伸。该封装还包括：多个第一键合导线，其将所述IC芯片的所述第一I/O端子电连接到所述电路基板的所述键合指；以及多个第二键合导线，其将所述IC芯片的所述第二I/O端子电连接到所述退耦电容器的所述键合焊盘。在该封装中，所述IC芯片的所述第二I/O端子具有多个电源引脚和多个接地引脚，所述退耦电容器的所述键合焊盘具有至少一个电源焊盘和接地焊盘。
该封装中，所述退耦电容器还可具有形成在其中的多个连接通路，所述连接通路将所述键合焊盘电连接到所述电路基板的所述上表面。所述第二键合导线比所述第一键合导线可具有相对更高的电阻率。另外，所述第二键合导线可由金和铝的合金制成。
所述退耦电容器可具有环状形状且可沿着所述IC芯片的周边连续延伸。供选地，所述退耦电容器可具有环状配置且可分成或分割成沿围绕IC芯片的所述确定周边延伸的数个单元。
所述退耦电容器的厚度可小于或等于所述IC芯片的厚度。所述退耦电容器可通过利用晶片制造工艺由硅制成。所述退耦电容器可具有两个或更多多晶硅层以及置于所述多晶硅层之间的一个或更多氧化物-氮化物-氧化物层。所述IC芯片可包括以堆叠设置的两个或更多单独IC芯片。该封装还可包括形成在所述电路基板的所述下表面上的多个导电球。
附图说明
图1是示出传统IC芯片封装的内部结构的平面图；
图2是沿图1的II-II线截取的横截面图；
图3是示出具有根据本发明一示例性实施例的环形硅退耦电容器的IC芯片封装的横截面图；
图4是示出图3所示的封装中退耦电容器的配置的平面图；
图5是示出图3所示的封装的导线键合方案的平面图；
图6是与图3对应的放大局部视图；
图7是示出根据本发明一示例性实施例的硅退耦电容器的分层结构的横截面图；
图8是示出使用根据本发明一示例性实施例的硅退耦电容器的模拟结果的曲线图；
图9是示出根据本发明另一示例性实施例的环形硅退耦电容器的平面图；
图10A和10B是示出图9所示的退耦电容器上的键合焊盘的两个示例的平面图；
图11是示出具有根据本发明再一示例性实施例的退耦电容器的IC芯片封装的局部横截面图。
具体实施方式
现在将参照附图更全面地描述本发明的示例性、非限制性实施例。然而，本发明能够以很多不同方式实施，而不应该解释为局限于这里提出的示例性实施例。相反，提供公开实施例是为了使本公开更彻底和全面，并向本领域的技术人员充分传达本发明的范围。本发明的原理和特征可应用于不同且众多的实施例而不偏离本发明的范围。
注意，为了避免模糊本发明的实质，公知的结构和工艺将不予详细描述或说明。还要注意，图没有按比例绘制。相反，为了说明的简洁和清楚，一些元件的尺寸相对于其它元件被放大。相同的附图标记用于各附图的相同和对应的部件。
图3在横截面图中示出具有根据本发明一示例性实施例的环形硅退耦电容器30的IC芯片封装20。
参照图3，封装20具有IC芯片22和退耦电容器30，两者都设置在电路基板21的上表面21a上。封装还具有设置在电路基板21的下表面21b上的多个导电球23。IC芯片22经第一键合导线24a电连接到电路基板21且通过第二键合导线24b电连接到退耦电容器30。IC芯片22、退耦电容器30、以及第一和第二键合导线24a和24b封装在成型树脂(molding resin)25内。
图4在平面图中示出图3所示的封装中退耦电容器30的配置。如图4所示，退耦电容器30具有环状形状，沿围绕IC芯片22的确定周边连续延伸。即，退耦电容器30设置在与传统电源/接地环通常形成的位置基本相同的位置。另外，退耦电容器30起上述传统电源/接地环的作用，如稍后将描述的。因此，尽管设置在封装内，退耦电容器30不增加封装的尺寸。将意识到，为了说明的简洁和清楚，图4没有示出形成在电路基板21的上表面21a上的包括键合指的电路图案。
将意识到，在本发明的精神和范围内，退耦电容器30可以围绕IC芯片22的确定周边仅部分地延伸，如下面参照图9所论述的。
IC芯片22具有多个输入/输出(I/O)端子26，也称为I/O焊盘或键合焊盘。I/O端子26根据其功能大致分为信号引脚、电源引脚和接地引脚。电源引脚包括AC电源引脚和DC电源引脚，且AC引脚可以负载各种AC电压。I/O端子还根据其功能具有不同的导线键合方案(wire-bonding scheme)。
图5在平面图中示出图3所示的封装的导线键合方案。参照图5，起AC电源引脚作用的第一I/O端子26a通过第二键合导线24b连接到退耦电容器30。类似地，起接地引脚作用的第二I/O端子26b通过第二键合导线24b连接到退耦电容器30。起信号引脚作用的第三I/O端子26c和起DC电源引脚作用的第四I/O端子26d通过第一键合导线24a分别连接到电路基板21上的键合指27。
第一键合导线24a可由金(Au)制成，第二键合导线24b可由金(Au)和具有相对较高电阻率的其它金属例如铝(Al)的合金制成。例如，金和铝可以按照1比1的比例混合。第二键合导线24b的较高的电阻率有助于降低共振频率的峰，因此减小同时开关噪声。
IC芯片22上的I/O端子26可以如图4所示地布置成一行，或供选地如图5所示地布置成两行。但是，这些布置仅仅是示例性的而不应被作为本发明的示例性实施例的限制。
退耦电容器30通过利用公知的晶片制造工艺由硅(Si)制成。这使得不仅可以在退耦电容器30上形成用于各种AC电源引脚的各种键合焊盘，而且可以在芯片层次上低退耦电容器30的厚度。
图6是与图3对应的放大局部视图。如图6所示，退耦电容器30位于非常接近IC芯片22，因为它代替了传统电源/接地环。此外，退耦电容器30与传统块电容器相比具有芯片级或低于芯片级的减小的厚度。因此，退耦电容器30上的键合焊盘31变得非常接近于IC芯片22上的I/O端子26，从而第二键合导线24b的长度可以显著缩短。
另外，晶片制造工艺可以在退耦电容器30内形成一个或更多连接通路，例如通路32。连接通路32提供退耦电容器30的顶部和底部之间的直接电路径。采用连接通路32，退耦电容器30不需要传统的双导线键合。因此，穿过退耦电容器30的整个电路径显著缩短，且相关电感有利地减小。连接通路32可以例如通过焊料33电连接到(直接或间接地)电路基板21的上表面21a。
如上面论述的，退耦电容器30可以通过利用晶片制造工艺由硅(Si)制成。图7在横截面图中示出硅退耦电容器30的分层结构。但是，图7的分层结构仅以示例的方式给出，而不是作为本发明的限制。
参照图7，第一氧化物层42形成在硅基板41上之后，第一多晶硅层43a沉积在其上。接着，顺序沉积第二氧化物层44a、氮化物层44b和第三氧化物层44c，且然后第二多晶硅层43b沉积在其上。两个多晶硅层43a和43b充当导电层，而设置的氧化物-氮化物-氧化物层44a、44b和44c充当电介质层。即，产生电容器结构。在该结构中，第一多晶硅层43a可以用作接地平面(ground plane)(Vss)，第二多晶硅层43b可以用作电源平面(power plane)(Vdd)。
然后第二多晶硅层43b被构图从而形成数个电容器区(capacitorblock)。接着，涂敷第一层间电介质层45a。顺序选择性蚀刻第一层间电介质层45a、第三氧化物层44c、氮化物层44b和第二氧化物层44a，从而形成分别与第一和第二多晶硅层43a和43b连接的接触46a和46b。
其后，第一金属层47a和47b沉积在第一层间电介质层45a上且被构图从而与各自的接触46a和46b连接。然后第二层间电介质层45b涂敷于其上且被选择性蚀刻从而形成通路48。接着，第二金属层49沉积于其上从而与通路48连接。接着，钝化层(未示出)涂覆于其上且被选择性蚀刻从而定义前述键合焊盘(图6中的31)。这样上面论述的图6中的连接通路32可以形成在图7的分层结构中，在第一金属层47a、47b和/或第二金属层49下。
图8是示出利用根据本发明一示例性实施例和传统技术的模拟结果的曲线图。图8的曲线图表示相对于频率(水平轴)的电源传输网络阻抗(powerdelivery network impedance)(垂直轴)。本领域技术人员将理解，阻抗可以在电源/接地端子测量且所得阻抗曲线实际上表示电源传输效率的倒数，即阻抗越低，电源传输效率越高。
现有技术的模拟使用电源/接地环(图1所示的15)而没有使用块退耦电容器(图1所示的13)。本发明的模拟使用环状硅退耦电容器(图4所示的30)和含有铝的第二键合导线(图4所示的24b)。虽然传统电源/接地环具有约1500μm的总体宽度，但本发明的硅退耦电容器具有约1000μm的宽度和约30nF的电容。如图8中代表本发明模拟的粗线所示，在超过约100MHz的频率共振峰显著降低。当然，该高频范围是高速、高频开关电路制造、封装和安装中感兴趣的范围。
图9在平面图中示出根据本发明另一示例性实施例的环状硅退耦电容器30。
参照图9，该实施例中的退耦电容器30具有环状构造且利用晶片制造工艺制成。与前面的实施例相反，本实施例中的退耦电容器30被分成布置为沿IC芯片22的周边(或围绕芯片22的确定外围)部分地(且根据本发明的优选实施例，基本连续但不完全连续地)延伸的数个单元或段。
图10A和10B在平面图中分别示出图9所示的退耦电容器30上的键合焊盘31的两个示例。如上所论述的，退耦电容器30的键合焊盘31电连接到IC芯片的AC电源引脚和接地引脚。图10A和10B所示的键合焊盘31的示例仅仅是示例性的而不应被看作本发明的限制。
参照图10A，退耦电容器30的键合焊盘具有多个第一AC电源焊盘31a、多个第二AC电源焊盘31b、以及多个接地焊盘31c。第一和第二AC电源焊盘31a和31b电连接到IC芯片的不同电压AC引脚。当IC芯片具有大量的电源/接地引脚时可以利用分开的键合焊盘这样的配置。即，IC芯片的各个引脚可以导线键合到最近的键合焊盘，因此允许优化的导线键合，例如具有最小实际特征电感的最短实际键合导线路径。
参照图10B，退耦电容器30的键合焊盘具有细长的单个第一AC电源焊盘31a、细长的单个第二AC焊盘31b、以及细长的单个接地焊盘31c。结合的键合焊盘这样的配置可用于代替电源/接地环。
本发明的硅退耦电容器可有助于用于封装内系统(SIP)。下面的图11示出这样的相关例子。图11是示出具有根据本发明再一示例性实施例的退耦电容器30的IC芯片封装20的局部横截面图。
参照图11，封装20具有堆叠设置在电路基板21上的数个IC芯片22a、22b和22c。IC芯片22a、22b和22c可以是存储芯片和/或逻辑芯片。粘合材料28置于最下面的IC芯片22a与电路基板21之间以及相邻的IC芯片22a、22b、以及22c之间。大量导电球23例如焊料球形成在电路基板21下面。
硅退耦电容器30位于电路基板21上芯片堆叠附近。如上面论述的，退耦电容器30具有环状形状或环状配置，无论连续或分段。各IC芯片22a、22b和22c的电源/接地引脚通过具有较高电阻率的第二键合导线24b电连接到退耦电容器30。
如上文全面论述的，可以采用根据本发明实施例的退耦电容器而与封装的类型无关。此外，该退耦电容器可以利用晶片制造工艺由硅制成。因为该硅退耦电容器可以具有芯片级或低于芯片级的减小的厚度，所以封装的厚度不会由于退耦电容器而增加。另外，由于该硅退耦电容器可以代替传统的电源/接地环，所以该退耦电容器可以包括在封装内而不增加封装的尺寸。
另外，该退耦电容器不仅提供与各种电源引脚的有效连接，还允许根据IC芯片的电源/接地引脚的位置的各个优化的导线键合连接。因此该退耦电容器还允许缩短的电连接，例如导线键合路径，以及因此减小的电感。
此外，该退耦电容器和AC电源引脚可以通过具有更高电阻率的第二键合导线连接，这降低了共振频率的峰，且因此减小了麻烦的同时开关噪声。
尽管参考本发明的示例性实施例特别显示和描述了本发明，但是本领域技术人员应理解，在不偏离所附权利要求所定义的本发明的精神和范围的情况下，可以进行各种形式和细节上的改变。
本申请要求2004年11月9日向韩国知识产权局提交的韩国专利申请No.2004-90669的优先权，在此引用其全部内容作为参考。

Claims (31)

1.一种集成电路(IC)芯片封装，包括：
电路基板，其包括上表面、下表面、以及形成在所述上表面上的多个键合指；
至少一个IC芯片，其设置在所述电路基板的所述上表面上且包括多个第一输入/输出(I/O)端子和多个第二I/O端子；
退耦电容器，其在所述电路基板的所述上表面上沿围绕所述IC芯片的确定周边至少部分地延伸；
多个第一键合导线，其将所述IC芯片的所述第一I/O端子电连接到所述电路基板的所述键合指；以及
多个第二键合导线，其将所述IC芯片的所述第二I/O端子电连接到所述退耦电容器，
其中所述退耦电容器包括形成在其上的多个键合焊盘和形成在其中的多个连接通路，其中所述键合焊盘连接到所述第二键合导线，且其中所述连接通路将所述键合焊盘电连接到所述电路基板的所述上表面。
2.如权利要求1所述的封装，其中所述退耦电容器的所述键合焊盘包括至少一个电源焊盘和接地焊盘。
3.如权利要求2所述的封装，其中所述键合焊盘包括多个分开的电源焊盘和多个分开的接地焊盘。
4.如权利要求2所述的封装，其中所述键合焊盘包括细长的单个电源焊盘和细长的单个接地焊盘。
5.如权利要求1所述的封装，其中所述第二I/O端子包括多个电源引脚和多个接地引脚。
6.如权利要求1所述的封装，其中所述第二键合导线比所述第一键合导线包括相对更高的电阻率。
7.如权利要求6所述的封装，其中所述第二键合导线由含有金和铝的合金的材料制成。
8.如权利要求1所述的封装，其中所述退耦电容器包括环状形状且沿着所述确定周边连续延伸。
9.如权利要求1所述的封装，其中所述退耦电容器包括环状配置且分成两个或更多沿着所述确定周边布置的段。
10.如权利要求1所述的封装，其中所述退耦电容器的厚度不大于所述IC芯片的厚度。
11.如权利要求1所述的封装，其中所述退耦电容器通过利用晶片制造工艺由硅制成。
12.如权利要求1所述的封装，其中所述退耦电容器包括两个或更多多晶硅层以及置于所述两个或更多多晶硅层的相邻层之间的一个或更多氧化物-氮化物-氧化物层。
13.如权利要求1所述的封装，其中所述IC芯片包括堆叠设置的两个或更多单独的IC芯片。
14.如权利要求1所述的封装，还包括：
形成在所述电路基板的所述下表面上的多个导电球。
15.一种集成电路(IC)芯片封装，包括：
电路基板，其包括上表面、下表面、以及形成在所述上表面上的多个键合指；
至少一个IC芯片，其设置在所述电路基板的所述上表面上且包括多个第一输入/输出(I/O)端子和多个第二I/O端子；
退耦电容器，其包括形成在其上的多个键合焊盘且在所述电路基板的所述上表面上沿围绕所述IC芯片的确定周边至少部分延伸；
多个第一键合导线，其将所述IC芯片的所述第一I/O端子电连接到所述电路基板的所述键合指；以及
多个第二键合导线，其将所述IC芯片的所述第二I/O端子电连接到所述退耦电容器的所述键合焊盘，
其中所述IC芯片的所述第二I/O端子包括多个电源引脚和多个接地引脚，且其中所述退耦电容器的所述键合焊盘包括至少一个电源焊盘和接地焊盘。
16.如权利要求15所述的封装，其中所述退耦电容器还包括形成在其中的多个连接通路，所述连接通路将所述键合焊盘电连接到所述电路基板的所述上表面。
17.如权利要求15所述的封装，其中所述第二键合导线比所述第一键合导线包括相对更高的电阻率。
18.如权利要求17所述的封装，其中所述第二键合导线由含有金和铝的合金的材料制成。
19.如权利要求15所述的封装，其中所述退耦电容器包括沿所述确定周边连续延伸的环状形状。
20.如权利要求15所述的封装，其中所述退耦电容器包括环状配置且分成两个或更多沿所述确定周边布置的段。
21.如权利要求15所述的封装，其中所述退耦电容器的厚度不大于所述IC芯片的厚度。
22.如权利要求15所述的封装，其中所述退耦电容器通过利用晶片制造工艺由硅制成。
23.如权利要求15所述的封装，其中所述退耦电容器包括两个或更多多晶硅层以及置于所述两个或更多多晶硅层的相邻层之间的一个或更多氧化物-氮化物-氧化物层。
24.如权利要求15所述的封装，其中所述IC芯片包括堆叠设置的至少两个单独的IC芯片。
25.如权利要求15所述的封装，还包括：
形成在所述电路基板的所述下表面上的多个导电球。
26.一种半导体封装，包括：
基板；
集成电路，其安装在所述基板上，所述集成电路包括一个或更多接地/电源导线键合焊盘；
环形结构，其整体地形成在所述基板上且基本围绕所述集成电路的周边延伸，所述环形结构具有能够将所述集成电路从所述基板内的一个或更多接地/电源端子连接退耦的特征电容，所述环形结构还包括一个或更多键合导线焊盘从而定义一集成的环形退耦电容器；以及
一个或更多键合导线，其将所述集成电路的该一个或更多接地/电源导线键合焊盘与所述环形结构的所述一个或更多键合导线焊盘的对应的键合导线焊盘电连接，
由此所述集成电路的所述一个或更多接地/电源端子通过由所述环形结构定义的所述集成环形退耦电容器间接地电连接到所述基板内的一个或更多接地/电源端子连接。
27.一种用于制造半导体封装的方法，该方法包括：
准备电路基板，该电路基板包括上表面，该上表面包括形成在其上的多个键合指；
将集成电路(IC)芯片安装在所述电路基板的所述上表面上，所述IC芯片包括一个或更多接地/电源导线键合焊盘；
在所述电路基板上制造整体环形结构，该整体环形结构基本围绕所述IC芯片的周边延伸，该环形结构具有配置来将所述IC芯片从所述基板内一个或更多接地/电源端子连接退耦的特征电容，所述环形结构还包括一个或更多键合导线焊盘从而定义集成环形退耦电容器；以及
附贴一个或更多键合导线从而将所述IC芯片的所述一个或更多接地/电源导线键合焊盘与相应的所述环形结构的一个或更多键合导线焊盘电连接，所述附贴以这样的方式进行，即所述IC芯片的所述一个或更多接地/电源端子通过由所述环形结构定义的所述集成环形退耦电容器间接电连接到所述基板内所述一个或更多接地/电源端子连接。
28.如权利要求27所述的方法，其中所述安装是两个或更多堆叠的集成电路(IC)芯片的安装。
29.如权利要求27所述的方法，其中所述制造包括堆叠两个或更多多晶硅层以及置于所述两个或更多多晶硅层的相邻层之间的一个或更多氧化物-氮化物-氧化物层。
30.如权利要求27所述的方法，还包括：
安装多个导电球在所述电路基板的与所述上表面相对的下表面上。
31.如权利要求27所述的方法，其中所述IC芯片还包括一个或更多信号导线键合焊盘，该方法还包括：
附贴一个或更多第二键合导线从而将所述一个或更多信号导线键合焊盘电连接到所述电路基板的所述一个或更多键合指。
CNA2005101203004A 2004-11-09 2005-11-09 具有环形硅退耦电容器的集成电路芯片封装及其制造方法 Pending CN1773699A (zh)

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