CN101312176A - 半导体器件、引线框以及半导体器件的安装结构 - Google Patents

半导体器件、引线框以及半导体器件的安装结构 Download PDF

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Publication number
CN101312176A
CN101312176A CNA200810109145XA CN200810109145A CN101312176A CN 101312176 A CN101312176 A CN 101312176A CN A200810109145X A CNA200810109145X A CN A200810109145XA CN 200810109145 A CN200810109145 A CN 200810109145A CN 101312176 A CN101312176 A CN 101312176A
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lead
wire
semiconductor device
tube core
wires
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百合野孝弘
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Fujitsu Semiconductor Ltd
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Fujitsu Ltd
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Abstract

本发明提供一种半导体器件结构，其中，围绕半导体元件设置的多个引线之间的间隔可以变窄，从而增加引线的数量，并且防止或减小引线之间的电干扰，从而在引线之间不产生串音干扰。本发明的半导体器件包括：半导体元件以及围绕该半导体元件设置的多个引线。所述多个引线包括多个第一引线和多个第二引线。所述多个第一引线通过多个连接构件连接至该半导体元件的多个电极端子。所述多个第二引线设置在所述多个第一引线之间，且未连接至该半导体元件的电极端子。

Description

半导体器件、引线框以及半导体器件的安装结构
相关申请的交叉引用
本申请基于并要求2007年5月25日提交的在先日本专利申请No.2007-138984的优先权，其全部内容通过参考在此合并。
技术领域
本发明涉及一种半导体器件、引线框以及半导体器件的安装结构，更特别地，涉及一种半导体器件、引线框以及半导体器件的安装结构，其使内引线设置间距减小，从而增加引脚的数量。
背景技术
随着电子设备的性能在尺寸减小方面的改进，需要快速和高性能半导体器件(例如，安装在电子设备中的半导体集成电路器件)的尺寸和重量进一步减小。
例如，即使在树脂封装半导体装置(其为半导体装置的一种类型)中，外部接线端子(引线)也需要以更高的密度设置。
为了满足需要，外部接线端子(引线)围绕树脂封装半导体器件中的管芯台(die stage)以更高的密度设置，该管芯台支撑半导体元件(半导体芯片)。
参考图8A和图8B，其描述了作为传统半导体器件的实例的半导体器件600。
图8A示出了半导体器件600的引线框以及安装在引线框上的半导体元件的设置。图8B示出了图8A的放大的主要部分。
在半导体器件600中，半导体元件60安装并附着至引线框70的矩形管芯台72上，且管芯台72的四个角由管芯台杆71支撑。半导体元件60的电极端子通过接合线80连接至引线框70的引线73。
多个引线73围绕管芯台72设置在大致同一个平面上。通过系杆(连杆)74，每一个引线73具有称为内引线73A和外引线73B的部分。内引线73A比位于外侧上的外引线73B更靠近管芯台72(内侧)。
这种类型的半导体器件可以被称为四方扁平封装(QFP)半导体器件，其中多个引线73沿矩形管芯台72的四个边设置。
多个引线73中的每一个内引线73A通过接合线80连接至半导体元件60的电极端子(例如，信号输入/输出端子、电源端子或接地端子)。
在半导体器件600中，引线73的内引线73A之间的间隙较窄，以使引线73在半导体元件60附近以高密度(间距)设置。这增加了设置的引线73的数量。从而，可以提高半导体器件600的性能。
但是，引线73之间的窄间隙会导致引线形成困难，并且在半导体器件运行时在引线73之间产生干扰。这将产生串音干扰。
为了克服这一问题，管芯台杆(支撑杆)通常被用作接地(地)线、电源线和/或其它的公共端子，且围绕半导体元件平行延伸(例如，参考国际公布WO98/31051和03/105226)。
因而，可以减少引线的数量并以适当密度设置引线。
但是，在这种情况下，延伸的管芯台杆(支撑杆)不能支撑管芯台。因而，需要其它支撑构件来支撑半导体元件。
同时，日本专利公报(JP-A)No.11-40721公开了一种结构，其中在多个信号引线的顶端之间设置降噪金属片，并将降噪金属片嵌入到封装的树脂中。
降噪金属片的构件不同于引线的构件，且金属片通过连接导体或连接金属线连接至管芯焊盘(管芯台)。
因而，半导体器件制造变得复杂，且信号线不能被充分屏蔽。
另外，JP-A No.2006-19767公开一种高脚数四方无引脚扁平(QFN)封装的半导体器件制造，其中具有不同长度的引线围绕管芯焊盘(管芯台)交替地(两个交错列)设置，从而设置大量引线，且改变了线环(wire loop)的高度，以用于连接。
在该半导体器件中，与图8所示的传统器件中一样，引线之间产生电干扰，但没有对抗该电干扰的反措施。
发明内容
本发明克服了传统半导体器件的问题并达到了下述目的。
本发明的一个目的在于提供一种半导体器件结构，其中可以减小围绕半导体元件设置的多个引线之间的间隙，以增加引线的数量，且防止或减少了多个引线之间的电干扰，以使引线之间不产生串音干扰。
本发明的另一个目的在于提供一种适用于该半导体器件结构的引线框结构。
本发明的又一个目的在于提供一种对于半导体器件的特殊结构也能发挥作用的安装结构。
根据实施例的一个方案，半导体器件包括：半导体元件；以及多个引线，围绕该半导体元件设置；其中，所述多个引线包括多个第一引线和多个第二引线；所述多个第一引线通过多个连接构件连接至该半导体元件的多个电极端子；并且所述多个第二引线设置在所述多个第一引线之间，且未连接至该半导体元件的电极端子。
根据实施例的另一个方案，引线框包括：管芯台，其上安装有半导体元件；以及多个引线，围绕该管芯台设置；其中，所述多个引线包括多个第一引线和多个第二引线；所述多个第一引线通过多个连接构件连接至安装在该管芯台上的该半导体元件的多个电极端子；并且所述多个第二引线设置在所述多个第一引线之间，且比所述多个第一引线的顶端距离该管芯台更远，且所述多个第二引线未连接至该半导体元件的电极端子。
根据本发明，可以克服传统半导体器件的问题，使连接至半导体元件的电极端子的引线顶端之间的间距变窄，且减少引线之间的串音干扰。因而，可以提高半导体器件的性能特性。
附图说明
图1A是示出本发明的第一实例(实例1)中的半导体器件结构在树脂封装之前的平面图。
图1B是图1A的放大局部图。
图2是示出图1A和图1B所示的第一实例(实例1)中的半导体器件结构的外部立体图。
图3A是示出本发明的第二实例(实例2)中的半导体器件结构在树脂封装之前的平面图。
图3B是图3A的放大局部图。
图4A是示出本发明的第三实例(实例3)中的半导体器件结构在树脂封装之前的平面图。
图4B是图4A的放大局部图。
图5A是示出本发明的第四实例(实例4)中的半导体器件结构在树脂封装之前的平面图。
图5B是图5A的放大局部图。
图6是示出根据本发明的半导体器件安装在支撑基板上的外部立体图。
图7是示出图6所示的支撑基板中的导电图案的放大局部平面图。
图8A是示出传统半导体器件结构在树脂封装之前的平面图。
图8B是图8A的放大局部图。
具体实施方式
通过实例详述根据本发明的半导体器件以及该半导体器件的安装结构。然而，本发明的范围和构思不限于这些实例。
(实例1)
参考图1A、图1B和图2描述根据本发明的半导体器件的第一实例--半导体器件100。
图1A示出了半导体器件100的引线框以及安装在该引线框上的半导体元件的设置。图1B示出了图1A的放大的主要部分。
在本实例中，半导体元件10安装并附着至引线框20的矩形管芯台22，且管芯台杆21支撑管芯台22的四个角。半导体元件10的电极端子通过接合线31连接至引线框20的引线23，且可选择地连接至管芯台22。
多个引线23(第一引线)围绕管芯台22设置在大致同一个平面上。通过系杆(连杆)24，每一个引线23具有被称为内引线23A和外引线23B的部分。内引线23A比位于外侧上的外引线23B更靠近管芯台22(内侧)。
如图所示，这种类型的半导体可以被称为四方扁平封装(QFP)半导体器件，其中多个引线23沿矩形管芯台22的四个边设置。
多个引线23的每个内引线23A通过接合线31连接至半导体元件10的电极端子(例如信号输入/输出端子、电源端子或接地端子)。
在此，在引线23之间设置长度与引线23相同的引线23S(内引线23SA)，且内引线23SA的顶端通过接合线33连接至管芯台22。
内引线23A和内引线23SA的接合区域表面选择性地镀银(Ag)，以使接合线31和33可以分别连接至内引线23A和23SA。
本实例中半导体器件100的区别特征在于：在围绕管芯台22设置在大致同一个平面上的多个引线23(第一引线)之间选择性地设置引线25(第二引线)；且引线25没有通过接合线31连接至半导体元件10的电极端子。
通过系杆(连杆)24，每一个引线25还具有被称为内引线和外引线的部分。内引线比位于外侧上的外引线更靠近管芯台22(内侧)。
引线25的内引线25A比引线23的内引线23A短。
因而，引线23没有以低密度(间距)设置在管芯台22附近，即，半导体元件10的附近。
由于引线25没有通过接合线31连接至半导体元件10的电极端子，因而引线25的表面没有镀银(Ag)。
附着并支撑在引线框20的管芯台22上的半导体元件10、接合线31、引线23和引线25的内引线通过公知的树脂模制由树脂封装。
引线框20由铜(Cu)合金或42合金(镍(Ni)含量42％的铁(Fe)镍(Ni)合金)制成。
接合线31的、连接至引线框20的引线23的部分预先镀银(Ag)。
按照以下步骤制造半导体元件10：对半导体基底(例如由硅(Si)或砷化镓(GaAs)制成)的多个主表面进行晶片处理；以及形成有源区(电路形成区)。有源区包括有源元件(例如晶体管)、无源元件(例如电容元件)以及连接这些功能元件的互连层。连接至互连层的电极端子设置在半导体基体的一个主表面上。
接合线31是含有金(Au)、铜(Cu)和铝(Al)或这些材料中的任一种的薄合金线。
而且，使用环氧树脂进行封装。
在树脂封装之后，引线的外引线和管芯台杆21从引线框20切断，去除引线之间的系杆(连杆)24，且使引线成形。因而，形成如图2所示的半导体器件100。
注意，在图2中部分去除封装树脂40，以示出半导体器件100中的引线23和25等的设置。
特别地，图2示出了引线23和25的上表面从管芯台22上安装有半导体元件10的同一侧露出。
如图2所示，引线25未连接至半导体器件100中的半导体元件10的电极端子。引线25可以独立地连接至外部电极端子。
因而，当半导体器件100安装在插入电子设备等中的互连板时，可以通过插座(socket)或互连板的电极端子为引线25提供参考电势(例如，接地电势)。
特别地，当参考电势(例如，接地电势)施加至具有这种结构的半导体器件100中的引线25时，可以电屏蔽引线25两侧的引线23。因而，可以防止或减小引线23之间的串音干扰。
如前所述，本实例中使用的引线框20包括管芯台22和多个引线。半导体元件10安装在管芯台22上，且多个引线围绕管芯台22设置。多个引线由多个引线23(第一引线)和多个引线25(第二引线)构成。多个引线23通过多个连接构件(例如，接合线31)连接至安装在管芯台22上的半导体元件10的多个电极端子。引线25选择性地设置在多个引线23之间，且没有通过连接构件连接至半导体元件10的电极端子。
特别地，引线23和引线25在引线框20中同时形成。因而，通过引线框20，可以在不增加制造成本的情况下，采用传统的树脂封装半导体器件制造来有效地制造半导体器件100。
(实例2)
参考图3A和图3B描述根据本发明的半导体器件的第二实例——半导体器件200。
图3A示出了半导体器件200的引线框，以及安装在该引线框上的半导体元件的设置。图3B示出了图3A的放大的主要部分。
注意，使用相同的附图标记表示与图1A、图1B和图2中示出的半导体器件100的部件相对应的部件。
类似于第一实例，半导体元件10安装并附着至引线框20的矩形管芯台22，且管芯台杆21支撑管芯台22的四个角。半导体元件10的电极端子通过接合线31连接至引线框20的引线23，且可选择地连接至管芯台22。
多个引线23(第一引线)围绕管芯台22设置在大致同一个平面上。通过系杆(连杆)24，每一个引线23具有称为内引线23A和外引线23B的部分。内引线23A比位于外侧上的外引线23B更靠近管芯台22(内侧)。
多个引线23的每一个内引线23A通过接合线31连接至半导体元件10的电极端子(例如信号输入/输出端子、电源端子或接地端子)。
类似于第一实例，引线25(第二引线)选择性地设在设置于大致同一个平面上的多个引线23之间，且引线25未连接至半导体元件10的电极端子。
通过系杆(连杆)24，每一个引线25还包括称为内引线和外引线的部分。内引线比位于外侧上的外引线更靠近管芯台22(内侧)。
本实例中的半导体器件200的区别特征在于：与管芯台杆21相邻的引线26与管芯台杆21合并。
因而，在形成半导体器件之后，与引线25一样，当参考电势(例如，接地电视)施加至引线26时，管芯台杆25两侧的引线23被电屏蔽。因而，可以防止或减小引线23之间的串音干扰。
而且，由于设置了引线26，因而不需要设置第一实例的引线23S(内引线23SA)。从而，可以更容易地设置引线23。
(实例3)
参考图4A和图4B描述根据本发明的半导体器件的第三实例——半导体器件300。
图4A示出半导体器件300的引线框和安装在该引线框上的半导体元件的设置。图4B示出了图4A的放大的主要部分。
注意，使用相同的附图标记表示与图1A、图1B、图2、图3A和图3B中示出的半导体器件100或200的部件相对应的部件。
类似于第一和第二实例，半导体元件10安装并附着至引线框20的矩形管芯台22，且管芯台杆21支撑管芯台22的四个角。半导体元件10的电极端子通过接合线31连接至引线框20的引线23，且可选择地连接至管芯台22。
多个引线23(第一引线)围绕管芯台22设置在大致同一个平面上。通过系杆(连杆)24，每一个引线23具有称为内引线23A和外引线23B的部分。内引线23A比位于外侧上的外引线23B更靠近管芯台22(内侧)。
多个引线23的每一个内引线23A通过接合线31连接至半导体元件10的电极端子(例如信号输入/输出端子、电源端子或接地端子)。
类似于第一和第二实例，引线25(第二引线)选择性地设在设置于大致同一个平面上的多个引线23之间，且引线25未连接至半导体元件10的电极端子。
通过系杆(连杆)24，每一个引线25还包括称为内引线和外引线的部分。内引线比位于外侧上的外引线更靠近管芯台22(内侧)。
本实例中的半导体器件300的区别特征在于：连接构件、接合线35与选择性地设置在引线23之间的引线25互连。
特别地，引线25的内引线25A的、与半导体元件10相邻的顶端25AA连接至接合线35的一端。接合线35的另一端在相邻的引线23的上方连接至另一引线25的顶端25AA。
在本实例中，由于顶端25AA连接至接合线35，因而引线25的顶端25AA的表面镀银(Ag)。
接合线35与多个引线25的顶端25AA互连，以使引线25沿引线23以最大长度存在，且使引线25的屏蔽效果变得更强。
如果接合线35在更靠近外引线的部分而不是引线25的顶端25AA与引线25互连，则引线23的端部相对于半导体元件10是自由的。因而，引线25的屏蔽效果下降。
注意，除了引线25的顶端25AA以外的，可选择在引线25的其它部分(例如更靠近外引线的部分)上设置接合线35。即，可选择让引线25上的多个接合线35对准(图中未示出)。
在半导体元件10的多个电极端子通过接合线31连接至相应的引线23之前/之后，接合线35可以连接至引线25的顶端25AA。这些步骤可以在需要时交替执行。
注意，图4A和图4B示出了邻近管芯台杆21的引线26与管芯台杆21合并，如第二实例中所示。
除了引线25的互连以外，管芯台杆21两侧的引线23通过上述结构更有效地被电屏蔽。因而，可以防止或减小引线23之间的串音干扰。
而且，由于设置了引线26，因而不必设置第一实例的引线23S(内引线23SA)。因而，可以更容易地设置引线23。
(实例4)
参考图5A和图5B描述根据本发明的半导体器件的第四实例——半导体器件400。
图5A示出了半导体器件400的引线框和安装在该引线框上的半导体元件的设置。图5B示出了图5A的放大的主要部分。
注意，使用相同的附图标记表示与图1A、图1B、图2、图3A、图3B、图4A和图4B中示出的半导体器件100、200和300的部件相对应的部件。
类似于第一至第三实例，半导体元件10安装并附着至引线框20的矩形管芯台22，且管芯台杆21支撑管芯台22的四个角。半导体元件10的电极端子通过接合线31连接至引线框20的引线23，且可选择地连接至管芯台22。
多个引线23(第一引线)围绕管芯台22设置在大致同一个平面上。通过系杆(连杆)24，每一个引线23具有称为内引线23A和外引线23B的部分。内引线23A比位于外侧上的外引线23B更靠近管芯台22(内侧)。
多个引线23的每一个内引线23A通过接合线31连接至半导体元件10的电极端子(例如信号输入/输出端子、电源端子或接地端子)。
类似于第一到第三实例，引线25(第二引线)选择性地设在设置于大致同一个平面上的多个引线23之间，且引线25未连接至半导体元件10的电极端子。
通过系杆(连杆)24，每一个引线25还包括称为内引线和外引线的部分。内引线比位于外侧上的外引线更靠近管芯台22(内侧)。
本实例中的半导体器件400的区别特征在于：引线25选择性地设置在多个引线23之间并在多个引线23之间延伸，且引线25的顶端25AW和引线23的顶端23AA以大约相同的距离与管芯台22或半导体元件10相邻设置。
由于引线25未连接至连接线31，因而引线25的顶端25AW小于(窄于)引线23的顶端23AA。特别地，引线25的顶端25AW的宽度等于或小于引线23的顶端23AA的宽度的80％。
由于至少引线25的顶端25AW很小，因而没有显著减小引线23的顶端23AA的设置密度。
由于引线25设置在引线23的顶端附近且延伸至引线23的顶端附近，因而引线25沿着引线23的几乎全部长度存在，引线23位于引线25的两侧。因而，可以更有效地发挥引线25的屏蔽效果。
注意，图5A和图5B示出邻近管芯台杆21的引线26与管芯台杆21合并，如第二实例中所示。
除了延伸的引线25的设置以外，管芯台杆21两侧的引线23通过上述结构更有效地被电屏蔽。因而，可以防止或减小引线23之间的串音干扰。
而且，由于设置了引线26，因而不必设置第一实例的引线23S(内引线23SA)。因而，可以更容易地设置引线23。
(实例5)
在实例5中描述根据本发明的半导体器件的安装结构。
在此，使用第一实例的半导体器件100。该实例基于半导体器件100安置或安装在诸如电路板之类的支撑基板上的结构。照例，半导体器件200、300或400可以以与半导体器件100相同的方式安装。
图6示出了安装在诸如电路板之类的支撑基板50上的半导体器件100。
类似于图2，图6中半导体器件100的封装树脂40被部分移除。特别地，图6示出了引线23(第一引线)和引线25(第二引线)的上表面从管芯台22上安装有半导体元件10的同一侧露出。
半导体器件100通过将引线23的外引线23B和引线25的外引线25B连接并附着至支撑基板50的一个主表面上的相应端子51而安装在支撑基板50上。
支撑基板50是由有机绝缘树脂(例如玻璃环氧树脂、玻璃双马来酰亚胺三嗪(BT)或聚酰亚胺)或绝缘无机材料(例如陶瓷或玻璃)制成的绝缘基底。在支撑基板50的正面和/或背面上以及可选地在其内侧(内层)上设置导电层。
导电层主要由铜(Cu)构成。导电层的表面受到两层电镀，以使镍(Ni)和金(Au)层从下层按照这种顺序形成在表面上。
支撑基板50可以被称为互连板、电路板或内插板。
端子51连接至设置于支撑基板50的一个主表面(正面)、另一个主表面(背面)或支撑基板50内侧上的导电图案。
在半导体器件100安装在支撑基板50上之前，预焊接半导体器件100的外引线和支撑基板50的端子51。当外引线和端子51接触时，焊料再次熔化(重熔)，以使它们可以彼此连接。
在该安装结构中，连接至半导体器件100中的引线23和25的多个端子51选择性地连接至导电图案52S、导电图案52B、导电图案52G等。导电图案52S、52B和52G分别连接至信号电势、电源电势和地电势。
特别地，连接至半导体器件100中的信号输入/输出端子的引线23连接至导电图案52S。连接至半导体器件100中的电源端子的引线23连接至导电图案52B。连接至半导体器件100中的接地端子的引线23连接至导电图案52G。
同时，引线25连接至与地电势连接的导电图案52G。
如前所述，引线25连接至参考电势(例如地电势)，以使设置在引线25两侧的引线23可以被屏蔽。因而，可以提高半导体器件的性能特性。
由于现今对电子设备性能要求高，因而更多数量的半导体器件结合有多个功能电路。
在这种情况下，多个功能电路需要与信号电路分隔开，且可以需要不同的工作电压。
为了从外部施加不同的工作电压，多个功能电路通过不同的电路图案连接至支撑基板上的相应电源电路。
通过不同的导电图案将参考电势提供至不同的功能电路。
对于图6中示出的半导体器件100，不同的参考电势提供至多个结合的功能电路。
特别地，设置在引线23a至23d之间的引线25a至25c通常连接至第一导电图案52G1，且还通过第一导电图案52G1连接至第一参考电势。
而且，设置在引线23e至23g之间的引线25d至25e通常连接至设置于半导体器件100下方的导电图案52Gs，且还通过第二导电图案52G2连接至第二参考电势。
另外，设置在引线23h至23j之间的引线25f至25g通常连接至第三导电图案52G3，且还通过第三导电图案52G3连接至第三参考电势。
如上所述，引线25连接至参考电势(例如，地电势)，且设置在引线23之间，以使半导体器件100中的多个功能电路可以在引线之间不产生串音干扰的情况下，独立地执行它们自己必需的操作。
同时，在需要时，第一至第三参考电势可以在支撑基板50上互连。
注意，图6没有示出如图3所示的管芯台杆21通过引线26连接至参考电势等。但是，该结构可以可选择地使用。
图7示出了设置在支撑基板50上的导电图案52Gs以及导电图案52G2。
特别地，导电图案52Gs设置在半导体器件100下方的支撑基板50上，且与连接至引线25的端子51互连。例如，可以设置U形或C形导电图案52Gs。
导电图案52Gs不仅可以形成为在支撑基板50的表面上形成的导电层，还可以形成为内导电层。
在上述本发明的实施例中，一个半导体元件安装在引线框的管芯台上。但是，本发明的范围和构思不限于该结构。
本发明的范围和构思可以应用到多个半导体元件层叠在一个管芯台上，或者多个半导体元件设置和安装在大的管芯台或者多个连续设置的管芯台上。
通过应用根据本发明的半导体器件、引线框和半导体器件的安装结构，安装在电子设备中的树脂封装半导体器件可以获得更快更高的性能，且可以减小尺寸和重量。

Claims (10)

1.一种半导体器件，包括：
半导体元件；以及
多个引线，围绕该半导体元件设置，
其中，所述多个引线包括多个第一引线和多个第二引线；
所述多个第一引线通过多个连接构件连接至该半导体元件的多个电极端子；并且
所述多个第二引线设置在所述多个第一引线之间，且未连接至该半导体元件的多个电极端子。
2.根据权利要求1所述的半导体器件，其中，所述多个第一引线和所述多个第二引线由多个相同的构件形成。
3.根据权利要求1所述的半导体器件，其中，所述多个第二引线的顶端设置为比所述多个第一引线的顶端距离该半导体元件更远。
4.根据权利要求1所述的半导体器件，其中，所述多个第二引线的顶端通过设置在所述多个第一引线上方的多个连接构件互连。
5.根据权利要求1所述的半导体器件，
其中，所述多个第一引线的顶端位于该半导体元件附近，且所述多个第二引线的顶端位于该半导体元件附近；并且
所述多个第二引线的顶端比所述多个第一引线的顶端窄。
6.根据权利要求1所述的半导体器件，其中，所述多个第二引线连接至支撑管芯台的管芯台杆，该半导体元件安装在该管芯台上。
7.根据权利要求1所述的半导体器件，其中，施加至所述多个第二引线的电势为参考电势。
8.一种引线框，包括：
管芯台，其上安装有半导体元件；以及
多个引线，围绕该管芯台设置；
其中，所述多个引线包括多个第一引线和多个第二引线；
所述多个第一引线通过多个连接构件连接至安装在该管芯台上的该半导体元件的多个电极端子；并且
所述多个第二引线设置在所述多个第一引线之间，且比所述多个第一引线的顶端距离该管芯台更远，且所述多个第二引线未连接至该半导体元件的多个电极端子。
9.根据权利要求8所述的引线框，其中，支撑该管芯台的管芯台杆连接至所述多个第二引线。
10.一种引线框，包括：
管芯台，其上安装有半导体元件；以及
多个引线，围绕该管芯台设置；
其中，所述多个引线包括多个第一引线和多个第二引线；
所述多个第一引线的顶端位于该管芯台附近；且
所述多个第二引线的顶端位于该管芯台附近，且比所述多个第一引线的顶端窄。
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