CN107342276B - 半导体器件及相应方法 - Google Patents

半导体器件及相应方法 Download PDF

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CN107342276B
CN107342276B CN201611236433.2A CN201611236433A CN107342276B CN 107342276 B CN107342276 B CN 107342276B CN 201611236433 A CN201611236433 A CN 201611236433A CN 107342276 B CN107342276 B CN 107342276B
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die
die pad
semiconductor
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package
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CN107342276A (zh
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F·G·齐格利奥利
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STMicroelectronics SRL
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Abstract

各个实施例涉及半导体器件及相应方法。一种半导体器件包括：一个或多个半导体裸片；支撑一个或多个半导体裸片的裸片焊盘；模制到由所述裸片焊盘支撑的一个或多个半导体裸片上的封装件，其中裸片焊盘被暴露在封装件的表面处；以及暴露的裸片焊盘，其中具有蚀刻图案以在裸片焊盘中形成至少一个电接触焊垫。

Description

半导体器件及相应方法
技术领域
本描述涉及半导体器件。
背景技术
例如在半导体器件的所谓有机衬底封装件中可以提供嵌入式电容器。例如，电容器可以例如在平坦裸片焊盘区域上利用SMD焊接工艺，被嵌入在引线框架(LF)封装件中。
此外，裸片焊盘可以用于散热和/或为半导体裸片提供单个输入/输出焊盘。
尽管在该领域中有广泛的活动，仍然需要提供改进的封装价值和改进的器件性能两者的布置。
发明内容
一个或多个实施例可以应用于例如在引线框架中提供嵌入式电容器和/或例如为集成电路(IC)提供多功能裸片焊盘。
一个或多个实施例还可以涉及相应的方法。
权利要求是本文关于一个或多个实施例提供的技术公开的不可分割的部分。
一个或多个实施例针对一种包括暴露的裸片焊盘的半导体器件，该暴露的裸片焊盘可以变换为接触焊盘(焊垫)阵列，从而增加给定封装件的输入/输出线的数量，而不增加尺寸或改变引线数。
一个或多个实施例使得可能通过在相同引线框架中并入多个功能/裸片以在多个器件中使用相同的引线框架，而无需对有源区上焊盘(Pad On Active(POA))规格的实质改变。
例如在混合封装件引线框架和/或多个裸片焊盘功能方面，一个或多个实施例可以提供优于已知解决方案的优点。
在一个或多个实施例中，可以例如通过预镀引线框架(PPF)的方式，经由对裸片焊盘的选择性蚀刻来实现这些结果。
附图说明
现在将参照附图仅通过示例的方式描述一个或多个实施例，其中：
图1是根据一个或多个实施例的半导体器件的截面图，
图2和图3是根据一个或多个实施例的裸片焊盘的示意性平面图(分别从顶部和底部看)，
图4是根据一个或多个实施例的具有焊接在其上的电容器的裸片焊盘的示意性表示，
图5至图7是根据一个或多个实施例的从裸片焊盘的顶部观察的示意性平面图，
图8是根据一个或多个实施例的半导体器件的截面图，
图9是根据图8的器件中的引线框架引线和裸片焊盘的示意性表示，
图10至图12是根据图8的器件中的裸片焊盘/引线框架布置的示意性平面图(在图10和图12的情况下是从底部观察，在图11的情况下是从顶部观察)，
图13是根据一个或多个实施例的半导体器件的截面图，以及
图14是根据一个或多个实施例的工艺的示例性流程图。
应当理解，为了表示的清楚，各个附图可能不是以相同的比例绘制的。
具体实施方式
在随后的描述中，图示了一个或多个具体细节，旨在提供对实施例的示例的深入理解。实施例可以通过一个或多个具体细节或者利用其他方法、部件、材料等来获得。在其他情况下，未详细地图示或描述已知的结构、材料或操作，使得不会使实施例的某些方面变得模糊。
在本说明书的框架中对“实施例”或“一个实施例”的引用旨在表示关于实施例所描述的特定配置、结构、特性符合至少一个实施例。因此，本说明书中的一个或多个点中可能存在的诸如“在实施例中”或“在一个(或多个)实施例中”的短语不一定指代一个相同的实施例。此外，如结合任意附图所例示的特定构造、结构或特性可以在如其他附图中可能示例的一个或多个实施例中以任何其他相当的方式组合。
本文中使用的参考仅仅是为了方便而提供，因此不限定保护的程度或实施例的范围。
用于产生蚀刻引线框架的技术可以用于制造诸如四方扁平无引线(QFN)集成电路的半导体器件。
如所指出的，具有所包括的无源器件的引线框架在本领域中是已知的(如由诸如US 7,489,021 B2的文档所例示的)。
此外，具有堆叠的裸片组件的半导体封装件在本领域中是已知的(如由诸如US2009/0261462A1的文档所例示的)。
此外，在http://www.digikey.com/en/articles/techzone/2014/feb/ optimized-integrated-pol-converters-deliver-performance-without–trade–offs可获得的Ashok Bindra的“Integrated POL(Point of Load)converters deliveringperformance without trade–offs”公开了集成在四方扁平无引线(QFN)器件中的电容器。
图1是半导体封装件或器件10的示例，半导体封装件或器件10包括安装在裸片(支撑)焊盘14上的半导体裸片(或半导体器件本身)12(例如，中间插入有裸片附接材料(DAM)16)。半导体裸片12包括诸如集成电路的一个或多个电气部件。集成电路可以是模拟电路或数字电路，该模拟电路和数字电路可以实现为在裸片内形成的并且根据如本领域中公知的裸片的电气设计和功能而电互连的有源器件、无源器件、导电层和电介质层。
附图标记18标记可以经由打线接合线或网络20电连接到半导体裸片12(更适当地，以接触例如在其上表面处提供的裸片焊盘)的器件的引线框架的接触引脚(引线指或尖端)。
先前讨论的元件可以嵌入(例如，塑料的)封装件22中，封装件22包括诸如所谓的封装模制化合物(PMC)的封装材料，封装材料通过留下封装件22的向外延伸的引脚18的外(远)尖端，被模制在所讨论的各种元件上。
裸片焊盘14可以是“暴露的”类型，即裸片焊盘14从封装件22(例如，在其底部表面处)暴露。
在前面讨论的总体布置在本领域中是常规的，因此为了简洁将不在更详细的描述中进行描述。
在半导体器件10中还提供了至少一个电容器24，如图1所例示的，电容器24通过采取例如“暴露的”裸片焊盘14的选择性蚀刻而嵌入半导体器件10的封装件22中。
图2是包括图1的器件10的接触引脚18和裸片焊盘14的引线框架的示意性俯视图。裸片焊盘在140处示出了用于焊接电容器24的端子240(例如，电源端子和接地端子)的可能位置(点)。
图3是从引线框架的底部观察的对应视图，该视图示出了在图1中的封装件22的(例如，底部)表面处暴露的裸片焊盘14的所暴露的金属材料(例如铜)。
具体地，附图标记1400在图4中标记裸片焊盘14的部分，该部分可以通过(例如，如前所述的)任何已知的蚀刻工艺选择性地蚀刻。例如，所蚀刻的部分1400可以围绕端子140中的一个被蚀刻。
如图1的截面图(其中裸片焊盘14的蚀刻部分再次标记为1400)所例示的，蚀刻可以在金属裸片焊盘中产生“焊垫”(land)1402，“焊垫”1402与裸片焊盘的其余部分分离并且因此可以单独地连接到例如引线框架的任意引脚18。
以示例的方式，在图1的示意性表示中：
-电容器24的端子240中的一个可以连接(例如，焊接)到裸片焊盘14的主体部分，
-端子240的另一个可以连接(例如，焊接)到通过在裸片焊盘14中蚀刻形成的“焊垫”1402，焊垫1402通过接合线(例如，如1404处所示出的)进一步连接到引线框架的引脚18中的一个。
例如，这可以例如经由如图1中示意性地表示的布线来发生，或如图6和图7中示意性地表示的通过与引线框架18中的引脚18中的一个形成为整体(例如，一体件)的焊垫1402来发生。
如在1400处所例示的裸片焊盘14的蚀刻图案可以在各种可能的图案内选择，从而产生相应的各种各样的焊垫形态，包括在裸片焊盘14中产生所蚀刻的多个焊垫1402的可能性。
更一般地，在不必采用额外的分流条/引线的情况下，可以产生多个裸片焊盘焊垫1402以附接例如无源部件或不同的裸片。
图1至图7例示了可以以高自由度选择、而不考虑具体应用的这样的附加部件的放置。
这适用于例如诸如图1中所例示的电容器24的一个或多个电容器。
在一个或多个实施例中，如图1中所例示的半导体器件10的制造可以涉及如图14中所例示的步骤。
即，在开始步骤之后，在一个或多个实施例中可以发生以下步骤：
-1000：电容器放置和焊接(在仍未被蚀刻的裸片焊盘14上)，
-1002：(例如，通过在16处应用裸片附接材料)裸片附接，
-1004：(例如，在20处)打线接合，
-1006：(例如，在22处)封装件模制，
-1008：例如在所暴露的底部处的裸片焊盘蚀刻，以产生焊垫1402，以及
-1010：测试和精加工。
应当理解，该方法可以以不同于所呈现的顺序发生，例如1002裸片附接可以发生在电容器附接之前或者与电容器附接同时发生。
图8至图13例示了根据一个或多个实施例的可能的开发。在这些图中，与已经结合图1至图7所讨论的部分或元件对应的部分或元件已经用相同的附图标记表示，因此不必重复详细描述。
例如，这种开发可以包括提供包含第一半导体裸片121和第二半导体裸片122的“堆叠”布置的半导体器件10，其中例如，第一裸片121具有耦合到裸片焊盘14的电连接焊盘161，并且两个裸片121和122通过如162处所例示的诸如胶带的附接材料相互附接。
图9是根据图8的器件中的引线框架引线和裸片焊盘14的示意性表示。
图10是引线框架的裸片焊盘14的示例性仰视图，该图指示裸片焊盘14的所暴露的金属(例如，铜)区域1400，该金属区域1400可以被蚀刻以产生相应的焊垫1402，例如用于(例如经由焊接)与第一裸片121的连接形成物161电连接。
在一个或多个实施例中，引线框架布置18可以是标准的，其可能在裸片焊盘14的底部表面上具有预镀图案以暴露用于选择性蚀刻(其同样可以根据标准制造流程执行)的铜。
在一个或多个实施例中，一个或多个所蚀刻的焊垫1402可以例如通过如在1404处示意性地指示的接线连接到引线框架18的引脚。
在一个或多个实施例中，可以提供如图11中示意性例示的用于打线接合的对应点(例如，镀点)1404a。
图11是裸片焊盘14的示例性俯视平面图，该图除了打线接合点1404a之外，还示出了用于裸片附接的中心点1406。
同样，根据各种不同的几何形状可以进行(如1400处所例示的)裸片焊盘14的金属材料的蚀刻：图10和图12的比较证明了这一点，二者均是从裸片焊盘14的底部观察的示意性平面图。
图13例示了为第一裸片121提供与用于第二裸片122的打线接合布局202不同的相应打线接合布局(例如，在201处)的可能性，其中相同的附图标记用于标记在前面已讨论的部分或元素(因此不必重复详细的相应描述)。
因此，一个或多个实施例可以包括经由线上流动(FOW)附接技术在162处耦合的第一裸片和第二裸片121、122。
这使得在一个或多个实施例中，制造如图8或图13中所例示的半导体器件可以再次包括步骤1006(封装件模制)、1008(蚀刻所暴露的裸片焊盘14以产生接触焊垫)以及1010(测试和精加工)。
在一个或多个实施例中，当制造如图8或图13中所例示的半导体器件时，步骤1000至步骤1004可以不同于先前结合制造如图1所例示的半导体器件所讨论的类似步骤。
例如，在一个或多个实施例中，在制造如图8所例示的半导体器件中的步骤1000至步骤1004可以包括以下步骤：
-1000：在仍然未蚀刻的裸片焊盘14上安装(例如，在161处-表面安装器件(SMD)-倒装芯片-打线接合)第一裸片121，
-1002：例如，如FOW附接162所例示的，将第二裸片122附接到第一裸片121上，
-1004：为第二裸片122提供打线接合202。
在如图13所例示的一个或多个实施例中，在步骤1000处，第一裸片121可以附接(例如，通过在16处应用裸片附接材料)在仍未蚀刻的裸片焊盘14上，并且可以为第一裸片121提供单独的打线接合201。在这种情况下，在步骤1000之后并且在步骤1002(将第二裸片122附接到第一裸片121上，例如，在162处)之前，在(第一)打线接合步骤1004a中可以提供用于第一裸片121的(第一)打线接合布局201。
应当理解，本文结合附图之一例示的实施例的细节可以自由地转换到其他附图中例示的实施例。
仅仅提及一个示例(这仅仅是非限制性示例)，例如经由与裸片焊盘层14中的电接触焊垫1402耦合的电连接形成物161，第一裸片121与裸片焊盘14的电耦合布置，不以任何方式与第二裸片122的存在相关联，并且可以应用于如图1中所例示的“单裸片”布置。
因此，一个或多个实施例可以提供一种半导体器件(例如，10)，包括：
-至少一个半导体裸片(例如，12或121、122)，
-支撑所述至少一个半导体裸片的(导电的，例如，铜的)裸片焊盘(例如，14)，
-到由所述裸片焊盘支撑的所述至少一个半导体裸片上的封装件(例如，22)，其中所述裸片焊盘在所述封装件的表面处被暴露，以及
-所述暴露的裸片焊盘在其中具有蚀刻图案(例如，1400)，具有形成在所述裸片焊盘中的至少一个电接触焊垫(例如，1402)。
一个或多个实施例可以包括具有至少一个电接触引脚的引线框架(例如，18)，所述至少一个电接触引脚与所述裸片焊盘中的所述至少一个电接触焊垫(例如，经由电容器24或导电路径1404)电耦合。
一个或多个实施例可以包括嵌入在所述封装件中的电容器(例如，24)，其中所述电容器设置在所述至少一个电接触引脚和所述裸片焊盘中的所述至少一个电接触焊垫之间，从而在其间提供电耦合。
在一个或多个实施例中，所述至少一个电接触引脚可以经由接线与所述裸片焊盘中的所述至少一个电接触焊垫(例如，在1404处)电耦合。
一个或多个实施例可以包括裸片焊盘面向半导体器件内部的表面的用于所述接线的至少一个电接触点(例如，1404a)。
在一个或多个实施例中，所述至少一个电接触引脚可以通过与所述裸片焊盘中的所述至少一个电接触焊垫一体成型而与所述至少一个电接触焊盘电耦合。
在一个或多个实施例中，所述至少一个半导体裸片可以经由以下中的至少一个与所述裸片焊盘耦合：
-裸片附接层(例如，16、162)，和/或
-与形成在所述裸片焊盘中的所述至少一个电接触焊垫耦合的至少一个电耦合形成物(例如，161)。
一个或多个实施例可以包括：
-由所述裸片焊盘支撑的第一半导体裸片(例如，121)，以及
-堆叠在所述第一半导体裸片上的至少一个第二半导体裸片(例如，122)。
一个或多个实施例可以包括引线框架(例如，18)，其中所述第一半导体裸片和所述至少一个第二半导体裸片具有到所述引线框架的相应打线接合装置(例如，201、202)。
在一个或多个实施例中，一种提供半导体器件的方法可以包括：
-将至少一个半导体裸片布置在裸片焊盘上，从而，所述至少一个半导体裸片由所述裸片焊盘支撑，
-在由所述裸片焊盘支撑的所述至少一个半导体裸片上形成封装件，所述裸片焊盘在所述封装件的表面处被暴露，以及
-将所蚀刻的图案蚀刻到所述暴露的裸片焊盘中，从而在所述裸片焊盘中形成至少一个电接触焊垫。
在不损害根本原理的情况下，在不脱离保护范围的情况下，细节和实施例可以相对于仅通过示例的方式所公开的内容而变化，甚至显著地变化。
可以组合以上所描述的各种实施例来提供另外的实施例。根据以上详细描述，可以对这些实施例进行这些改变和其他改变。一般来说，在所附权利要求中，所使用的术语不应当被解释为将权利要求限制于说明书和权利要求中公开的具体实施例，而是应当被解释为包括所有可能的实施例以及该权利要求所授权的等同物的全部范围。因此，权利要求不受本公开限制。

Claims (5)

1.一种半导体封装件，包括：
平面裸片焊盘，所述平面裸片焊盘包括第一部分和第二部分，所述第二部分与所述第一部分分离；
多个引线，所述多个引线中的第一引线耦合到所述平面裸片焊盘的所述第二部分，其中所述多个引线中的第一引线与所述平面裸片焊盘的所述第二部分成一体；
耦合到所述平面裸片焊盘的半导体裸片；以及
在所述半导体裸片周围的封装材料，所述平面裸片焊盘的表面在所述封装材料的表面处被暴露。
2.根据权利要求1所述的半导体封装件，其中所述半导体裸片由所述平面裸片焊盘的所述第一部分和所述第二部分支撑。
3.根据权利要求1所述的半导体封装件，包括耦合到所述平面裸片焊盘的电容器，其中所述电容器的第一端子耦合到所述平面裸片焊盘的所述第一部分，并且所述电容器的第二端子耦合到所述平面裸片焊盘的所述第二部分，其中所述半导体裸片耦合到所述第二部分。
4.根据权利要求1所述的半导体封装件，其中所述半导体裸片是第一半导体裸片，所述半导体封装件包括与所述第一半导体裸片垂直堆叠的第二半导体裸片。
5.根据权利要求4所述的半导体封装件，其中所述第二半导体裸片耦合到所述第一半导体裸片的背部表面。
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CN206293435U (zh) * 2016-04-29 2017-06-30 意法半导体股份有限公司 半导体器件与半导体封装件

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