CN100416815C - 包括无源器件的引线框架及其形成方法 - Google Patents
包括无源器件的引线框架及其形成方法 Download PDFInfo
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- CN100416815C CN100416815C CNB2004800047021A CN200480004702A CN100416815C CN 100416815 C CN100416815 C CN 100416815C CN B2004800047021 A CNB2004800047021 A CN B2004800047021A CN 200480004702 A CN200480004702 A CN 200480004702A CN 100416815 C CN100416815 C CN 100416815C
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Abstract
一种半导体器件封装(10)包括一个半导体器件(芯片)(12)和电气连接到一个公共引线框架(17)的无源器件(14)。该引线框架(17)由一个冲压和/或蚀刻的金属结构组成,并包括多个导电引线(16)和多个插入物(20)。将无源器件(14)电气连接到插入物(20)上,并且将芯片(12)上的I/O基座(22)电气连接到引线(16)上。在一个模成分(28)中封装芯片(12)、无源器件(14)和引线框架(17),这形成了一个封装体(30)。引线(16)的底面(38)暴露在封装(10)的底面(34)上。
Description
相关申请的交叉引用
本申请要求提交于2003年2月21日的美国临时专利申请第60/449,049号的优先权,在此通过引用合并了其全部内容。
技术领域
本发明大体上涉及半导体器件封装,特别地,涉及基于引线框架的包括至少一个无源器件的半导体器件封装。
背景技术
在传统的半导体器件封装中,外壳包装半导体器件(芯片)以避免暴露于环境而对芯片的损坏。外壳可以是密封的、包装在塑料中或者是受保护而不受环境影响。
在基于引线框架的半导体器件封装中,通过导电的引线框架,在至少一个芯片和外部电路例如印刷电路板之间发送电信号。所述引线框架包括大量引线,每个引线有一个内部引线端和一个相对的外部引线端。内部引线端被电气连接到芯片上的输入/输出(I/O)基座,并且外部引线端提供了封装体之外的终端。若外部引线端在封装体表面终止,该封装被称为“无引线”封装,而如果外部引线延伸超出了封装体的边缘,则该封装被称为“有引线的”。已知的无引线封装的例子包括方形扁平无引线(QFN)封装,其有四组安放在正方形封装体底部的边缘周围的引线,和双列扁平无引线(DFN)封装,其有两组沿着封装体底部的相对侧安放的引线。在提交于2002年4月29日的共同拥有的美国专利申请序列号10/134,882中公开了用于制造基于引线框架的封装的方法,并且在此通过引用合并了其全部内容。
在许多电子装配中,将无源元件像例如电容器、电感器和电阻器与半导体器件封装相互连接以提供所需的功能。迄今,这些无源元件中的大部分无法以有成本效益的方式集成在包装的芯片封装之内。
从制造商和用户的观点看,由于外部连接增加了(最终转移给用户的)制造成本并且随着信号从外部元件的传播会将噪声引入封装中,电子装配要求尽可能少的这种连接是合乎需要的。
因此,发明者意识到存在着对改进的半导体器件封装的需求,包括一种用于接近芯片地安放无源元件和用于在单个封装中包装所述无源元件和芯片的有成本效益的方法。
发明内容
通过一种半导体器件封装,可以克服或减轻现有技术的上述及其它缺点和不足,其包括:一个封装体;一个安放在所述封装体之内的半导体器件;至少一个安放在所述封装体之内的无源器件;以及一个由导电材料形成的引线框架。所述引线框架包括多个电连接到所述半导体器件上的I/O基座的引线,暴露于所述封装体的第一表面,以及多个电连接到所述至少一个无源器件的第一插入物。可以从电容器、电感器和电阻器中选择所述至少一个无源器件。所述封装体可以由封装所述半导体芯片的至少一部分、所述至少一个无源元件的至少一部分、以及所述引线框架的至少一部分的模成分形成。引线可以充分地暴露而与所述封装体的表面共面。
可以将所述半导体器件上的I/O基座引线接合或带状接合到多个引线。在一个实施例中,所述引线框架进一步包括一个芯片基座,从而使所述半导体器件固定在该芯片基座上。在另一实施例中,所述半导体器件的一部分从封装体中暴露出来。作为替代地,将所述半导体器件上的I/O基座焊接到附着于多个引线上以形成倒装晶片连接的第二插入物上的接合位置。以支柱暴露在封装体表面的方式,支柱可以安放在第一和/或第二插入物上的接合位置之下。
在另一方面,一种半导体器件封装包括:一个形成第一封装表面的至少一部分的模成分;至少一个由所述模成分至少部分地覆盖的无源器件;一个由所述模成分至少部分地覆盖的半导体器件,该半导体器件包括多个I/O基座;以及一个由导电材料形成并且由所述模成分部分地覆盖的引线框架。该引线框架包括:多个引线,每个引线有一个第一表面,其形成电气连接到多个I/O基座中的至少一个I/O基座的接合位置,和一个暴露在第一封装表面上的第二表面,以及多个电气连接到所述至少一个无源器件的插入物。所述多个插入物每个有一个与所述多个引线的第一表面共面的第三表面,并且所述多个插入物中的每个插入物的至少一部分与所述第一封装表面相间隔。
在另一方面,一种形成一个半导体器件封装的方法包括:从导电材料形成一个引线框架,其包括:在所述导电材料中形成多个引线和多个第一插入物,并且蚀刻所述多个引线和所述多个插入物的底面,所述蚀刻定义了多个触点上的第一表面;将半导体器件上的I/O基座电气连接到所述多个引线;电气连接至少一个无源器件横穿多个插入物中的多个第一插入物对;以及使用模成分覆盖所述引线框架、所述半导体器件和所述至少一个无源器件中的每一个的至少一部分。所述模成分形成第一封装表面的至少一部分。每个引线的第一表面暴露在第一封装表面上,并且每个第一插入物的至少一部分与第一封装表面相间隔。
可以将半导体器件上的I/O基座引线接合或带状接合到所述多个引线。形成所述引线框架可以进一步包括从导电材料形成一个芯片基座。在本实施例中,所述方法进一步包括将半导体器件固定到芯片基座上。在另一实施例中,部分半导体器件暴露在第一封装表面上。在另一实施例中,将半导体器件上的I/O基座电气连接到所述多个引线包括,将I/O基座焊接到引线框架上的接合位置以形成一个倒装晶片连接。在该实施例中,形成引线框架可能进一步包括形成多个连接到多个引线的第二插入物,同时在所述第二插入物上形成接合位置。而且在该实施例中,蚀刻可以进一步定义在第二插入物上的接合位置之下的支柱,同时在使用模成分覆盖之后,所述支柱暴露在第一封装表面上。
在所述方法中,蚀刻可以进一步定义一个从所述多个第一插入物中的至少一个第一插入物延伸出来的支柱,同时在使用模成分覆盖之后,该支柱暴露在第一封装表面上。可以在使用模成分覆盖之前,将每个引线的支柱和第一表面附着于一个表面上。
在下文的附图和描述中,提出了本发明的一个或多个实施例的细节。从这些描述和附图以及从权利要求书中,本发明的其它特征、目的和优势将是显而易见的。
附图说明
从结合附图进行的下述详细描述,本发明将被更充分地理解,其中同样的元件编号相同,并且其中:
图1是依照本发明的一个实施例的基于引线框架的包括无源器件的半导体器件封装的部分横断面透视图;
图2是用于图1的所述装置的引线框架的俯视图;
图3是图2的引线框架的仰视图;
图4是图3沿着截面4-4的引线框架的侧面图;
图5是有连接到其上的无源器件的图2的引线框架的透视图;
图6是有一个芯片和连接到其上的无源器件的图2的引线框架的俯视图;
图7是在成型之后基于引线框架的半导体器件封装的顶端透视图;
图8是在成型之后基于引线框架的半导体器件封装的仰视图;
图9是用于基于引线框架的半导体器件封装中的替代引线框架的俯视图;
图10是图9的替代引线框架的仰视图;
图11是图9的替代引线框架沿着图10的截面11-11的侧视图;
图12是包括图9的替代引线框架的半导体器件封装的仰视图;
图13是用于基于引线框架的半导体器件封装中的另一替代引线框架的俯视图;
图14是图13的替代引线框架的仰视图;
图15是图13的替代引线框架沿着图14的截面15-1 5的侧视图;以及
图16是包括图13的替代引线框架的半导体器件封装的仰视图。
具体实施方式
图1是一个半导体器件封装10的部分剖视图,其包括一个半导体器件(芯片)12和电气连接到一个公共引线框架17的无源器件14。引线框架17由一个冲压和/或蚀刻的金属结构组成,并包括多个导电引线16和多个插入物20。将可能包括电容器、电感器、电阻器或任何别的这种无源电子器件的无源器件14电气连接到插入物20上。在所示的实施例中,将芯片12上的I/O基座22通过导线26电气连接到在引线16上形成的接合位置24;然而,如下文中将进一步详细描述的,可以使用其它方法电气连接I/O基座22和接合位置24。而且在所示的实施例中,引线框架17包括一个芯片支撑基座54,在其上放置芯片12。将芯片12、无源器件14、导线26和引线框架17封在模成分28中,其形成一个分别有顶部、底部和侧面(表面)32、34和36的封装体30。引线16的底面38暴露在封装10的底面34上,并且可被电气连接到外电路,例如印刷电路板等等。
图2是在半导体器件封装制造过程的成型步骤之前所示的引线框架17的俯视图。图3是图2的引线框架17的仰视图,图4是引线框架1 7沿着图3的截面4-4的侧视图。如图2中可看到的,可以通过外部框架50来互相连接大量引线框架16以便于制造多个封装10。在通常在应用模成分28(图1)之后进行的成型步骤期间,沿着线52切割引线框架16以删除外部框架50并分离出单独的引线框架16。
在图2-4所示的引线框架17中,在芯片支撑基座(芯片基座)54的两个相对侧上安放四个引线16。从芯片基座54的每个拐角延伸出来的是一个连接杆56,其用于在(图1)模成分28之内固定芯片基座54。安放在两个连接杆56之间形成的间隔中的是插入物20。在所示的实施例中,引线框架17包括两个大体上L形的插入物20。应当意识到可以按照对(图1)无源器件14的类型的需要,改变插入物20的数量和配置。此外,应当意识到可以按照对特定应用的需要,修改引线16的数量、配置和位置。例如,尽管引线16表示为位于接近封装10的底面34的边缘,引线16可以替代地位于底面34上的其它位置上。引线16和插入物20互相间隔,且远离芯片基座54,以便在成型处理之后引线16和插入物20互相电气隔离并且与芯片基座54电气隔离。
如图3和4所示,从每个大体上L形的插入物20的底部延伸出来的是一个支柱58,其具有与引线16的底面38和芯片基座54的底面62共面的底面60。安放在连接杆56之一上的标签64包括一个从其上延伸的指示柱66,其底部与引线16、芯片基座54和支柱58的底面共面。
引线框架17可以由任何一片适当的导电材料最好是铜或铜基合金形成。就铜基合金来说,这意味着按重量算,该材料包含超过50%的铜。这片形成引线框架17的导电材料最好有在约0.10mm至约0.25mm之间的、在图4中表示为T1的厚度,并且在约0.15mm至约0.20mm之间更好。可以使用任何已知的方法例如冲压、化学蚀刻、激光消融等等来形成包括芯片基座54、引线16、插入物20和连接杆56在内的引线框架17的每个特征的前身。引线框架17包括一个厚度减小的区域,其在图3中由阴影线表示,在图4中由T2表示。可以使用受控制的削减工艺,例如化学蚀刻或激光消融来形成材料厚度的减少以形成厚度减小的区域。例如,分别打算形成引线16、支柱58和芯片基座54的底面38、60和62的每个表面可以镀上一层化学保护层,并且无覆盖的表面暴露在适当的蚀刻剂中一段时间以有效除去足够的材料从而实现厚度T2。厚度T2最好在引线框架17的厚度Tl(即用于形成引线框架的材料厚度)的约25%至约60%之间,并且在该厚度的约40%至约50%之间更好。该优选范围之内的厚度提供了在厚度减小的部分之下的足够间隙,以容纳用于在封装10之内锁定引线框架17的模成分。
在形成引线框架17的各种特征之后,将支柱58、引线16和芯片基座54的底面附着到图5中所示的一个表面100上。在所示的实施例中,在胶带上形成表面100,其接触并固定分别形成支柱58、引线16和芯片基座54的底面的、基本共面的表面60、38和62。尽管图5只画出了单个引线框架17,应当意识到可以提供如图2和3所示的多个互相连接的引线框架16。
由于引线框架17附着于表面100上,那么无源器件14可被电气连接到引线框架17上。在所示的实施例中,每个无源器件14从一个插入物20延伸到另一个,跨越插入物20之间的空间。例如,在大体上L形的插入物20和大体上T形的插入物20之间电气连接两个无源器件14,而在大体上L形的插入物20之间电气连接一个无源器件14。无源器件14可以使用任何便利的方法像例如焊接、导电性胶粘剂或环氧树脂等等,附着在插入物20上。有利的是,一个引线框架17的设计可以用于许多不同类型的插入物14。
图6是在将导线26接合到芯片12上的I/O基座22、引线16上的接合位置24和插入物20上的接合位置104之后,引线框架17的俯视图。在接合导线之前,使用任何便利的方法例如焊接、环氧树脂、双面胶带等等,将芯片12固定到芯片基座54上。在将芯片12固定到芯片基座54上之后,将导线26分别地连接在芯片12上的I/O基座22和各个引线16上的接合位置24之间,以及在插入物20上的接合位置104和一个或多个引线16上的接合位置24之间。支柱58位于插入物20上的接合位置104之下,以保持接合位置104与引线16的共面性,从而允许导线26的精确接合,以及因而减少在封装10制造中的缺陷。此外,支柱58传递与导线26在(图5)表面100上的接合相关的力量,从而允许使用各种各样的引线接合法。例如,可以使用超声波焊接来进行引线接合,其中应用压力和超声波振动脉冲的组合来形成冶金冷焊;热压焊,其中应用压力和高温的组合来形成焊接;或热声接合,其中应用压力、高温和超声波振动脉冲的组合来形成焊接。用于接合中的导线类型最好由金、金基合金、铝或铝基合金。作为引线接合的替代,也可以使用带状自动接合(TAB)。
在接合导线26之后,使用模成分28来覆盖芯片12、引线框架17、无源器件14和导线26,如图1和7所示。可以使用任何便利的技术,例如传递或喷射成型工艺,来施加模成分28。模成分28是电气绝缘的材料,最好是聚合物模树脂,例如环氧树脂,其流体温度范围在约250℃至约300℃之间。模成分28也可以是低温热玻璃合成物。
在施加模成分28的期间,支柱58、引线16和芯片基座54的底面60、38和62分别保持附着在(图5)表面100上以阻止引线框架17运动,并且因此有助于确保导线接合不被干扰或破坏。此外,在引线框架17的厚度减小部分之下形成的容间容纳模成分28,并用于固定封装10之内的插入物20、引线16和芯片基座54。
在施加模成分28之后,除去粘着的(图5)表面100,并且如果必要,通过冲压、或用刀刃锯、喷水管、激光等等来成型附着的封装10。图7是封装10在成型之后的顶部透视图,图8是封装10在成型之后的仰视图。参见图7和8,在除去粘着的表面100(图5)并成型之后,暴露出每个封装10的引线框架17部分。特别地,引线16部分、插入物20部分和连接杆56部分暴露在封装10的侧面36上。如图8所示,芯片基座54、引线16、支柱58和标识柱66的底面暴露在封装10的底面34上。
在所示的实施例中,每个引线16暴露在侧面36上的部分通过模成分28从其相关的底面38上隔开,这形成封装10的整个底边。作为替代地,可以配置一个或多个触点16,以便引线16暴露在侧面36上的部分在封装10的底边处与引线16的底面38相连接。在该实施例,所述一个或多个引线16形成封装10的底边的一部分。在典型的配置中,只有引线16的底面38将被用于连接外部电路。然而,如果希望的话,支柱58的底面60也可以连接到外部电路。
参见图9-11,表示的是用于封装10中的替代的引线框架120。引线框架120与图2-4中所示的引线框架17基本上相似,除了使用插入物122来配置引线框架120,以用于倒装晶片方式电气连接芯片12和引线16。也就是说,倒转芯片12以便(图1)I/O基座22表面向下,并且通过焊接等将I/O基座22直接电气连接到在插入物122顶部形成的接合位置124。可选地,引线框架120也可以包括在大体上L形插入物20和一个或多个引线16之间延伸的插入物126。在插入物122上的接合位置124之下形成支柱128,以在焊接和密封处理期间支撑该接合位置124。
插入物122的增加消除了对图2-4的芯片基座54的需求,因为插入物122在封装10之内支撑芯片12。此外,插入物122和126的增加消除了对上述引线接合或带状接合步骤的需求。另外,使用引线框架120来制造封装10基本上与上面描述的相似,而产生如图12所示的有底面34的封装10。
如图12所示,引线16、支柱58和支柱128的底面暴露在封装10的底面34上。在典型配置中,只有引线16的底面38将被用于连接到外部电路。然而,如果希望的话,支柱58和/或128的底面38也可以连接到外部电路。若支柱128的底面38用于连接外部电路,可以从引线框架120中删除引线16和插入物122。在此情况下,支柱128作为封装10的引线。如同在此描述的任何实施例,应当意识到可以按照特定应用的需要,修改引线16的数量、配置和位置。例如,尽管将引线16表示为位于接近封装10的底面34的边缘,引线16可以替代地位于底面34上的其它位置上。
参见图13-15,表示的是用于封装10中的另一替代引线框架150。引线框架150基本上与图2-4所示的引线框架17相似,除了引线框架150并不包括芯片基座54。在该配置中,在引线接合和密封处理期间由(图5)表面100来支撑芯片12。另外,使用引线框架130来制造封装10基本上与上面描述的相似,而产生如图16所示的有底面34的封装10。芯片12、引线16和支柱58的底面暴露在封装10的底面34上。
在在此描述的任意实施例中,无源器件14位于紧密接近于芯片12的位置,产生了总尺寸小于传统的多元件芯片封装的封装10。发明者意识到本发明的配置验证了在元件之间更快的电连接,因为外部引线更少,元件之间的导线长度更短。该封装可以用作双列扁平无引线装配的插入式替换,像例如小外形集成电路(SOIC)、薄缩小外形封装(TSSOP)、四分之一尺寸外形封装(QSOP)等等。
尽管结合首选实施例描述并示意了本发明,可以进行对熟悉技术的人来说显而易见的许多变化和修改,而无需背离本发明的精髓和范围。举例来说,应当意识到采用替换的封装配置是在本发明的范围之内。各种修改可以包括,例如在芯片附着和/或引线接合之前或之后应用电镀。
因此,本发明的讲授并非意在限制任何具体的半导体芯片封装配置,例如上文详细描述的配置。同样地,在附上的权利要求书中提出的本发明并不限制上文提出的构造的精确细节,因而对熟悉技术的人来说显而易见的其它变化和修改,如同在定义的权利要求中提出的,被确定为包括在本发明的精髓和范围之内。
Claims (33)
1. 一种配置用来电气连接到一个外部电路的半导体器件封装(10),所述半导体器件封装(10)包括:
一个封装体(30);
一个安放在所述封装体(30)之内的半导体器件(12);
至少一个安放在所述封装体(30)之内的无源器件(14);以及
一个由导电材料形成的引线框架(17),所述引线框架(17)包括:
接近所述封装体(30)的第一侧面(36)排列的多个第一引线(16),
接近所述封装体的第二侧面(36)排列的多个第二引线(16),将所述多个第一和第二引线(16)电气连接到所述半导体器件(12)上的I/O基座(22),所述多个第一和第二引线中的每个引线(16)包括一个从所述封装体(30)暴露出来的第一表面(38)以电气连接到外部电路,以及
电气连接到所述至少一个无源器件(14)的多个第一插入物(20),将所述多个第一插入物(20)中的至少一个插入物(20)电气连接到多个第一和第二引线(16)中的至少一个引线(16)以将所述至少一个无源器件(14)电气连接到外部电路,其中将所述多个第一插入物(20)、所述半导体器件(12)和所述至少一个无源器件(14)安放在所述多个第一和第二引线(16)之间。
2. 权利要求1的半导体器件封装(10),其中所述封装体(30)由封装所述半导体芯片(12)的至少一部分、所述至少一个无源元件(14)的至少一部分和所述引线框架(17)的至少一部分的模成分(28)形成。
3. 权利要求2的半导体器件封装(10),其中暴露所述引线(16)的第一表面(38),使其与所述封装体(30)的表面(34)共面。
4. 权利要求1的半导体器件封装(10),其中所述至少一个无源器件(14)是从由电容器、电感器和电阻器组成的组中挑选出来的。
5. 权利要求1的半导体器件封装(10),其中所述引线框架(17)进一步包括一个安放在多个第一和第二引线(16)之间的芯片基座(54),所述半导体器件(12)被固定到所述芯片基座(54)。
6. 权利要求1的半导体器件封装(10),其中所述半导体器件(12)的一部分从所述封装体(30)中暴露出来。
7. 权利要求1的半导体器件封装(10),其中将所述半导体器件(12)上的I/O基座(22)焊接到所述引线框架(17)上的接合位置(124)以形成一个倒装晶片连接。
8. 权利要求7的半导体器件封装(10),其中在连接到所述多个第一和第二引线(16)的第二插入物(122)上形成所述接合位置(124)。
9. 权利要求8的半导体器件封装(10),其中所述第二插入物(122)各自包括一个安放在接合位置(124)之下的支柱(128),所述支柱(128)暴露在封装体(10)的表面(34)上。
10. 权利要求8的半导体器件封装(10),其中通过至少一个第三插入物(126),将所述多个第一插入物(20)中的至少一个插入物(20)电气连接到所述多个第一和第二引线(16)中的至少一个引线(16)上。
11. 权利要求1的半导体器件封装(10),其中将所述半导体器件(12)上的I/O基座(22)引线接合或带状接合到所述多个第一和第二引线(16)。
12. 权利要求1的半导体器件封装(10),其中所述多个第一插入物(20)中的至少一个第一插入物(20)包括一个从其上延伸的支柱(58),所述支柱(58)暴露在封装体(10)的表面(34)上。
13. 一种半导体器件封装(10),其包括:
形成第一封装表面(34)的至少一部分的模成分(28);
由所述模成分(28)至少部分地覆盖的至少一个无源器件(14);
一个由所述模成分(28)至少部分地覆盖的半导体器件(12),所述半导体器件(12)包括多个I/O基座(22);以及
一个由导电材料形成并且由所述模成分(28)部分地覆盖的引线框架(17),所述引线框架(17)包括:
接近所述封装体(30)的第一侧面(36)排列的多个第一引线(16),
接近所述封装体(30)的第二侧面(36)排列的多个第二引线(16),所述多个第一和第二引线中的每个引线具有一个形成电气连接到多个I/O基座(22)中的至少一个I/O基座(22)的接合位置的第一表面,和一个暴露在第一封装表面(34)上的第二表面(38),以及
电气连接到至少一个无源器件(1 4)的多个第一插入物(20),所述多个第一插入物(20)各自包括从所述插入物(20)的表面延伸的支柱(58),所述支柱(58)具有一个与所述多个第一和第二引线(16)的第一表面共面的表面,从而使所述多个第一插入物(20)中的每个第一插入物(20)的至少一部分与所述第一封装表面(34)相间隔,其中将所述多个第一插入物(20)、所述半导体器件(12)和所述至少一个无源器件(14)安放在多个第一和第二引线(16)之间。
14. 权利要求13的半导体器件封装(10),其中所述至少一个无源器件(14)是从由电容器、电感器和电阻器组成的组中挑选出来的。
15. 权利要求13的半导体器件封装(10),其中所述引线框架(17)进一步包括一个安放在多个第一和第二引线(16)之间的芯片基座(54),所述半导体器件(12)被固定到所述芯片基座(54)。
16. 权利要求13的半导体器件封装(10),其中所述半导体器件(12)的一部分暴露在第一封装表面(34)上。
17. 权利要求13的半导体器件封装(10),其中将所述半导体器件(12)上的I/O基座(22)焊接到引线框架(17)上的接合位置(124)以形成一个倒装晶片连接。
18. 权利要求17的半导体器件封装(10),其中在连接到所述多个第一和第二引线(16)的多个第二插入物(122)上形成所述接合位置(124)。
19. 权利要求18的半导体器件封装(10),其中所述第二插入物(122)均包括一个安放在接合位置(124)之下的支柱(128),所述支柱(128)暴露在第一封装表面(34)上。
20. 权利要求13的半导体器件封装(10),其中所述多个第一插入物(20)中的至少一个第一插入物(20)包括一个从其上延伸的支柱(58),所述支柱(58)暴露在第一封装表面(34)上。
21. 权利要求13的半导体器件封装(10),其中将所述半导体器件(12)上的I/O基座(22)引线接合或带状接合到所述多个第一和第二引线(16)。
22. 权利要求13的半导体器件封装(10),其中将所述多个第一和第二引线(16)中的至少一个引线(16)电气连接到所述多个第一插入物(20)中的至少一个第一插入物(20)上。
23. 一种形成一个半导体器件封装(10)的方法,该方法包括:
从导电材料形成一个引线框架(17),其包括:
用导电材料形成多个第一引线(16)、多个第二引线(16)和多个第一插入物(20),所述多个第一插入物(20)安放在多个第一和第二引线(16)之间,所述多个第一插入物(20)各自包括从所述插入物(20)的表面延伸的支柱(58)以及
蚀刻所述多个第一和第二引线(16)和多个第一插入物(20)的底面,该蚀刻定义了在多个第一和第二引线(16)上的多个第一表面(38)和在从第一插入物(20)延伸的支柱上的多个第二表面(60),第一表面(38)与第二表面(60)是共面的;
将半导体器件(12)上的I/O基座(22)电气连接到多个第一和第二引线(16),所述半导体器件(12)安放在多个第一和第二引线(16)之间;
电气连接至少一个无源器件(14)跨过多个第一插入物(20)中的若干第一插入物(20)对;以及
使用模成分(28)覆盖引线框架(17)、半导体器件(12)和所述至少一个无源器件(14)中的每一个的至少一部分,所述模成分(28)形成第一封装表面(34)的至少一部分,其中每个引线(16)的第一表面(38)暴露在第一封装表面(34)上,并且每个第一插入物(20)的至少一部分通过所述支柱与第一封装表面(34)相间隔。
24. 权利要求23的方法,其中所述至少一个无源器件(14)是从由电容器、电感器和电阻器组成的组中挑选出来的。
25. 权利要求23的方法,其中形成所述引线框架(17)进一步包括,从导电材料形成一个芯片基座(54),并且所述方法进一步包括:
将半导体器件(12)固定到所述芯片基座(54)上。
26. 权利要求23的方法,其中所述半导体器件(12)的一部分暴露在第一封装表面(34)上。
27. 权利要求23的方法,其中将所述半导体器件(12)上的I/O基座(22)电气连接到多个第一和第二引线(16)包括:
将I/O基座(22)焊接到引线框架(17)上的接合位置(124)上以形成一个倒装晶片连接。
28. 权利要求27的方法,其中形成所述引线框架(17)进一步包括形成多个连接到多个第一和第二引线(16)的第二插入物(122),所述接合位置(124)在第二插入物(122)上形成。
29. 权利要求28的方法,其中所述蚀刻进一步定义了安放在第二插入物(122)上的接合位置(124)之下的支柱(128),在使用模成分(28)覆盖之后,所述支柱(128)暴露在第一封装表面(34)上。
30. 权利要求23的方法,其中所述蚀刻进一步定义了从所述多个第一插入物(20)中的至少一个第一插入物(20)中延伸出来的支柱(58),在使用模成分(28)覆盖之后,所述支柱(58)暴露在第一封装表面(34)上。
31. 权利要求30的方法,进一步包括:
在使用模成分(128)覆盖之前,将所述支柱(58)和每个引线(16)的第一表面(38)粘着到一个表面(100)上。
32. 权利要求23的方法,其中将所述半导体器件(12)上的I/O基座(22)电气连接到多个第一和第二引线(16)包括:
将I/O基座(22)引线接合或带状接合到多个第一和第二引线(16)。
33. 权利要求23的方法,进一步包括:
将所述多个第一和第二引线(16)中的至少一个引线(16)电气连接到多个第一插入物(20)中的至少一个第一插入物(20)上。
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2004
- 2004-02-17 US US10/563,172 patent/US7489021B2/en not_active Expired - Lifetime
- 2004-02-17 JP JP2006503649A patent/JP2007521643A/ja not_active Abandoned
- 2004-02-17 KR KR1020057015419A patent/KR20050109502A/ko not_active Application Discontinuation
- 2004-02-17 EP EP04711876A patent/EP1602130A4/en not_active Withdrawn
- 2004-02-17 WO PCT/US2004/004676 patent/WO2004077508A2/en active Application Filing
- 2004-02-17 CN CNB2004800047021A patent/CN100416815C/zh not_active Expired - Fee Related
- 2004-02-20 TW TW093104345A patent/TWI334212B/zh not_active IP Right Cessation
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US6054764A (en) * | 1996-12-20 | 2000-04-25 | Texas Instruments Incorporated | Integrated circuit with tightly coupled passive components |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107342276A (zh) * | 2016-04-29 | 2017-11-10 | 意法半导体股份有限公司 | 半导体器件及相应方法 |
CN107342276B (zh) * | 2016-04-29 | 2022-06-10 | 意法半导体股份有限公司 | 半导体器件及相应方法 |
Also Published As
Publication number | Publication date |
---|---|
CN1751390A (zh) | 2006-03-22 |
TWI334212B (en) | 2010-12-01 |
EP1602130A4 (en) | 2008-11-05 |
TW200504983A (en) | 2005-02-01 |
WO2004077508A3 (en) | 2005-01-27 |
EP1602130A2 (en) | 2005-12-07 |
US7489021B2 (en) | 2009-02-10 |
KR20050109502A (ko) | 2005-11-21 |
JP2007521643A (ja) | 2007-08-02 |
WO2004077508A2 (en) | 2004-09-10 |
US20080036034A1 (en) | 2008-02-14 |
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