CN100514580C - 可颠倒无引线封装及其堆叠 - Google Patents

可颠倒无引线封装及其堆叠 Download PDF

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Publication number
CN100514580C
CN100514580C CNB2004800243737A CN200480024373A CN100514580C CN 100514580 C CN100514580 C CN 100514580C CN B2004800243737 A CNB2004800243737 A CN B2004800243737A CN 200480024373 A CN200480024373 A CN 200480024373A CN 100514580 C CN100514580 C CN 100514580C
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Prior art keywords
encapsulation
pillar
lead
circuit chip
semiconductor packages
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CNB2004800243737A
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CN1842906A (zh
Inventor
沙菲杜尔·伊斯拉姆
罗马里考·S·圣安托尼奥
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Advanced Interconnect Technology Ltd
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Advanced Interconnect Technology Ltd
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Abstract

一种半导体器件封装，包括具有布置在封装的周边处的多个支柱的导电引线框架。支柱的每一个具有布置在第一封装面处的第一接触表面和布置在第二封装面处的第二接触表面。引线框架也包括布置在第二封装面处的多个支柱延伸部。支柱延伸部的每一个包括在与第二封装面相对的支柱延伸部的表面上形成的接合点。在半导体器件上的至少一个I/O焊盘，使用导线接合、卷带自动接合或倒装芯片法电气连接到在接合点处的支柱延伸部上。封装使用具有预成形引线的、有或没有抽头的引线框架组装，或者它能采用部分蚀刻引线框架的使用。可以形成半导体器件封装的堆叠。

Description

可颠倒无引线封装及其堆叠
对于相关申请的交叉引用
本申请要求提交于2003年8月26日的美国临时专利申请No.60/497,829(代理人案号no.102451-100)的优先权，该美国临时专利申请全文引用以作为参考。
技术领域
本发明涉及半导体器件封装。更具体地说，本发明涉及可颠倒无引线半导体器件封装和用来制造可颠倒无引线半导体器件封装的方法。
背景技术
在基于引线框架的半导体器件封装中，电信号通过导电引线框架在至少一个半导体器件(电路芯片(die))与诸如印刷电路板之类的外部电路之间传输。引线框架包括多根引线，每根具有内部引线端和相对的外部引线端。内部引线端电气连接到在电路芯片上的输入/输出(I/O)焊盘上，并且外部引线端提供用来连接到外部电路的端子。在外部引线端在封装本体的表面处终止的场合，封装称作“没有引线”或“无引线”封装。如果外部引线端超越封装本体周边延伸，则封装称作“有引线的”。已知的无引线封装的例子包括：四边扁平无引线(QFN)封装，它们具有在四边封装本体的底部的周边周围布置的四组引线；和双边扁平无引线(DFN)封装，它们具有沿封装本体的底部的相对侧布置的两组引线。
一种用来制造用于四边扁平无引线(“QFN”)封装的引线框架的方法公开在授予McLellan等的美国专利No.6,498,099中，该专利全文引用作为参考。在McLellan等的专利中，导电基片的第一侧被部分蚀刻以限定支撑垫和内部引线端。半导体器件接合到部分限定的支撑垫上，并且由导线接合等电气互连到部分限定的内部引线端上。半导体器件、部分限定的支撑垫、部分限定的内部引线及导线接合然后封装在聚合物模制树脂中。导电基片的相对第二侧然后被蚀刻，以电气隔离支撑垫和内部引线端以及限定外部引线端。
另一种用于QFN封装的制造的方法公开在提交于2002年4月29日并且在此全文引用作为参考的共同拥有的美国专利申请No.10/134,882中。
希望在半导体封装工业中使半导体封装的外形高度(厚度)最小以促进在移动、无线及医学用途中的进步。当前要求是对于具有亚毫米级的外形高度的封装。对于增大处理能力和速度的需要，也产生增加能配合到给定区域上的电路芯片数量(即增加电路芯片密度)以及减小在电路芯片之间的电气路径的长度的需求。
对于用于增加电路芯片密度和减小电气路径长度的需求的一种解决方案是在单个封装内部堆叠多个电路芯片。各电路芯片由绝缘层/插入物分离，使导线接合和/或倒装芯片电路芯片连接用来把电路芯片电气连接到公共引线框架上。然而，这种解决方案具有其缺点。首先，具有堆叠电路芯片的封装至少部分由于在封装内的增大数量的电气连接和对于布置在电路芯片之间的绝缘层/插入物的需要而引入封装组件的复杂性。如果任意缺陷在封装的组装期间发生，包括在堆叠内的所有芯片的整个封装是不可补救的。第二，在导线接合过程用来电气连接堆叠电路芯片的场合，在堆叠中的顶部电路芯片必须把尺寸定成在底部电路芯片上提供足够的外围空间以允许导线接合底部电路芯片。换句话说，顶部电路芯片必须比底部电路芯片小。最后，在单个封装中堆叠两个或多个电路芯片增大封装的厚度，并且产生关于功率管理和散热的问题。
因而，存在对于具有减小外形尺寸同时允许增大电路芯片密度和减小在电路芯片之间的电气路径的长度的半导体器件封装的需要。
发明内容
上述和其它需要由一种包括模制化合物的半导体器件封装满足，该模制化合物形成如下的一部分：第一封装面、与第一封装面相对的第二封装面、以及在第一与第二封装面之间延伸的封装侧面。半导体器件和导电引线框架至少部分地由模制化合物覆盖。导电引线框架包括布置在封装的周边处、并且具有布置在第一封装面处的第一接触表面和布置在第二封装面处的第二接触表面的多个支柱。半导体器件定位在多个支柱的中心。引线框架还包括多个支柱延伸部，每个具有布置在第二封装面处的第三接触表面。该多个支柱延伸部从多个支柱向半导体器件延伸。每一个支柱延伸部包括在与第二封装面相对的支柱延伸部的表面上形成的接合点。在半导体器件上的至少一个I/O焊盘电气连接到在接合点处的支柱延伸部。
在一个实施例中，I/O焊盘的至少一个被导线接合或带接合到接合点上。在另一个实施例中，I/O焊盘的至少一个直接电气连接到接合点上，用来形成倒装芯片型连接。该半导体器件封装可以具有四个封装侧面，使多根引线布置在四个封装侧面的两个中。可选择地，该半导体器件封装可以具有四个封装侧面，使多根引线布置在所有四个封装侧面中。在另一个实施例中，形成半导体器件封装的堆叠。
在另一个方面，一种在制造半导体器件封装时使用的方法包括：(a)由导电材料形成多个支柱，该多个支柱具有与半导体器件封装的预定外形高度相等的高度，并且在多个支柱中的每个支柱具有定位在预定封装侧面处的侧表面；(b)把半导体器件布置在由多个支柱限定的中央区域内，半导体器件包括布置在其上的多个I/O焊盘；(c)把多个I/O焊盘电气连接到从多个支柱突出的相关导电支柱延伸部上；以及(d)用模制化合物覆盖电路芯片、多个支柱以及支柱延伸部的至少一部分。
把I/O焊盘电气连接到接合点上可以包括把I/O焊盘导线接合或直接电气连接到接合点上，以形成倒装芯片型连接。在支柱的每一个的端部上的接触表面可以直接电气连接到相邻半导体器件封装的接触表面上。
在一个实施例中，形成多个支柱包括：选择具有与半导体器件封装的预定外形高度相等的外形高度的导电材料片；和，选择性地从片除去材料以形成支柱。在另一个实施例中，形成多个支柱包括：选择具有比半导体器件封装的预定高度大的外形高度的导电材料片；和，选择性地从片除去材料，以在导电材料的基片部分上形成支柱。在这个实施例中，该方法还包括：在用模制化合物覆盖电路芯片和支柱及支柱延伸部之后，除去导电材料的基片部分。
本发明的一个或多个实施例的细节在附图和下面的描述中叙述。本发明的其它特征、目的及优点通过描述和附图以及由权利要求变得明显。
附图说明
由结合其中类似元件被类似标号的附图进行的如下详细描述，将更充分地理解本发明，并且在附图中：
图1是按照本发明一个实施例的一种四边、无引线、导线接合的半导体器件封装的部分剖开、顶部立体图；
图2是图1的半导体器件封装的横截面视图；
图3是图1的半导体器件封装的仰视图；
图4是图1的半导体器件封装的俯视图；
图5a-5j描绘使用用来组装半导体器件的第一方法在组装的各个阶段中的图1的半导体器件封装；
图6a-6j描绘使用用来组装半导体器件的第二方法在组装的各个阶段中的图1的半导体器件封装；
图7是按照本发明另一个实施例的一种四边、无引线、倒装芯片半导体器件封装的部分剖开、顶部立体图；
图8是图7的半导体器件封装的横截面视图；
图9是图7的半导体器件封装的可选择布置的横截面视图；
图10是图7的半导体器件封装的俯视图；
图11是图7的半导体器件封装的仰视图，表示选择性引线轨迹；
图12a-12h描绘使用用来组装半导体器件的第一方法在组装的各个阶段中的图7的半导体器件封装；
图13a-13h描绘使用用来组装半导体器件的第二方法在组装的各个阶段中的图7的半导体器件封装；
图14是一半导体器件封装堆叠的横截面视图，每个半导体器件封装布置有直立位置的电路芯片；
图15是一半导体器件封装堆叠的横截面视图，每个半导体器件封装布置有颠倒位置的电路芯片；及
图16是一半导体器件封装堆叠的横截面视图，每个半导体器件封装以交替直立和颠倒位置布置。
具体实施方式
参照图1和2，表示一种四边、无引线、导线接合的半导体器件封装10。半导体器件封装10具有底部封装面12、与底部封装面12相对的顶部封装面14、以及在底部与顶部封装面12、14之间延伸的封装侧面16。各个封装面部分地由模制化合物18形成，该模制化合物18覆盖半导体器件(电路芯片)20和导电引线框架22的部分。导电引线框架22包括多根引线23。引线23的每一根包括布置在封装的周边处的支柱24。支柱24的每一个具有布置在顶部封装面14处的第一接触表面26和布置在底部封装面12处的第二接触表面28。电路芯片20连到定位在由多个支柱24形成的中央区域中的电路芯片支撑垫30上。每根引线也包括支柱延伸部32，具有布置在底部封装面12处的接触表面34。每个支柱延伸部32从相关支柱24向电路芯片20延伸，使支柱24和支柱延伸部32形成用来接收电路芯片20的凹进部分。每个支柱延伸部32包括形成在与底部封装面12相对的支柱延伸部32的表面上的接合点36。在表示的实施例中，接合点36经导线40电气连接到相关输入/输出I/O焊盘38上。
引线23彼此以及与电路芯片垫30间隔开，以把引线23彼此电气隔离以及与电路芯片垫30隔离开。从电路芯片垫30的四个角部的每一个延伸的是系杆42，系杆42表示为具有从其端部延伸的突起的一般为直的杆。系杆42用于把电路芯片垫30锚定在模制化合物18内。
在表示的实施例中，引线框架22包括布置在封装10的四侧的每一个上的三根引线23。然而，将理解，引线23的数量和位置可以按具体用途的需要而修改。例如，对于在双边、无引线半导体封装中的使用，引线框架22可以包括布置在封装10的相对侧上的两组引线23。
封装10提供外形高度，如在图2中在50处指示的那样，该高度典型地大于包围电路芯片20的厚度的几倍。例如，对于约0.2毫米(mm)的电路芯片外形高度(以52指示)，封装外形高度50可以是约0.5mm，使支柱延伸部32、电路芯片支撑垫30以及系杆42具有约0.1mm的外形高度(以54指示)。考虑到在电路芯片20与电路芯片支撑垫30之间的约0.025mm的接合材料层，约0.175mm剩余在电路芯片20上方，用来接收接合导线(以56指示)。支柱的外形高度等于封装的外形高度50(约0.5mm)，使支柱相对于接合点的外形高度(以58指示)是约0.4mm。一般地说，封装10可以具有比电路芯片20的外形高度52大约大2.5倍的外形高度50。
如图3中所示，每根引线23的一部分在封装10的底部封装面12上暴露。引线23的暴露部分包括在支柱24的每一个上的接触表面28、和支柱延伸部32的接触表面34。如图4中所示，在引线23的每一根上的接触表面28在封装10的顶部封装面14处暴露。图3和4的比较表明，包括支柱24的每一个的接触表面28和支柱延伸部32的接触表面34的在底部封装面12上的总接触表面面积大于在顶部封装面14处的接触表面26。封装10在接触表面26、28或34的任一个处和/或在支柱24的暴露侧表面60处(图2)可以电气连接到外部电路上，如连接到印刷电路板、另一个半导体器件封装、或试验装置上。电信号经每个I/O焊盘38、导线40、支柱延伸部32及支柱24在电路芯片20与外部电路之间传输。
引线框架22的设计允许封装10使用用于标准QFN组装和修整的相同设备来组装。例如，封装10能使用具有预成形引线的、有或没有抽头的引线框架来组装，或者它能采用部分蚀刻引线框架的使用，其中基片被部分地蚀刻以限定引线23，并且除去基片以在封装后形成引线。这些方法的每一种在下文讨论。
现在参照图5，表示使用采用具有预成形引线23的引线框架22的方法在组装的各个阶段的半导体器件封装10。图5a是三个互连引线框架22的平面图，并且图5b-5j是在各个组装阶段中的互连引线框架22的横截面视图。如图5中所示，多于一个引线框架22优选地部分连接，以允许封装10的同时组装。可设想的是，可选择地，封装10可以个别地组装。
引线框架22可以由任何适当的导体片形成，并且优选地是铜或铜基合金。铜基合金是指包含按重量计大于50％的铜的材料。形成引线框架22的传导材料片具有与封装10的希望外形高度相等的外形高度。
使用诸如压印、化学蚀刻、激光烧蚀等之类的任何已知方法可以形成包括电路芯片支撑垫30、引线23以及系杆42的引线框架22的各特征。优选地使用诸如化学蚀刻或激光烧蚀之类的受控去除过程形成在这些特征的每一个中形成的各种凹进部分。例如，打算形成支柱24的接触表面26的每个表面可以涂有化学抗蚀剂，并且剩余表面暴露于适当蚀刻剂一段时间，以便有效地把在剩余表面下面的厚度减小到支柱延伸部32、电路芯片支撑垫30以及系杆42的希望厚度(即外形高度)。这些结构的预期上表面然后可以涂有化学抗蚀剂，并且剩余表面暴露于蚀刻剂一段时间，以便有效除去除了引线23、支撑垫30以及系杆42之外的材料。
参照图5c，在形成引线框架22之后，在支柱延伸部32上的接合点36可以镀有便于与接合导线接合的材料。例如，在使用金接合导线的场合，接合点36可以镀有金。可选择地，依据具体应用或使用的接合导线的类型，可以镀敷整个引线框架22，或者可以不进行镀敷。
参照图5d，在准备导线接合时，支柱24的底部接触表面28、支柱延伸部32的接触表面34、以及电路芯片支撑垫30的底部表面固定到表面70上。在所示的实施例中，表面70形成在粘合带上，该粘合带接触和固定大体共面的接触表面28和34及电路芯片支撑垫73的底部表面。
参照图5e，其次使用任何便利的方法，如焊料、环氧树脂、双面粘合带等，把电路芯片20固定到支撑垫30上。在电路芯片20固定到支撑垫30上之后，导线40个别地连接在电路芯片20上的I/O焊盘38与在相应引线23上的接合点36之间。
在使用图5的方法组装封装期间，支柱延伸部32用电路芯片支撑垫30固定到表面70上，因而允许导线40精确地接合到接合点36上，结果，减小在封装10的组件中的缺陷。另外，因为支柱延伸部32沿其整个长度由表面70支撑，所以本发明允许在导线接合时使用比对于先有技术的引线可能的更广泛的各种接合方法和导线材料。例如，可以使用其中施加压力和超声波振动脉冲串的组合以形成冶金冷焊接的超声波接合、其中施加压力和升高温度的组合以形成焊接的热压缩接合，或其中施加压力、升高温度以及超声波振动脉冲串的组合以形成焊接的热声波接合，从而进行导线接合。在接合中使用的导线40的类型优选地由金、金基合金、铝或铝基合金制成。作为对于导线接合的选择例，可以使用卷带自动接合(TAB)。
参照图5g，在完成导线接合之后，电路芯片20、引线框架22以及接合导线40用模制化合物18覆盖。模制化合物18可以使用任何便利的技术施加，如使用转移或注射模制过程。模制化合物是具有在约150℃至约300℃之间的范围内的流动温度(flow temperature)的电绝缘材料，优选的是聚合物模制树脂，如环氧树脂。模制化合物18也可以是低温热玻璃复合物。在模制化合物18的施加期间，在引线23之间的空隙被保持，因为支柱24和支柱延伸部32固定到表面70上。
参照图5h，在涂敷之后，互连的封装10与表面70分离，并且连接表面28和34镀敷有便于与外部电路电气连接的材料。如果整个引线框架22以前被镀敷，则连接表面28和34的镀敷可能是不必要的。
连接的封装10然后通过用刀片锯、水喷射等分成单个的，如图5i中所示。在分成单个之后，暴露所有支柱24的侧表面60。
封装10如希望的那样可使用在底部封装面12和/或顶部封装面14上的接触表面26、28和/或34电气连接到印刷电路板、另一个封装或任何其它外部电路上，因而使得封装10是完全可颠倒的。就是说，封装10可以在使电路芯片20处于直立位置中的情况下被安装，或者封装10可以在使电路芯片20倒置的情况下颠倒和安装，如图5j中所示。封装10的可颠倒性减轻了对于在要求电路芯片20面向上或向下的应用之间的任何电路芯片20或封装10重新设计的需要。在封装顶部和底部面14、12上的接触表面26、28及34也允许多个封装10堆叠，以提供增大的芯片密度。另外，接触表面26、28及34或侧表面60的任意表面可以用作测试点，以测试封装10的电气功能或测试封装10对于外部电路的电气连接。侧表面60也起到可见指示器的作用，以保证当把封装10表面安装到印刷电路板上时与在印刷电路板上的垫的适当对准。
现在参照图6，表示使用一种采用部分蚀刻的引线框架的方法在组装的各个阶段中的半导体器件封装10。图6a是引线框架22的前驱体72的平面图，并且图6b是引线框架前驱体72的横截面视图。优选地连接多个引线框架前驱体72，以允许同时组装。可设想的是，可选择地，可以个别地组装引线框架前驱体72。
引线框架前驱体72可以由任何适当的导体片形成，并且优选地是铜或铜基合金。铜基合金是指包含按重量大于50％的铜的材料。形成引线框架前驱体的传导材料片具有比封装10的希望外形高度大的外形高度。
优选地使用诸如化学蚀刻和激光烧蚀之类的受控去除过程形成在引线框架前驱体72的每一个中形成的各种特征。例如，预期形成支柱24的接触表面26的每个表面可以涂有化学抗蚀剂，并且剩余表面暴露于适当的蚀刻剂一段时间，以便有效地减小在剩余表面下面的厚度，从而达到支柱相对于接合点36的希望外形高度。接着，支柱延伸部32、电路芯片支撑垫30以及系杆(未表示)的预期上表面然后可以涂有化学抗蚀剂，并且剩余表面暴露于蚀刻剂一段时间，以便有效除去足够量的材料以提供支柱24、支柱延伸部32、支撑垫30以及系杆(未表示)相对于剩余材料的上表面74的希望高度，该剩余材料形成基片76。这个过程导致部分形成的支柱24、支柱延伸部32、系杆以及支撑垫30，它们所有都从基片76延伸。
参照图6c，在支柱延伸部32上的接合点36可以镀敷有便于导线接合的材料。例如，在使用金接合导线的场合，接合点可以镀有金。
参照图6d，接着使用任何便利的方法，如焊料、环氧树脂、双面粘合带等，把电路芯片20固定到支撑垫30上。在电路芯片20固定到支撑垫30上之后，导线40个别地连接在电路芯片20上的I/O焊盘38与在相应引线23上的接合点36之间，如图6e中所示。
在图6的方法中，支柱延伸部32与电路芯片支撑垫30一起从公共表面-基片76延伸，因而允许导线40精确地接合到接合点36上。结果，减小封装10的组件中的缺陷。另外，因为支柱延伸部32沿其整个长度由基片76支撑，所以在导线接合时可以使用比对于先有技术的设计可能的更广泛的各种接合方法和导线材料。例如，可以使用其中施加压力和超声波振动脉冲串的组合以形成冶金冷焊接的超声波接合、其中施加压力和升高温度的组合以形成焊接的热压缩接合、或其中施加压力、升高温度以及超声波振动脉冲串的组合以形成焊接的热声波接合，从而进行导线接合。在接合中使用的导线的类型优选地由金、金基合金、铝或铝基合金制成。作为对于导线接合的选择例，可以使用卷带自动接合(TAB)。
参照图6f，在完成导线接合之后，电路芯片20、引线框架前驱体72以及接合导线40用模制化合物18覆盖。模制化合物18可以使用任何便利的技术施加，如使用转移或注射模制过程。模制化合物是具有在约150℃至约300℃之间的范围内的流动温度的电绝缘材料，优选的是聚合物模制树脂，如环氧树脂。模制化合物18也可以是低温热玻璃复合物。
在引线框架前驱体72用模制化合物18封装之后，使用诸如化学蚀刻和激光烧蚀之类的受控去除过程除去基片材料76。这个步骤的结果表示在图6g中。基片材料76的除去创建电路芯片垫30和系杆(未表示)的接触表面28和34及底部表面。这些表面可以被镀敷以便于至外部电路的电气连接。而且，焊料球78可以连到接触表面28和/或34上，以便于与外部电路电气连接，如图6h中所示。
连接的封装10然后通过用刀片锯、水喷射等分成单个的，如图6i中所示。在分成单个之后，暴露所有支柱24的侧表面60。生成的封装10与由参照图5描述的方法生成的相同。封装10可以在使电路芯片20处于直立位置的情形下被安装，或者封装10可以在使电路芯片20倒置的情形下颠倒和安装，如图6j中所示。
参照图7和8，表示一种四边形、无引线、倒装芯片半导体器件封装100。图7的封装100大体与在图1和2中表示的封装10类似，不同之处在于，在封装100中的电路芯片20使用倒装芯片法连接到引线框架102上。作为结果，没有使用电路芯片支撑垫30或系杆42。可设想的是，图1和2的引线框架22可以用于倒装芯片和导线接合封装10和100，通过除去电路芯片支撑垫30和杆42使引线框架22修改成用于倒装芯片封装100的引线框架102。
封装100提供外形高度，如在图8中在50处指示的那样，该外形高度典型地比包围电路芯片20的厚度大几倍。例如，对于约0.2毫米(mm)的电路芯片外形高度52，封装外形高度50可以是约0.5mm，使支柱延伸部32具有约0.1mm的外形高度54。考虑到回流之后在电路芯片20与接合点36之间的约0.075mm的接合高度104，约0.125mm剩余在电路芯片20上方，如在56处指示的那样。支柱24的外形高度等于封装100的外形高度50(约0.5mm)，使支柱24相对于接合点36的外形高度58是约0.4mm。一般地说，封装100可以具有比电路芯片的外形高度52大约大2.5倍的外形高度50。
图9表示以110指示的一种四边、无引线、倒装芯片半导体器件封装的另一个实施例。除电路芯片20的一侧在封装110中在顶部封装面14上暴露之外，封装110与封装100(图8)相同。在顶部封装面14上暴露电路芯片20，对于控制在电路芯片20中的热量可能是有益的，并且允许较薄的轮廓高度50。例如，对于约0.2毫米(mm)的电路芯片20外形高度56，封装110外形高度50可以是约0.4mm，使支柱延伸部32具有约0.1mm的外形高度54。考虑到回流之后在电路芯片20与接合点36之间的约0.075mm的接合高度104，封装110外形高度50为0.4mm。支柱24的外形高度等于封装110的外形高度50(约0.4mm)，使支柱24相对于接合点36的外形高度58是约0.3mm。一般地说，封装110可以具有比电路芯片20的外形高度56大约大2倍的外形高度50。
图10和11分别表示封装100的俯视图和仰视图。如图10中所示，在引线23的每一个上的接触表面28在封装10的顶部封装面14处暴露。如图11中所示，每个引线23的一部分在封装10的底部封装面12上暴露。引线23的暴露部分包括在支柱24的每一个上的接触表面28，以及支柱延伸部32的接触表面34。可选择地，支柱延伸部32的每一个可以成形为包括在支柱延伸部32与电路芯片20之间延伸的、与具有在电路芯片垫38之间的细沟的电路芯片一起使用的插入物108。
用来制造图8和9的封装100和110的方法与参照图5和6描述的那些类似，主要不同之处在于，电路芯片20直接电气连接到接合点36上，如图8和9中所示，而不是如图5和6中表示的那样连到支撑垫上并且导线接合或带接合到接合点36上。“直接”电气连接是指互连而不使用插入导线接合或卷带自动接合带。适当的连接包括具有从包括金、锡和铅的组选择的主要成分的焊料。
现在参照图12，表示使用一种采用具有预成形引线23的引线框架102的方法在组装的各个阶段中的半导体器件封装100。尽管表示图8的封装100，但参照图12描述的方法同样可应用于图9的封装110。图12a是引线框架102的平面图，并且图12b是引线框架102的横截面视图。如图12中所示，多于一个引线框架102部分互连，以允许同时组装。可设想的是，可选择地，引线框架102可以个别地组装。引线框架102可以使用以上参照图5描述的方法形成，而不形成电路芯片支撑垫或系杆。
参照图12c，在准备电路芯片20对于引线23的接合时，支柱24的第二接触表面28和支柱延伸部32的接触表面34可以固定到表面70上。在表示的实施例中，表面70形成在粘合带上，该粘合带接触和固定大体共面的接触表面28和32。
参照图12d，在电路芯片20上的I/O焊盘38使用任何便利方法直接电气连接到接合点36上。支柱延伸部32沿其整个长度由表面70支撑，保证接合点36的共面性。因为确保接合点36的共面性，所以增加倒装芯片接合的精度，并因此减小制造缺陷的机会。
在I/O焊盘38已经电气连接到其相关接合点36上之后，电路芯片20和引线框架102覆盖以模制化合物18，如在图12e中描绘的那样。模制化合物18可以使用任何便利的技术施加，如使用转移或注射模制过程。模制化合物18是具有在约150℃至约300℃之间的范围内的流动温度的电绝缘材料，优选的是聚合物模制树脂，如环氧树脂。模制化合物18也可以是低温热玻璃复合物。在模制化合物18的施加期间，在引线23之间的空隙被保持，因为它们固定到表面70上。在电路芯片20和引线框架102被涂敷之后，互连封装100与表面70分离(例如，除去带)。
参照图12f，连接表面28和34可以镀敷有便于与外部电路电气连接的材料。如果整个引线框架102先前被镀敷，则连接表面28和34的镀敷可能是不必要的。
连接的封装100然后通过用刀片锯、水喷射等分成单个的，如图12g中所示。在分成单个之后，暴露每个支柱24的侧表面60。
接触表面26、28及34如希望的那样允许封装100使用在顶部封装面14或底部封装面12上的触点电气连接到印刷电路板、另一个封装、或任何其它外部电路上，因而使封装100是完全可颠倒的。就是说，封装100可以在使电路芯片100处于直立位置的情形下被安装，或者封装100可以在使电路芯片100倒置的情况下颠倒和安装，如图12h中所示。这减轻了对于在要求电路芯片20面向上或向下的应用之间的任何电路芯片20或封装100重新设计的需要。在封装顶部和底部面14、12上的接触垫26、28及34也允许多个封装100堆叠，以提供增大的芯片密度。支柱24的侧表面60可以用作测试点，以测试封装100的电气功能或测试封装100对于外部电路的电气连接。侧表面60也起到可见指示器的作用，以保证当把封装100表面安装到印刷电路板上时与在印刷电路板上的垫的适当对准。
现在参照图13，表示使用一种采用部分蚀刻的引线框架的方法在组装的各个阶段中的半导体器件封装100。尽管示出图8的封装100，但参照图12描述的方法同样可应用于图9的封装110。图13a是引线框架102的前驱体114的平面图，并且图13b是引线框架前驱体114的横截面视图。多个引线框架前驱体114优选地部分连接，以允许同时组装。可设想的是，可选择地，引线框架前驱体114可以个别地组装。引线框架前驱体114可以使用以上参照图6描述的方法形成，而不形成电路芯片支撑垫或系杆。
参照图13c，在电路芯片20上的I/O焊盘38使用任何便利方法直接电气连接到接合点36上。支柱延伸部32沿其整个长度由基片材料76支撑，由此保证接合点36的共面性。因为保证接合点36的共面性，所以增加倒装芯片接合的精度，并因此减小制造缺陷的机会。
在I/O焊盘38已经电气连接到其相关接合点36上之后，电路芯片20和引线框架前驱体114覆盖以模制化合物18，如在图13d中描绘的那样。模制化合物18可以使用任何便利的技术施加，如使用转移或注射模制过程。模制化合物18是具有在约150℃至约300℃之间的范围内的流动温度的电绝缘材料，优选的是聚合物模制树脂，如环氧树脂。模制化合物18也可以是低温热玻璃复合物。
在用模制化合物18覆盖电路芯片20和引线框架前驱体114之后，使用诸如化学蚀刻或激光烧蚀之类的受控去除过程除去基片材料76。基片材料76的除去创建接触表面28和34，如在图13(e)中描绘的那样。这些表面可以被镀敷以便于至外部电路的电气连接。而且，焊料球78可以连到接触表面28和或34上，以便于电气连接，如图13f中所示。
连接的封装100然后通过用刀片锯、水喷射等分成单个的，如图13g中所示。在分成单个之后，暴露每个支柱24的侧表面60。
生成的封装100与由参照图9描述的方法生成的相同。封装100可以在使电路芯片20处于在直立位置的情况下被安装，或者封装100可以在使电路芯片倒置的情况下颠倒和安装，如图13h中所示。
在图1-10的实施例中，在封装顶部和底部面14、12上的接触表面26、28及34的可用性允许多个封装堆叠，以提供增大的芯片密度。如图14中所示，在每个封装100上的接触表面26、28及/或34可以直接电气连接在相邻封装100上的对应接触表面26、28及/或34，以形成堆叠。适当的连接包括具有从包括金、锡和铅的组选择的主要成分的焊料。因为封装100被直接电气连接，所以在电路芯片20之间的电气路径的长度保持为最小。封装100可以布置成使电路芯片直立20，如图14中所示，或者使电路芯片20倒置，如图15中所示。可选择地，如图16中所示，在一个封装100上的接触表面26或28可以直接电气连接到在相邻封装100上的相同接触表面26或28上，从而封装以交替的顶部对顶部和底部对底部方式堆叠。尽管在图14-16中以举例子的目的表示了封装100，但这里描述的任一个实施例可以以同一方式堆叠。
与在公共封装中采用堆叠电路芯片以减小堆叠的外形的、增加芯片密度的常规方法相比，这里描述的封装的堆叠减小堆叠组装的复杂性，同时提供类似的芯片密度。复杂性的减少至少部分归因于当在公共封装中堆叠电路芯片时使用的绝缘层/插入物的消除。此外，本发明的封装提供从顶部封装面14、底部封装面12或侧面16测试的能力。这呈现显著优点：能够辨别在堆叠中的哪个封装是有故障的。如果发现封装的任一个有缺陷，则能丢弃个别封装和其芯片，因而减小与要求处置在公共封装中的多个芯片的现有技术封装有关的浪费。最后，作为引线具有与封装相同的外形高度和形成封装侧面的部分的结果，本发明的封装提供优于对于现有技术布置可能的增加的散热。
本发明保证可以单独使用或在要求芯片密度增大的场合可以堆叠的减小的外形封装。封装使用在封装的底部面和/或顶部面上的任何接触表面能电气连接到印刷电路板、另一个封装、或任何其它外部电路上，因而使封装是完全可颠倒的。就是说，封装可以在使电路芯片处于直立位置的情况下安装，或者封装可以在使电路芯片倒置的情况下颠倒和安装。封装的可颠倒性减轻了对于在要求电路芯片面向上或向下的应用之间的任何电路芯片或封装重新设计的需要。
本发明的封装可以使用用于标准QFN组装和修整的相同设备组装，并且能使用具有预成形引线的引线框架或使用部分蚀刻的引线框架组装。封装能使用导线接合、卷带自动接合或倒装芯片法组装，在这些不同方法的每一种之间仅稍微改进引线框架。
已经描述了本发明的多个实施例。尽管如此，应理解，在不脱离本发明的精神和范围的前提下可以进行各种修改。因而，其它实施例在如下权利要求的范围内。

Claims (8)

1.一种半导体器件封装(10，100)，包括：
模制化合物(18)，用于形成如下的一部分：
第一封装面(14)，
第二封装面(12)，其与第一封装面(14)相对，及
封装侧面(16)，其在第一与第二封装面(14，12)之间延伸；
具有相对的第一和第二侧面的设在中央的支撑垫(30)，所述第一侧面与所述第二封装面(12)共面；
半导体器件(20)，其至少部分地由模制化合物(18)覆盖且贴附到所述支撑垫(30)的所述第二侧面，该半导体器件(20)包括多个I/O焊盘(38)；及
导电引线框架(22)，其包括：
多个支柱(24)，其布置在封装(10，100)的周边处，每个支柱(24)具有布置在第一封装面(14)处的第一接触表面(26)和布置在第二封装面(12)处的第二接触表面(28)，该半导体器件(20)定位在由多个支柱(24)限定的中央区域中，和
多个支柱延伸部(32)，每个支柱延伸部(32)具有布置在第二封装面(12)处的第三接触表面(34)，该多个支柱延伸部(32)从多个支柱(24)向半导体器件(20)延伸，该支柱延伸部(32)的每一个包括在与第二封装面(12)相对的支柱延伸部(32)的表面上形成的接合点(36)，至少一个I/O焊盘(38)在接合点(36)处电气连接到支柱延伸部(32)，其中所述接合点(36)与所述支撑垫(30)的所述第二侧面共面。
2.根据权利要求1所述的半导体器件封装(10)，其中，该至少一个I/O焊盘(38)被导线接合或带接合到接合点(36)上。
3.根据权利要求1所述的半导体器件封装(10，100)，其中，该半导体器件封装(10，100)具有四个封装侧面(16)，并且该多个支柱(24)布置在该四个封装侧面(16)的两个中。
4.根据权利要求1所述的半导体器件封装(10，100)，其中，该半导体器件封装(10，100)具有四个封装侧面(16)，并且该多个支柱(24)布置在所有四个封装侧面(16)中。
5.一种半导体器件封装(10，100)的堆叠，每个半导体器件封装(10，100)包括：
模制化合物(18)，用于形成如下的一部分：
第一封装面(14)，
第二封装面(12)，其与第一封装面(14)相对，及
封装侧面(16)，其在第一与第二封装面(14，12)之间延伸；
具有相对的第一和第二侧面的设在中央的支撑垫(30)，所述第一侧面与所述第二封装面(12)共面；
半导体器件(20)，其至少部分地由模制化合物(18)覆盖且贴附到所述支撑垫(30)的所述第二侧面，该半导体器件(20)包括多个I/O焊盘(38)；及
导电引线框架(22)，其包括：
多个支柱(24)，其布置在封装(10，100)的周边处，每个支柱(24)具有布置在第一封装面(14)处的第一接触表面(26)和布置在第二封装面(12)处的第二接触表面(28)，该半导体器件(20)定位在由该多个支柱(24)限定的中央区域中，和
多个支柱延伸部(32)，每个支柱延伸部(32)具有布置在第二封装面(12)处的第三接触表面(34)，该多个支柱延伸部(32)从该多个支柱(24)向半导体器件(20)延伸，支柱延伸部(32)的每一个包括在与第二封装面(12)相对的支柱延伸部(32)的表面上形成的接合点(36)，至少一个I/O焊盘(38)在接合点(36)处电气连接到支柱延伸部(32)，其中所述接合点(36)与所述支撑垫(30)的所述第二侧面共面；
其中，半导体器件封装(10，100)的至少一个的第一接触表面(26)直接电气连接到相邻半导体器件封装(10，100)的第一和第二接触表面(26，28)的一个上。
6.根据权利要求5所述的半导体器件封装(10)的堆叠，其中，该至少一个I/O焊盘(38)被导线接合或带接合到接合点(36)上。
7.根据权利要求5所述的半导体器件封装(10，100)的堆叠，其中，每个半导体器件封装(10，100)具有四个封装侧面(16)，并且该多个支柱(24)布置在该四个封装侧面(16)的两个中。
8.根据权利要求5所述的半导体器件封装(10，100)的堆叠，其中，每个半导体器件封装(10，100)具有四个封装侧面(16)，并且该多个支柱(24)布置在所有四个封装侧面(16)中。
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EP1668686A4 (en) 2006-09-13
CN1842906A (zh) 2006-10-04
CN101587869B (zh) 2011-04-13
KR20060121823A (ko) 2006-11-29
CN101587869A (zh) 2009-11-25
WO2005022591A3 (en) 2005-10-20
TWI368276B (en) 2012-07-11
TW200520091A (en) 2005-06-16
US7709935B2 (en) 2010-05-04
US8058104B2 (en) 2011-11-15
WO2005022591A9 (en) 2005-06-02
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