JP2015035554A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2015035554A JP2015035554A JP2013166808A JP2013166808A JP2015035554A JP 2015035554 A JP2015035554 A JP 2015035554A JP 2013166808 A JP2013166808 A JP 2013166808A JP 2013166808 A JP2013166808 A JP 2013166808A JP 2015035554 A JP2015035554 A JP 2015035554A
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- Prior art keywords
- wiring
- chip
- terminal
- resin sealing
- semiconductor device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
【解決手段】本発明は、ダイパッド10と、ダイパッド10上に搭載された半導体チップ14と、一端が半導体チップ14に接続されるワイヤ30a、30bと、ワイヤ30a、30bの他端が接続されると共に、上端よりも大きい面積の下端を有する入力端子26及び出力端子28と、ダイパッド10、半導体チップ14、ワイヤ30a、30b、入力端子26、及び出力端子28を封止し、上面に入力端子26及び出力端子28の上端が露出すると共に、下面に入力端子26及び出力端子28の下端が上端よりも大きい面積で露出してなる樹脂封止部32と、を備える半導体装置である。
【選択図】図1
Description
11 リードフレーム
14 半導体チップ
26 入力端子
28 出力端子
30a〜30d ワイヤ
32 樹脂封止部
34 基準電位端子
40 プリント基板
44、44a、44b 入力配線
46、46a、46b 出力配線
48、48a、48b 基準電位配線
50〜58 チップ部品
100〜400 半導体装置
Claims (3)
- ダイパッドと、
前記ダイパッド上に搭載された半導体チップと、
一端が前記半導体チップに接続される接続部と、
前記接続部の他端が接続されると共に、上端よりも大きい面積の下端を有する端子と、
前記ダイパッド、前記半導体チップ、前記接続部、及び前記端子を封止し、上面に前記端子の前記上端が露出すると共に、下面に前記端子の前記下端が前記上端よりも大きい面積で露出してなる樹脂封止部と、を備えることを特徴とする半導体装置。 - 上面にチップ部品が搭載され、下面に前記チップ部品に接続された電極が設けられた基板をさらに備え、
前記基板の前記電極は、前記樹脂封止部の上面に露出した前記端子の前記上端に接続され、前記樹脂封止部の下面に露出した前記端子の前記下端は、外部と接続される接続部となることを特徴とする請求項1記載の半導体装置。 - 前記端子の側面は、前記樹脂封止部の側面から露出していることを特徴とする請求項1または2記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013166808A JP2015035554A (ja) | 2013-08-09 | 2013-08-09 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2013166808A JP2015035554A (ja) | 2013-08-09 | 2013-08-09 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015035554A true JP2015035554A (ja) | 2015-02-19 |
JP2015035554A5 JP2015035554A5 (ja) | 2016-09-23 |
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JP2013166808A Pending JP2015035554A (ja) | 2013-08-09 | 2013-08-09 | 半導体装置 |
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JP (1) | JP2015035554A (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018170331A (ja) * | 2017-03-29 | 2018-11-01 | 旭化成エレクトロニクス株式会社 | 半導体装置 |
CN108831871A (zh) * | 2018-06-08 | 2018-11-16 | 郑州云海信息技术有限公司 | 一种提升qfn封装零件焊接质量的设计方法 |
KR20200087200A (ko) * | 2017-12-27 | 2020-07-20 | 미쓰비시덴키 가부시키가이샤 | 반도체 장치 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11307675A (ja) * | 1998-04-20 | 1999-11-05 | Matsushita Electron Corp | 樹脂封止型半導体装置及びその製造方法 |
JP2001177007A (ja) * | 1999-12-21 | 2001-06-29 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2003289128A (ja) * | 2002-01-23 | 2003-10-10 | Matsushita Electric Ind Co Ltd | 回路部品内蔵モジュールおよびその製造方法 |
JP2007503721A (ja) * | 2003-08-26 | 2007-02-22 | アドバンスド インターコネクト テクノロジーズ リミテッド | リバーシブル・リードレス・パッケージとその製造および使用方法 |
-
2013
- 2013-08-09 JP JP2013166808A patent/JP2015035554A/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11307675A (ja) * | 1998-04-20 | 1999-11-05 | Matsushita Electron Corp | 樹脂封止型半導体装置及びその製造方法 |
JP2001177007A (ja) * | 1999-12-21 | 2001-06-29 | Hitachi Ltd | 半導体装置及びその製造方法 |
JP2003289128A (ja) * | 2002-01-23 | 2003-10-10 | Matsushita Electric Ind Co Ltd | 回路部品内蔵モジュールおよびその製造方法 |
JP2007503721A (ja) * | 2003-08-26 | 2007-02-22 | アドバンスド インターコネクト テクノロジーズ リミテッド | リバーシブル・リードレス・パッケージとその製造および使用方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018170331A (ja) * | 2017-03-29 | 2018-11-01 | 旭化成エレクトロニクス株式会社 | 半導体装置 |
KR20200087200A (ko) * | 2017-12-27 | 2020-07-20 | 미쓰비시덴키 가부시키가이샤 | 반도체 장치 |
KR102351764B1 (ko) * | 2017-12-27 | 2022-01-14 | 미쓰비시덴키 가부시키가이샤 | 반도체 장치 |
US11335619B2 (en) | 2017-12-27 | 2022-05-17 | Mitsubishi Electric Corporation | Semiconductor device |
CN108831871A (zh) * | 2018-06-08 | 2018-11-16 | 郑州云海信息技术有限公司 | 一种提升qfn封装零件焊接质量的设计方法 |
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