CN105514057B - 高密度集成电路封装结构以及集成电路 - Google Patents

高密度集成电路封装结构以及集成电路 Download PDF

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Publication number
CN105514057B
CN105514057B CN201610027678.8A CN201610027678A CN105514057B CN 105514057 B CN105514057 B CN 105514057B CN 201610027678 A CN201610027678 A CN 201610027678A CN 105514057 B CN105514057 B CN 105514057B
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package structure
integrated circuit
line
chip
lead
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CN105514057A (zh
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梁大钟
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CHINA CHIPPACKING TECHNOLOGY Co Ltd
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CHINA CHIPPACKING TECHNOLOGY Co Ltd
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Priority to CN201610027678.8A priority Critical patent/CN105514057B/zh
Publication of CN105514057A publication Critical patent/CN105514057A/zh
Priority to TW105119856A priority patent/TWI628724B/zh
Priority to US15/260,069 priority patent/US9768101B2/en
Priority to JP2016177079A priority patent/JP2017126733A/ja
Priority to PCT/CN2017/070874 priority patent/WO2017121336A1/zh
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
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Abstract

本发明涉及一种高密度集成电路封装结构以及集成电路，属于集成电路封装的技术领域。本发明所述的高密度集成电路封装结构，包括密封金属引线框、芯片以及微米级连接线的长方体塑封结构，所述塑封结构的长度A1满足关系：1.20 mm +（B‑8）×0.3 mm /2≤A1≤4.50 mm +（B‑8）×1.00 mm /2；塑封结构的宽度A2满足关系：1.20 mm≤A2≤3.50 mm；塑封结构的厚度A3满足关系：A3≥0.35mm；B为外引脚线的个数。本发明的封装结构，能够适应芯片制造技术从微米级向亚微米，纳米级发展的需要，满足了低功耗、高速度、大容量、小体积的便携式产品需求。

Description

高密度集成电路封装结构以及集成电路
技术领域
本发明涉及集成电路封装的技术领域，更具体地说，本发明涉及一种高密度集成电路封装结构以及具有该封装结构的集成电路。
背景技术
集成电路是现代技术的核心，也是现代科学技术发展的基础，科学研究都必须依赖以集成电路为核心的仪器设备；另外它还是人类现代文明的基础，从根本上改变人们生活方式的现代文明，如物联网、互联网、电脑、电视、冰箱、手机、IPAD、IPHONE、各种自动控制设备等等都依赖集成电路来实现其智能化功能的。
集成电路的制造分设计、圆片制造、封装、测试几个主要部分，封装是其中关键环节，建立在封装技术上的封装形式是为满足各种用途对集成电路的性能、体积、可靠性、形状和成本的特殊要求而研制的。
集成电路封装：是指通过使用能够保证单晶材料完美晶格结构的研磨、切割技术将集成电路圆片分离成符合要求的单一芯片，用导电胶或共晶等技术将芯片固定到引线框基岛上，用微细连接技术(微米级)将芯片和外引线脚连接起来，然后用高分子材料或陶瓷材料将芯片和引线等保护起来，并形成一定的形状，成为可供用户使用的集成电路产品。
集成电路的封装类型可以概括为两大类：密封陶瓷封装以及塑料封装。密封陶瓷封装是利用真空密封装置将芯片与环绕的包围物隔离的方式封装，典型的密封陶瓷封装应用于高效能的封装等级。而塑料封装芯片则是利用环氧基树脂将芯片封装，虽然其难以完全与环境隔离，因此周边的空气可能穿过此封装，并在工艺中会对芯片的质量产生不良的影响，但近年来塑料封装技术在其应用和功效上得到了显著的发展，完全能够满足绝大部分工业、民用产品，材料成本低且塑料封装的生产工艺能够进行自动化生产，从而有效地降低了成本。
现在集成电路的封装形式主要有DIP、SOP、SSOP、TSSOP、MSOP、QFP、PLCC、QFN、DFN等。SOP、SSOP、TSSOP、MSOP等等封装结构由于体积小、频率特性较好、内阻较低、材料用量少、生产自动化程度高，而且整机企业使用时易于自动化作业，生产效率高、成本低，所以是绝大部分工业、民用产品采用的封装形式。
集成电路的封装形式对集成电路产品的性能、可靠性、成本具有重大作用。随着芯片制造技术从微米向纳米级发展，单位面积芯片功能每18个月翻番的摩尔定律在逐渐失效，未来功能强大的云计算、互联网中的物联网和移动网等等必须依赖其核心技术集成电路的突破，集成电路的大容量、高速度、低功耗的提高，在芯片制造上将变得越来越难，更大程度上需要封装形式及技术的突破。原来集成电路芯片制造技术的特征尺寸是微米级，甚至更宽，所以芯片的面积普遍较大，为了容纳下较大的芯片面积，导致封装结构尺寸很大，不但消耗很多原材料、封装生产效率低、功耗大、频率低、集成电路焊接在印刷线路板上需要占用较大的面积、成本较高；同时为了满足各种成品的尺寸要求，设计了接近的SOP、SSOP、TSSOP、MSOP等等多种封装结构；并且用现在的封装结构封装当今的小尺寸芯片的产品，由于引线比较长，频率特性下降、内阻明显增加、功耗及热耗大、产品寿命下降。随着芯片制造技术从微米级向亚微米，甚至纳米级(16纳米已经成熟，可以规模化生产)推进，芯片面积以几何级数减小，同时，对芯片的功耗、频率特性等提出了更高的要求，对封装结构也提出了更高的要求。
发明内容
为了适用芯片制造技术从微米级向亚微米，甚至纳米级的发展的需要，克服现有技术中的封装结构在电路体积大、产品电热性能差，严重影响产品可靠性、频率特性下降、制造成本高等方面的不足，本发明的目的在于提供一种高密度集成电路封装结构以及集成电路。
为了实现上述发明目的，本发明采用了以下技术方案：
一种高密度集成电路封装结构，包括：金属引线框，所述金属引线框包括引线框基岛、内引脚线和外引脚线；固定在引线框基岛上的芯片；以及芯片和内引脚线之间的微米级连接线；和密封所述金属引线框、芯片以及微米级连接线的长方体塑封结构，其特征在于：所述塑封结构的长度A1满足关系：1.20mm+(B-8)×0.30mm/2≤A1≤4.50mm+(B-8)×1.00mm/2；塑封结构的宽度A2满足关系：1.20mm≤A2≤3.50mm；塑封结构的厚度A3满足关系：A3≥0.35mm；B为外引脚线的个数，且为满足4≤B≤68的整数。
作为优选地，外引脚线的跨度B1满足2.30mm≤B1≤5.20mm；外引脚线的间距B2满足0.30mm≤B2≤1.00mm。
作为优选地，所述塑封结构的长度A1满足以下关系：A1＝2.50+(B-8)×0.53/2mm；塑封结构的宽度A2为2.60mm；塑封结构的厚度A3为0.85mm；外引脚线的跨度B1为4.00mm；外引脚线的宽度为0.20mm～0.23mm、引脚线中心间距B2为0.53mm。作为示例性地例子，外引脚线的个数可以为6、8、10、12、14、16、18、20、24个，并且塑封结构的长度A1分别为2.05mm、2.60mm、3.00mm、3.60mm、4.05mm、4.60mm、5.10mm、5.60mm、6.60mm。
作为优选地，所述封装结构中，在长方体塑封结构的底部还开设有应力释放槽，该应力释放槽的深度和宽度均为0.05mm，并且所述应力释放槽为螺旋形槽体。因为集成电路封装结构包括塑封树脂、金属引线框、硅芯片等不同的材料，由于使用的材料性质差异很大，热膨胀系数不一样，组合在一起时就会产生应力。该应力不仅会使不同材料间产生离层，影响产品可靠性，还会使芯片产生弯曲，硅晶格扭曲大量的模拟实验表明，对于本发明的封装结构，设置如上所述的螺旋形槽体，与常规形状的应力释放槽(例如常规的网状应力释放槽)能够避免集成电路使用时温度变化以及外力作用应力矢量的叠加，从而能够有效避免硅晶格的扭曲，最大幅度的避免了应力对集成电路性能的影响。
作为优选地，为了改善集成电路的导热性能，本发明对封装结构的内部位置关系等做了进一步的改进。设计的基岛到内引脚顶端的距离为0.150mm；基岛下沉距离为0.152mm；内引脚线长度为0.400mm。通过上述设计以及合理布线，可以很好地改善了电容、电感、电阻等参数降低集成电路体内温度，进一步提高集成电路使用寿命和可靠性。
本发明的第二方面还涉及上述高密度集成电路封装结构的封装方法。
所述封装方法包括以下步骤：
提供一金属引线框，所述金属引线框包括引线框基岛、内引脚线和外引脚线；
提供一芯片，并将所述芯片粘结于所述引线框基岛上；所述芯片和内引脚线之间通过微米级连接线电性连接；
通过注塑方法形成用于密封所述金属引线框和所述芯片的长方体塑封结构。
本发明的第三方面还涉及一种集成电路。所述集成电路通过设置多个本发明上述的高密度集成电路封装结构形成。
与现有技术相比，本发明所述的高密度集成电路封装结构具有以下有益效果：
(1)内阻大大减小，改善了封装结构的电性能和热性能，而且还可以节约一半左右的金属资源和成本。
(2)缩短了电信号的传输距离，减少信号传输的延迟时间和寄生参数，大大改善频率特性。
(3)封装效率更高、封装成本较低；节省总封装材料成本约45％，由于结构的改进，生产效率可以大大提高，整体生产效率可以提高35％左右，最高的工序，如切筋、注塑工序是原来的2倍以上；可以为整机厂家减少该集成电路占有印刷线路板的面积，可减少净面积75％。
(4)可以兼容多种封装结构，如SOP、TSSOP、SSOP、MSOP及部分QFN、DFN,满足日益发展的便携式产品的需求。
附图说明
图1为本发明一个实施例的引线框基岛的结构示意图。
具体实施方式
以下将结合具体实施例对本发明所述的高密度集成电路封装结构以及集成电路做进一步的阐述，以帮助本领域的技术人员对本发明的发明构思、技术方案有更完整、准确和深入的理解。
实施例1
如图1所示，本实施例所述的高密度集成电路封装结构包括金属引线框，金属引线框包括引线框基岛1、内引脚线2和外引脚线3；固定在引线框基岛上的芯片，以及芯片和内引脚线之间的微米级连接线；和密封金属引线框、芯片以及微米级连接线的长方体塑封结构；所述内引脚线和外引脚线相连接，在实施中，引脚线和外引脚线之间也可以通过银合金镀层连接。所述塑封结构的长度A1满足关系：1.20mm+(B-8)×0.30mm/2≤A1≤4.50mm+(B-8)×1.00mm/2；塑封结构的宽度A2满足关系：1.20mm≤A2≤3.50mm；塑封结构的厚度A3满足关系：A3≥0.35mm；B为外引脚线的个数，B为满足4≤B≤68的整数。以下将以外引线脚的个数为8的封装结构为例，对本发明的高密度集成电路封装结构做进一步的阐述。本发明的封装结构被本发明称之为CPC系列封装结构，即CPC4、CPC6、CPC8…………等。下面为了表述方便，本发明以CPC8代表本发明的外引线脚的个数为8的封装结构。
在本实施例中，所述塑封结构采用环氧树脂组合物封装而成，作为优选地所述环氧树脂组合物由双酚F型环氧树脂(DGEBF)、苯乙烯-马来酸酐共聚物(SMA1000)、聚乙醇二缩水甘油醚、聚丙二醇聚四氢呋喃端羟基聚酯、聚丁烯基琥珀酰亚胺、白炭黑、硅烷偶联剂和脱模剂。作为优选地，所述环氧树脂组合物由25～27.5wt％的苯乙烯-马来酸酐共聚物(SMA1000)、28～30wt％的熔融硅石、10～12wt％的聚丙二醇聚四氢呋喃端羟基聚酯、5.5～6.0wt％的白炭黑、3.5～4.0wt％的聚乙醇二缩水甘油醚、1.5～2.0wt％的聚丁烯基琥珀酰亚胺、0.5～0.8wt％的硅烷偶联剂、脱模剂，和余量的双酚F型环氧树脂(DGEBF)组成。在本实施例中所述双酚F型环氧树脂的环氧当量为171～175，25℃时的黏度为4000～6000mPa·s。所述白炭黑的比面积为100～300m2/g，粒径为10～50nm。熔融硅石的颗粒尺寸优选为1～50μm。所述硅烷偶联剂优选为γ-缩水甘油醚氧丙基三甲氧基硅烷、γ-甲基丙烯酰氧基丙基三甲氧基硅烷、γ-甲基丙烯酰氧基丙基三乙氧基硅烷或γ-甲基丙烯酰氧基甲基二甲氧基硅烷中的至少一种。所述脱模剂可选择有机硅系脱模剂或硬脂酸金属盐。在本实施例中通过添加聚丙二醇聚四氢呋喃端羟基聚酯和聚丁烯基琥珀酰亚胺出人意料的改善了抗回焊性和耐潮湿性，而且固化后的封装结构模量较小，能够有效吸收界面形变而产生的应力，基本没有观察到芯片分层和内部龟裂的情形，封装效果好。
在本实施例中，所述微米级连接线为直径为10～25μm的合金线，所述铜合金中含有2.50～3.05wt％的Ag、0.08～0.10wt％的In、0.05～0.06wt％的Ge、0.01～0.02wt％的Nb、0.003～0.005wt％的Zr和余量的Cu。所述微米级连接线可通过常规的铸锭、连铸、粗拔、退火、精拔、退火处理工艺制备得到，并且所述铜合金线表面上镀覆有银保护层，该微米连接线具有优异的抗氧化性能，有利于缩短焊接间距，特别适合于本发明所述的高密度、多引脚的集成电路封装。所述微米级连接线与芯片，以及所述微米级连接线与内引脚线之间通过软钎焊电性连接。软钎焊使用无铅钎料，并且所述无铅钎料含有3.2～3.6wt％的In、1.3～1.5wt％的Ag、0.5～0.6wt％的Bi、0.25～0.30wt％的Cu、0.10～0.15wt％的Ge，和余量的Sn。所述无铅钎料的熔化温度为201～206℃，其可焊性与可靠性好，抗剪切强度大于35.5MPa，电导率为10.2～10.5％IACS，适合于本发明所述的高密度、多引脚的集成电路封装。另外，微米级连接线采用纯铜线，微米级连接线与芯片，以及所述微米级连接线与内引脚线之间在高温情况下，也能通过原子吸引结合。进一步的，引脚线与PCB之间可以通过软钎焊电性连接；软钎焊使用无铅钎料，并且所述无铅钎料含有3.2～3.6wt％的In、1.3～1.5wt％的Ag、0.5～0.6wt％的Bi、0.25～0.30wt％的Cu、0.10～0.15wt％的Ge，和余量的Sn。
塑封体宽度的确定：
通过对减小封装内阻的专门研究，本发明得知，引线框基岛到引线脚间距为0.15mm以内时，电性能明显改善，生产效率、生产合格率、成本等综合效果较好。根据可靠性研究得知塑封体宽度为2.60mm左右时，可靠性、电性能、通用性等综合性能较好。现有技术中的芯片生产技术，针对这种封装形式的芯片，制造工艺一般在0.6微米以下，所产出的芯片尺寸通常在0.5×0.5mm2～1.5×1.8mm2之间，这就要求引线框的基岛尺寸为≤1.5×1.8mm2之间。基岛的边缘到内引线顶端的间距取决于材料厚度、刀具材料和加工精度，目前的技术要求达到0.10以上，考虑效率、刀具寿命后最合理的间距为0.15mm左右。内引线顶端到塑封体边缘的距离应为0.20～0.40mm，由引线脚的强度和可靠性决定。所以，如果只考虑产品的通用性的情况下，塑封体宽度应大于2.0mm。如果只考虑引线框生产技术，最小基岛为0.762×0.762mm2，塑封体宽度只需1.40mm，这样可以满足约40％左右的产品，比2.60mm塑封体宽度，塑封树脂可以减少15％，占总材料成本的1.0％，考虑投资成本，标准化应用需求，单独开发封装结构是不可取的。同样，将宽度增加到3.5mm，成本将增加约7.0％，生产效率下降，性能和通用性等其它特性没有改善，不应考虑。综上所述，塑封体宽度应为2.60mm。宽度在1.4mm到3.5mm之间的其它宽度与宽度为2.60mm比较，综合成本提高但没有本质差别，品质没有任何改善，所以不可取，但同样应该属于本发明保护范围。
塑封体长度的确定：
为减少集成电路在印刷线路板上占有的空间、减轻集成电路的重量、减少集成电路封装材料、提高集成电路生产时的效率(注：集成电路越短，用来排列集成电路的引线框就可以容纳更多的产品，生产效率就越高)、降低成本，设计集成电路塑封体时要尽量减少它的长度，塑封体越短越好。考虑到整机厂的应用中PCB板的制造，线宽在0.20mm以上、间距在0.30mm以上时，生产成本最低、效率最高、品质稳定，所以引线脚间距为0.50mm以上，考虑到电性能、机械加工要求，引线脚宽度为0.20mm～0.23mm，相应PCB板线宽以0.22～0.23较好，即引线脚间距为0.53mm是效率和综合成本最好的。小于以上尺寸的品质会下降，效率会降低，PCB板成本大幅度提高；所以封装和整机厂使用的综合成本反而提高，从封装成本与整机厂使用成本来考虑，引线脚间距确定为0.53mm。脚间距0.35mm到0.53mm之间没有改善性能，但综合成本反而提升，脚间距0.53mm到1.00mm之间，成本提高，性能没有改善。综上所述，引线脚间距确定为0.53mm。间距为0.35mm到1.00mm之间的其它尺寸，虽然可行，品质在规范内，成本提高，应该属于本发明保护范围。其相应的塑封体长度确定为2.60mm，塑封体长度从1.20mm到4.50mm之间的其它尺寸，同样应该属于本发明保护范围。
塑封体厚度的确定：
为满足终端产品轻、薄化要求，应该越薄越好；从减少塑封料用量考虑，塑封体也是越薄越好。考虑到芯片的厚度一般为0.19mm以上，芯片表面到塑封体表面距离考虑焊线的安全高度在0.2mm，基岛底面到塑封体底面的高度为0.2mm以上，引线框厚度为0.11mm以上，因此塑封体的厚度应大于0.70mm以上。但考虑到芯片减薄成本、线弧控制难易程度对品质的影响、电阻和强度对引线框厚度的要求、引线脚成型时产生的应力、塑封材料的气密性和通用性，本发明对成本和品质综合考虑后确定厚度为0.85mm。厚度0.35mm～0.85mm，生产难度增加，综合成本提高；厚度大于0.85mm以上,则用料增加，成本明显提高。综上所述，厚度确定为0.85mm。厚度在0.35mm以上的其它尺寸虽然可行，与这一尺寸相比，优点没有明显差异，综合效果较差，应该属于本发明保护范围。
塑封体高度方向的角度及棱角：
一般不作研究，由模具企业根据脱模需求和外观美观确定。
在长方体塑封结构的底部还开设有应力释放槽，该应力释放槽的深度和宽度均为0.05mm，该应力释放槽的长度和长方体塑封结构的宽度相等，并且所述应力释放槽为螺旋形槽体。在所述螺旋形槽体内填充有聚丁烯基琥珀酰亚胺和氨基聚酰胺树脂的组合物，并在40-50℃固化处理3.0-5.0min，其中：聚丁烯基琥珀酰亚胺和氨基聚酰胺树脂的质量比为3:1。因为集成电路封装结构包括塑封树脂、金属引线框、硅芯片等不同的材料，由于使用的材料性质差异很大，热膨胀系数不一样，组合在一起时就会产生应力。该应力不仅会使不同材料间产生离层，影响产品可靠性，还会使芯片产生弯曲，硅晶格扭曲大量的模拟实验表明，对于本发明的封装结构，设置如上所述的结构，与常规形状的应力释放槽(例如常规的网状应力释放槽)能够避免集成电路使用时温度变化以及外力作用应力矢量的叠加，而且能够使得应力向无方向性耗散，从而能够有效避免硅晶格的扭曲，最大幅度的避免了应力对集成电路性能的影响。
现有技术中的SOP、TSSOP、SSOP、MSOP封装形式与本实施例的产品CPC8最为接近，可以看成是最为接近的现有技术。
本发明中其它引线脚产品，在具体推出时，我司会综合考虑电性能、热性能、功耗、可靠性及生产效率、品质等情况，在本发明范围内选择最优的具体结构尺寸。
CPC8相比现有SOP8，具有以下优点：
一、品质优势
1.可靠性明显改善
本发明提出的应力槽理论、基岛表面结构、短流道结构很好地解决了外形变形、不同物质间的分层、芯片变形、塑封体与不同物质间的结合、塑封体的分子结构、以及注塑过程中流体对微连线的损坏等等，产品可靠性提高，品质得以保障。应力释放槽为螺旋形槽体，可将螺纹形的结构特性极佳的应用到应力的力学设计中。
2.电、热性能、频率特性明显改善，满足线宽日益缩小的芯片要求
缩短微米级连线、缩短引线脚，封装内阻及热阻明显下降，改善了电热性能及频率特性，也提高了可靠性。
二、成本优势明显
1.SOP8的塑封体体积是：长4.9mm*宽3.9mm*厚1.5mm＝28.7mm3，本发明以8脚的为例子，CPC8的塑封体尺寸是长2.60mm*宽2.60mm*厚0.85mm＝5.746mm3，可节省塑封树脂为80％,全中国年生产量500亿只以上产品，可节省人民币为：500*0.008*0.80(每只树脂成本价)＝3.20亿元。
2.SOP8的金属引线框平面展开体积是：(宽7.8mm*长4.9mm*厚0.203)＝7.76mm3,CPC8的金属引线框的平面展开体积是：(5.00mm*2.60mm*0.154mm)＝2.00mm3,可以节省金属材料74％，全中国年生产量500亿只以上产品，铜的价格每公斤50元，铜的密度为8.93，则可节省人民币为：500*(7.76-2.13)*8.93/1000/1000*50＝1.26亿元。
3.可以减少电镀面积，从而减少用锡量，减少包装、运输成本，由于引线框密度大幅提高，生产综合效率可以提高35％以上。
综上所述，本发明所发明产品的应用将为人类节省大量宝贵资源，为生产和使用企业节省能耗、提高效率、创造效益，为终端用户节约支出。每年仅本产品成本即可节省价值达到人民币5亿元以上。本发明首期推出的产品为CPC8、CPC12、CPC14、CPC16、CPC20、CPC24六款(目前用量最大的六款产品)，即可节省人民币10亿元以上。推出本发明的所有系列产品，每年将为人类节省数十亿元人民币。
三、其它优点
1.由于体积的微型化，占用整机印刷线路板的空间小了，使整机体积可以做得更小；同样大小的印刷线路板可以容纳更多的电子元件，使相同体积的整机功能更强。
2.由于体积微型化，产品的重量变轻，可以使焊接有集成电路印刷线路板的重量变轻。
综上所述，采用本发明封装的产品不仅经济效益明显，产品品质、功能、产业链效率及效益等等都有很大改善。
CPC8和TSSOP8、SSOP、MSOP8、部分QFN、DFN相比：
一、品质优势
1.可靠性明显改善
本发明提出的应力槽理论、基岛表面结构、短流道结构很好地解决了外形变形、不同物质间的分层、芯片变形、塑封体与不同物质间的结合、塑封体的分子结构、以及注塑过程中流体对微连线的损坏等等，产品可靠性提高，品质得以保障。
2.电、热性能、频率特性有明显改善
缩短微米级连线、缩短引线脚，封装内阻及热阻明显下降，改善了电性能，也提高了可靠性。
二、成本等其它优势
1.铜、树脂、锡材料较大幅度减少。
2.生产效率明显提升。
3.适用范围更广。
4.相比QFN、DFN生产难度下降，材料制造成本下降更明显。
综上所述，有些本来只能使用以上对照的封装产品，采用本发明的封装形式，具有较高的经济效益。
现代社会人工成本高涨，资源匮乏，原材料价格越来越贵，低碳是社会趋势也是社会的必然。本发明的发明满足了时代的要求，节省了宝贵的自然资源和人力资源，符合低碳、绿色的社会发展要求。
对于本领域的普通技术人员而言，具体实施例只是对本发明进行了示例性描述，显然本发明具体实现并不受上述方式的限制，只要采用了本发明的方法构思和技术方案进行的各种非实质性的改进，或未经改进将本发明的构思和技术方案直接应用于其它场合的，均在本发明的保护范围之内。

Claims (6)

1.高密度集成电路封装结构，包括：金属引线框，所述金属引线框包括引线框基岛、内引脚线和外引脚线；固定在引线框基岛上的芯片；以及芯片和内引脚线之间的微米级连接线；和密封所述金属引线框、芯片以及微米级连接线的长方体塑封结构，其特征在于：所述塑封结构的长度A1满足关系：1.20mm+(B-8)×0.3mm/2≤A1≤4.50mm+(B-8)×1.00mm/2；塑封结构的宽度A2满足关系：1.20mm≤A2≤3.50mm；塑封结构的厚度A3满足关系：0.35mm≤A3≤0.85mm；B为外引脚线的个数，且为满足4≤B≤68的整数；所述微米级连接线为直径为10～25微米的合金线，所述微米级连接线与芯片之间通过软钎焊电性连接；所述微米级连接线与内引脚线之间通过软钎焊电性连接；软钎焊材料使用无铅钎料，并且所述无铅钎料含有3.2～3.6wt％的In、1.3～1.5wt％的Ag、0.5～0.6wt％的Bi、0.25～0.30wt％的Cu、0.10～0.15wt％的Ge，和余量的Sn；所述塑封结构采用环氧树脂组合物封装而成，所述环氧树脂组合物由双酚F型环氧树脂、苯乙烯-马来酸酐共聚物、聚乙醇二缩水甘油醚、聚丙二醇聚四氢呋喃端羟基聚酯、聚丁烯基琥珀酰亚胺、白炭黑、硅烷偶联剂和脱模剂组成，所述塑封结构的底部开设有应力释放槽，所述应力释放槽为螺旋形槽体，在所述螺旋形槽体内填充有聚丁烯基琥珀酰亚胺和氨基聚酰胺树脂的组合物，并在40-50℃固化处理3.0-5.0min，其中：聚丁烯基琥珀酰亚胺和氨基聚酰胺树脂的质量比为3:1。
2.根据权利要求1所述的高密度集成电路封装结构，其特征在于：所述外引脚线的跨度B1满足2.30mm≤B1≤5.20mm；外引脚线的间距B2满足0.30mm≤B2≤1.00mm。
3.根据权利要求1所述的高密度集成电路封装结构，其特征在于：所述塑封结构的长度A1满足以下关系：A1＝2.50+(B-8)×0.53/2mm；塑封结构的宽度A2为2.60mm；塑封结构的厚度A3为0.85mm；外引脚线的跨度B1为4.00mm；外引脚线的宽度为0.20mm～0.23mm、引脚线中心间距B2为0.53mm。
4.根据权利要求1所述的高密度集成电路封装结构，其特征在于：该应力释放槽的深度和宽度均为0.05mm。
5.根据权利要求1所述的高密度集成电路封装结构，其特征在于：所述引线框基岛到内引脚顶端的距离为0.150mm；基岛下沉距离为0.152mm；内引脚线长度为0.400mm。
6.根据权利要求1-5任一项所述的高密度集成电路封装结构的封装方法，其特征在于：包括以下步骤：提供一金属引线框，所述金属引线框包括引线框基岛、内引脚线和外引脚线；提供一芯片，并将所述芯片粘结于所述引线框基岛上；所述芯片和内引脚线之间通过微米级连接线电性连接；通过注塑方法形成用于密封所述金属引线框和所述芯片的长方体塑封结构。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6495399B1 (en) * 1999-11-01 2002-12-17 Chartered Semiconductor Manufacturing Ltd. Method of vacuum packaging a semiconductor device assembly
CN102361025A (zh) * 2011-10-28 2012-02-22 深圳市气派科技有限公司 一种高密度集成电路封装结构、封装方法以及集成电路

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58169948A (ja) * 1982-03-30 1983-10-06 Fujitsu Ltd 樹脂封止型半導体装置
TW366576B (en) * 1997-08-06 1999-08-11 Apack Technologies Inc Flip chip joint lead frame packaging method for ICs and the devices
TW459315B (en) * 1999-04-06 2001-10-11 Walsin Advanced Electronics Stack-up chip packaging
CN100416815C (zh) * 2003-02-21 2008-09-03 先进互连技术有限公司 包括无源器件的引线框架及其形成方法
TWI249830B (en) * 2004-02-23 2006-02-21 Advanced Semiconductor Eng Leadless semiconductor package and manufacturing method thereof
US7518221B2 (en) * 2006-01-26 2009-04-14 International Business Machines Corporation Apparatus and methods for packaging integrated circuit chips with antennas formed from package lead wires
TWI329917B (en) * 2006-04-04 2010-09-01 Chipmos Technologies Inc Semiconductor chip having fine pitch bumps and bumps thereof
JP2008115373A (ja) * 2006-10-12 2008-05-22 Hitachi Chem Co Ltd 樹脂組成物の流れ率の測定方法、封止用エポキシ樹脂組成物及び電子部品装置
CN102985486A (zh) * 2010-10-01 2013-03-20 富士电机株式会社 树脂组合物
US8836136B2 (en) * 2011-10-17 2014-09-16 Invensas Corporation Package-on-package assembly with wire bond vias
CN202259275U (zh) * 2011-10-28 2012-05-30 深圳市气派科技有限公司 16引脚高密度集成电路封装结构
CN103243234B (zh) * 2013-04-27 2015-08-26 深圳市同方电子新材料有限公司 一种电子封装软钎焊用系列低银无铅钎料及其制备方法
CN104979303B (zh) * 2015-07-08 2018-12-04 气派科技股份有限公司 一种高密度集成电路封装结构
CN105514057B (zh) * 2016-01-15 2017-03-29 气派科技股份有限公司 高密度集成电路封装结构以及集成电路

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6495399B1 (en) * 1999-11-01 2002-12-17 Chartered Semiconductor Manufacturing Ltd. Method of vacuum packaging a semiconductor device assembly
CN102361025A (zh) * 2011-10-28 2012-02-22 深圳市气派科技有限公司 一种高密度集成电路封装结构、封装方法以及集成电路

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