WO2017121336A1 - 高密度集成电路封装结构以及集成电路 - Google Patents

高密度集成电路封装结构以及集成电路 Download PDF

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Publication number
WO2017121336A1
WO2017121336A1 PCT/CN2017/070874 CN2017070874W WO2017121336A1 WO 2017121336 A1 WO2017121336 A1 WO 2017121336A1 CN 2017070874 W CN2017070874 W CN 2017070874W WO 2017121336 A1 WO2017121336 A1 WO 2017121336A1
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integrated circuit
package structure
chip
line
circuit package
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PCT/CN2017/070874
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English (en)
French (fr)
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梁大钟
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气派科技股份有限公司
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Definitions

  • the present invention relates to the field of integrated circuit packages, and more particularly to a high density integrated circuit package structure and an integrated circuit having the package structure.
  • Integrated circuits are the core of modern technology and the basis of modern science and technology development. Scientific research must rely on integrated circuits with integrated circuits as the core. In addition, it is the foundation of modern human civilization and fundamentally changes the modern civilization of people's lifestyles. Such as the Internet of Things, the Internet, computers, televisions, refrigerators, mobile phones, IPAD, IPHONE, various automatic control devices, etc. rely on integrated circuits to achieve their intelligent functions.
  • the manufacturing sub-design of integrated circuits, wafer fabrication, packaging, and testing are the main components.
  • Packaging is a key link.
  • the packaging form based on packaging technology is to meet the performance, volume, reliability of integrated circuits for various purposes. Developed with special requirements for shape and cost.
  • Integrated circuit package refers to the separation of integrated circuit wafer into a single chip that meets the requirements by using the grinding and cutting technology that can ensure the perfect lattice structure of the single crystal material, and fixes the chip to the lead frame base by conductive glue or eutectic technology.
  • the chip and the outer lead are connected by micro-connection technology (micron level), and then the chip and the lead are protected by a polymer material or a ceramic material, and form a certain shape to become an integrated circuit for the user to use. product.
  • the package types of integrated circuits can be summarized into two broad categories: sealed ceramic packages and plastic packages.
  • Sealed ceramic packages are packaged in a vacuum-sealed manner to isolate the chip from the surrounding enclosure.
  • Typical sealed ceramic packages are used in high-performance package grades.
  • the plastic packaged chip uses an epoxy resin to encapsulate the chip. Although it is difficult to completely isolate it from the environment, the surrounding air may pass through the package and adversely affect the quality of the chip in the process.
  • the plastic packaging technology has been significantly developed in its application and efficacy, and can fully satisfy most industrial and civil products. The material cost is low and the plastic packaging production process can be automated, thus effectively reducing the cost.
  • the package form of integrated circuits mainly includes DIP, SOP, SSOP, TSSOP, MSOP, QFP, PLCC, QFN, DFN, and the like.
  • SOP, SSOP, TSSOP, MSOP and other package structures are small in size, good in frequency characteristics, low in internal resistance, low in material usage, high in production automation, and easy to automate when used by the whole machine, high production efficiency and cost Low, so it is the package form used by most industrial and civil products.
  • the package form of an integrated circuit plays a major role in the performance, reliability, and cost of integrated circuit products.
  • chip manufacturing technology moves from micron to nanoscale, Moore's Law, which doubles the chip function per unit area every 18 months, is gradually dying.
  • powerful cloud computing, Internet of Things and mobile networks in the Internet must rely on its core technology.
  • the breakthrough of integrated circuits the increase in the capacity, high speed and low power consumption of integrated circuits will become more and more difficult in chip manufacturing.
  • a breakthrough in packaging form and technology Originally, the feature size of integrated circuit chip manufacturing technology is micron-scale or even wider, so the area of the chip is generally large.
  • the package structure In order to accommodate a larger chip area, the package structure is large in size, which not only consumes a lot of raw materials, but also has low production efficiency. Large power consumption, low frequency, integrated circuit soldering on printed circuit boards need to occupy a large area, high cost; at the same time, in order to meet the size requirements of various finished products, design close SOP, SSOP, TSSOP, MSOP, etc.
  • SOP Small Specific Organization
  • SSOP Stylene oxide
  • TSSOP TSSOP
  • MSOP etc.
  • an object of the present invention is to provide a high-density integrated circuit package structure and an integrated circuit.
  • a high-density integrated circuit package structure comprising: a metal lead frame comprising a lead frame base island, an inner lead line and an outer lead line; a chip fixed on the base of the lead frame; and a chip and the inner a micron-sized connecting line between the pin lines; and a rectangular parallelepiped plastic sealing structure for sealing the metal lead frame, the chip and the micro-scale connecting line, wherein the length A1 of the plastic sealing structure satisfies the relationship: 1.20 mm+(B-8 ⁇ 0.30mm/2 ⁇ A1 ⁇ 4.50mm+(B-8) ⁇ 1.00mm/2; the width A2 of the plastic seal structure satisfies the relationship: 1.20mm ⁇ A2 ⁇ 3.50mm; the thickness A3 of the plastic seal structure satisfies the relationship: A3 ⁇ 0.35mm ; B is the number of outer pin lines, and is an integer satisfying 4 ⁇ B ⁇ 68.
  • the span B1 of the outer lead wire satisfies 2.30 mm ⁇ B1 ⁇ 5.20 mm; and the pitch B2 of the outer lead wire satisfies 0.30 mm ⁇ B2 ⁇ 1.00 mm.
  • the number of outer pin lines may be 6, 8, 10, 12, 14, 16, 18, 20, 24, and the length A1 of the plastic sealing structure is 2.05 mm, 2.60 mm, 3.00 mm, respectively. , 3.60mm, 4.05mm, 4.60mm, 5.10mm, 5.60mm, 6.60mm.
  • a stress relief groove is further formed at the bottom of the rectangular parallelepiped plastic structure, the stress relief groove has a depth and a width of 0.05 mm, and the stress relief groove is a spiral groove body.
  • the integrated circuit package structure includes different materials such as plastic sealing resin, metal lead frame, silicon chip, etc., the material properties used are very different, the thermal expansion coefficients are different, and stress is generated when combined. This stress not only causes separation between different materials, but also affects production. Product reliability, which also causes the chip to bend, the silicon lattice is distorted.
  • a spiral groove body as described above is provided, and a conventional shape stress relief groove (for example, a conventional mesh)
  • the stress relief groove can avoid the temperature variation of the integrated circuit and the superposition of the stress vector of the external force, so that the distortion of the silicon lattice can be effectively avoided, and the influence of the stress on the performance of the integrated circuit can be avoided to the maximum extent.
  • the present invention further improves the internal positional relationship of the package structure and the like.
  • the distance from the base of the design to the top of the inner pin is 0.150mm; the sinking distance of the base island is 0.152mm; the length of the inner lead wire is 0.400mm.
  • a second aspect of the invention also relates to a method of packaging the above high density integrated circuit package structure.
  • the packaging method includes the following steps:
  • Providing a metal lead frame including a lead frame base island, an inner lead line, and an outer lead line;
  • the chip and the inner pin line are electrically connected by a micron-level connecting line;
  • a rectangular parallelepiped plastic sealing structure for sealing the metal lead frame and the chip is formed by an injection molding method.
  • a third aspect of the invention also relates to an integrated circuit.
  • the integrated circuit is formed by providing a plurality of the high-density integrated circuit package structures of the present invention described above.
  • the high-density integrated circuit package structure of the present invention has the following beneficial effects:
  • FIG. 1 is a schematic structural view of a lead frame island according to an embodiment of the present invention.
  • the high-density integrated circuit package structure of this embodiment includes a metal lead frame including a lead frame island 1, an inner pin line 2, and an outer lead line 3; a chip on the island, and a micron-sized connection line between the chip and the inner pin line; and a rectangular parallelepiped plastic structure for sealing the metal lead frame, the chip, and the micro-scale connection line; the inner pin line and the outer pin line are connected
  • the pin line and the outer pin line can also be connected by a silver alloy plating.
  • the length A1 of the plastic sealing structure satisfies the relationship: 1.20 mm+(B-8) ⁇ 0.30 mm/2 ⁇ A1 ⁇ 4.50 mm+(B-8) ⁇ 1.00 mm/2; the width A2 of the plastic sealing structure satisfies the relationship: 1.20 mm ⁇ A2 ⁇ 3.50mm; the thickness A3 of the plastic sealing structure satisfies the relationship: A3 ⁇ 0.35mm; B is the number of outer pin lines, and B is an integer satisfying 4 ⁇ B ⁇ 68.
  • the high-density integrated circuit package structure of the present invention will be further described by taking a package structure having 8 outer lead pins as an example.
  • the package structure of the present invention is referred to as a CPC series package structure in the present invention, namely, CPC4, CPC6, CPC8, etc.
  • the present invention represents a package structure in which the number of outer lead pins of the present invention is 8 by CPC8.
  • the plastic sealing structure is encapsulated by an epoxy resin composition
  • the epoxy resin composition is composed of a bisphenol F type epoxy resin (DGEBF), a styrene-maleic anhydride copolymer. (SMA1000), polyglycol diglycidyl ether, polypropylene glycol polytetrahydrofuran hydroxyl terminated polyester, polybutenyl succinimide, white carbon black, silane coupling agent and mold release agent.
  • DGEBF bisphenol F type epoxy resin
  • SMA1000 styrene-maleic anhydride copolymer
  • polyglycol diglycidyl ether polypropylene glycol polytetrahydrofuran hydroxyl terminated polyester
  • polybutenyl succinimide polybutenyl succinimide
  • white carbon black silane coupling agent and mold release agent.
  • the epoxy resin composition comprises from 25 to 27.5% by weight of a styrene-maleic anhydride copolymer (SMA1000), 28 to 30% by weight of fused silica, and 10 to 12% by weight of a polypropylene glycol polytetrahydrofuran terminal hydroxyl group.
  • SMA1000 styrene-maleic anhydride copolymer
  • Ester 5.5 to 6.0 wt% of silica, 3.5 to 4.0 wt% of polyglycol diglycidyl ether, 1.5 to 2.0 wt% of polybutenyl succinimide, 0.5 to 0.8 wt% of silane coupling agent , a release agent, and the balance of bisphenol F-type epoxy resin (DGEBF).
  • DGEBF bisphenol F-type epoxy resin
  • the bisphenol F type epoxy resin has an epoxy equivalent of 171 to 175 and a viscosity at 25 ° C of 4000 to 6000 mPa ⁇ s.
  • the white carbon has a specific area of 100 to 300 m 2 /g and a particle diameter of 10 to 50 nm.
  • the particle size of the fused silica is preferably from 1 to 50 ⁇ m.
  • the silane coupling agent is preferably ⁇ -glycidyloxypropyltrimethoxysilane, ⁇ -methacryloxypropyltrimethoxysilane, ⁇ -methacryloxypropyltriethoxylate At least one of silane or ⁇ -methacryloxymethyldimethoxysilane.
  • the release agent may be selected from a silicone release agent or a stearic acid metal salt.
  • the addition of polypropylene glycol polytetrahydrofuran-terminated hydroxyl polyester and polybutenyl succinimide unexpectedly improves the reflow resistance and moisture resistance, and the package structure modulus after curing is small and can be effective. Absorbing the stress generated by the deformation of the interface, substantially no chip delamination and internal cracking were observed, and the encapsulation effect was good.
  • the micron-sized connecting wire is an alloy wire having a diameter of 10 to 25 ⁇ m, and the copper alloy contains 2.50 to 3.05 wt% of Ag, 0.08 to 0.10 wt% of In, and 0.05 to 0.06 wt%. Ge, 0.01 to 0.02 wt% of Nb, 0.003 to 0.005 wt% of Zr, and the balance of Cu.
  • the micron-sized connecting wire can be passed through conventional ingot casting, continuous casting, rough drawing, annealing,
  • the surface of the copper alloy wire is plated with a silver protective layer, and the micro-joint wire has excellent oxidation resistance, is favorable for shortening the welding pitch, and is particularly suitable for the high degree described in the present invention.
  • the micro-scale connection line and the chip, and the micro-scale connection line and the inner lead line are electrically connected by soldering.
  • the lead-free solder is used for soldering, and the lead-free solder contains 3.2 to 3.6 wt% of In, 1.3 to 1.5 wt% of Ag, 0.5 to 0.6 wt% of Bi, 0.25 to 0.30 wt% of Cu, 0.10. ⁇ 0.15 wt% Ge, and the balance of Sn.
  • the lead-free solder has a melting temperature of 201 to 206 ° C, good solderability and reliability, a shear strength of more than 35.5 MPa, and an electric conductivity of 10.2 to 10.5% IACS, which is suitable for the high density of the present invention.
  • Multi-pin integrated circuit package the micron-sized connecting wires are made of pure copper wires, micron-sized connecting wires and chips, and the micron-sized connecting wires and the inner pin wires can also be bonded by atomic attraction at high temperatures.
  • the lead wire and the PCB may be electrically connected by soldering; the soldering uses a lead-free solder, and the lead-free solder contains 3.2 to 3.6 wt% of In, 1.3 to 1.5 wt%. Ag, 0.5 to 0.6 wt% of Bi, 0.25 to 0.30 wt% of Cu, 0.10 to 0.15 wt% of Ge, and the balance of Sn.
  • the invention knows that when the distance between the base of the lead frame and the lead pin is 0.15 mm, the electrical performance is obviously improved, and the comprehensive effects of production efficiency, production yield and cost are better. According to the reliability study, when the width of the plastic package is about 2.60 mm, the comprehensive performances such as reliability, electrical performance and versatility are better.
  • the chip production technology in the prior art, for the chip in the package form, the manufacturing process is generally below 0.6 micron, and the chip size produced is usually between 0.5 x 0.5 mm 2 and 1.5 x 1.8 mm 2 , which requires The base island size of the lead frame is between ⁇ 1.5 ⁇ 1.8 mm 2 .
  • the distance from the edge of the island to the top of the inner lead depends on the material thickness, tool material and processing accuracy. The current technical requirements are above 0.10. Considering the efficiency and the tool life, the most reasonable spacing is about 0.15mm.
  • the distance from the tip of the inner lead to the edge of the molded body should be 0.20 to 0.40 mm, which is determined by the strength and reliability of the lead pin. Therefore, if only the versatility of the product is considered, the width of the molded body should be greater than 2.0 mm.
  • the minimum base island is 0.762 ⁇ 0.762 mm 2
  • the width of the plastic package is only 1.40 mm, which can satisfy about 40% of the product, and the plastic resin can be reduced by 15% compared with the width of the 2.60 mm plastic package. Accounting for 1.0% of the total material cost, considering the investment cost, standardized application requirements, it is not advisable to develop the package structure separately. Similarly, increasing the width to 3.5 mm, the cost will increase by about 7.0%, the production efficiency will decrease, and other characteristics such as performance and versatility will not be improved and should not be considered. In summary, the width of the molded body should be 2.60 mm.
  • the lead frame used to arrange the integrated circuit can be To accommodate more products, the higher the production efficiency
  • reduce the cost design the integrated circuit plastic package to minimize its length Degree, the shorter the plastic body, the better.
  • the lead pitch is 0.50mm or more, considering the electrical properties.
  • the lead pin width is 0.20mm ⁇ 0.23mm, and the corresponding PCB board line width is preferably 0.22 ⁇ 0.23, that is, the lead pin pitch is 0.53mm, which is the best efficiency and comprehensive cost.
  • the quality of the smaller than the above size will decrease, the efficiency will decrease, and the cost of the PCB will be greatly increased. Therefore, the overall cost of the package and the whole plant will be increased.
  • the lead pitch is determined to be 0.53. Mm. There is no improvement in performance between 0.35mm and 0.53mm, but the overall cost is increased. The distance between the feet is between 0.53mm and 1.00mm. The cost is improved and the performance is not improved.
  • the lead pitch is determined to be 0.53 mm.
  • the corresponding length of the molded body is determined to be 2.60 mm, and other dimensions of the length of the molded body from 1.20 mm to 4.50 mm are also within the scope of the present invention.
  • the thinner the better, the thinner the better, the thinner the plastics In order to meet the requirements of lightness and thinning of the terminal products, the thinner the better, the thinner the plastics.
  • the thickness of the chip is generally 0.19 mm or more, the distance from the surface of the chip to the surface of the plastic body is considered to be 0.2 mm, the height of the bottom surface of the base island to the bottom surface of the plastic body is 0.2 mm or more, and the thickness of the lead frame is 0.11 mm or more. Therefore, the thickness of the molded body should be greater than 0.70 mm.
  • the thickness is determined to be 0.85 mm.
  • the thickness is 0.35mm ⁇ 0.85mm, the production difficulty is increased, and the comprehensive cost is increased.
  • the thickness is determined to be 0.85 mm.
  • a stress relief groove is further disposed at a bottom of the rectangular parallelepiped structure, the stress relief groove has a depth and a width of 0.05 mm, the length of the stress relief groove is equal to the width of the rectangular parallelepiped structure, and the stress relief groove is a spiral groove. body.
  • the spiral tank is filled with a composition of polybutenyl succinimide and an amino polyamide resin, and cured at 40-50 ° C for 3.0-5.0 min, wherein: polybutenyl succinimide and The mass ratio of the amino polyamide resin was 3:1. Because the integrated circuit package structure includes different materials such as plastic sealing resin, metal lead frame, silicon chip, etc., the material properties used are very different, the thermal expansion coefficients are different, and stress is generated when combined.
  • This stress not only causes separation between different materials, affects product reliability, but also causes the chip to bend, and the silicon lattice is distorted.
  • a large number of simulation experiments show that for the package structure of the present invention, the structure as described above is set, and conventional The shape of the stress relief groove (for example, the conventional mesh stress relief groove) can avoid the temperature variation of the integrated circuit and the superposition of the stress vector of the external force, and can make the stress to the square
  • the directional dissipation can effectively avoid the distortion of the silicon lattice, and the influence of stress on the performance of the integrated circuit is avoided to the utmost extent.
  • the SOP, TSSOP, SSOP, MSOP package form of the prior art is the closest to the product CPC8 of the present embodiment, and can be regarded as the closest prior art.
  • CPC8 has the following advantages over existing SOP8:
  • the stress groove theory, the island surface structure and the short flow channel structure proposed by the invention well solve the deformation of the shape, the delamination between different substances, the deformation of the chip, the combination of the plastic body and the different substances, the molecular structure of the plastic body, As well as damage to the micro-wiring of the fluid during the injection molding process, the reliability of the product is improved and the quality is guaranteed.
  • the stress relief groove is a spiral groove body, which can apply the thread-shaped structural characteristics to the mechanical design of stress.
  • the invention takes 8 feet as an example.
  • the application of the product of the invention will save a lot of valuable resources for human beings, save energy, improve efficiency, create benefits for production and use enterprises, and save expenditure for end users. Only the cost of this product can save more than RMB 500 million per year.
  • the products launched in the first phase of the invention are six kinds of CPC8, CPC12, CPC14, CPC16, CPC20 and CPC24 (the six products with the largest current consumption), which can save more than RMB 1 billion. The launch of all the products of the invention will save billions of dollars per year for humans.
  • the space occupied by the whole printed circuit board is small, so that the whole machine volume can be made smaller; the same size printed circuit board can accommodate more electronic components, so that the same volume of the whole machine function Stronger.
  • the weight of the product becomes lighter, and the weight of the printed circuit board with integrated circuits can be made lighter.
  • the products packaged by the invention not only have obvious economic benefits, but also greatly improve product quality, function, industrial chain efficiency and efficiency.
  • CPC8 Compared with TSSOP8, SSOP, MSOP8, partial QFN and DFN:
  • the stress groove theory, the island surface structure and the short flow channel structure proposed by the invention well solve the deformation of the shape, the delamination between different substances, the deformation of the chip, the combination of the plastic body and the different substances, the molecular structure of the plastic body, As well as damage to the micro-wiring of the fluid during the injection molding process, the reliability of the product is improved and the quality is guaranteed.
  • the invention of the invention satisfies the requirements of the times, saves valuable natural resources and human resources, and meets the requirements of low carbon and green social development.

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Abstract

一种高密度集成电路封装结构以及集成电路，所述的高密度集成电路封装结构，包括密封金属引线框、芯片以及微米级连接线的长方体塑封结构，所述塑封结构的长度A1满足关系：1.20 mm +（B-8）×0.3 mm /2≤A1≤4.50 mm +（B-8）×1.00 mm /2；塑封结构的宽度A2满足关系：1.20 mm≤A2≤3.50 mm；塑封结构的厚度A3满足关系：A3≥0.35mm；B为外引脚线的个数。

Description

高密度集成电路封装结构以及集成电路 技术领域
本发明涉及集成电路封装的技术领域，更具体地说，本发明涉及一种高密度集成电路封装结构以及具有该封装结构的集成电路。
背景技术
集成电路是现代技术的核心，也是现代科学技术发展的基础，科学研究都必须依赖以集成电路为核心的仪器设备；另外它还是人类现代文明的基础，从根本上改变人们生活方式的现代文明，如物联网、互联网、电脑、电视、冰箱、手机、IPAD、IPHONE、各种自动控制设备等等都依赖集成电路来实现其智能化功能的。
集成电路的制造分设计、圆片制造、封装、测试几个主要部分，封装是其中关键环节，建立在封装技术上的封装形式是为满足各种用途对集成电路的性能、体积、可靠性、形状和成本的特殊要求而研制的。
集成电路封装：是指通过使用能够保证单晶材料完美晶格结构的研磨、切割技术将集成电路圆片分离成符合要求的单一芯片，用导电胶或共晶等技术将芯片固定到引线框基岛上，用微细连接技术(微米级)将芯片和外引线脚连接起来，然后用高分子材料或陶瓷材料将芯片和引线等保护起来，并形成一定的形状，成为可供用户使用的集成电路产品。
集成电路的封装类型可以概括为两大类：密封陶瓷封装以及塑料封装。密封陶瓷封装是利用真空密封装置将芯片与环绕的包围物隔离的方式封装，典型的密封陶瓷封装应用于高效能的封装等级。而塑料封装芯片则是利用环氧基树脂将芯片封装，虽然其难以完全与环境隔离，因此周边的空气可能穿过此封装，并在工艺中会对芯片的质量产生不良的影响，但近年来塑料封装技术在其应用和功效上得到了显著的发展，完全能够满足绝大部分工业、民用产品，材料成本低且塑料封装的生产工艺能够进行自动化生产，从而有效地降低了成本。
现在集成电路的封装形式主要有DIP、SOP、SSOP、TSSOP、MSOP、QFP、PLCC、QFN、DFN等。SOP、SSOP、TSSOP、MSOP等等封装结构由于体积小、频率特性较好、内阻较低、材料用量少、生产自动化程度高，而且整机企业使用时易于自动化作业，生产效率高、成本低，所以是绝大部分工业、民用产品采用的封装形式。
集成电路的封装形式对集成电路产品的性能、可靠性、成本具有重大作用。随着芯片制造技术从微米向纳米级发展，单位面积芯片功能每18个月翻番的摩尔定律在逐渐失效，未来功能强大的云计算、互联网中的物联网和移动网等等必须依赖其核心技术集成电路的突破，集成电路的大容量、高速度、低功耗的提高，在芯片制造上将变得越来越难，更大程度上需 要封装形式及技术的突破。原来集成电路芯片制造技术的特征尺寸是微米级，甚至更宽，所以芯片的面积普遍较大，为了容纳下较大的芯片面积，导致封装结构尺寸很大，不但消耗很多原材料、封装生产效率低、功耗大、频率低、集成电路焊接在印刷线路板上需要占用较大的面积、成本较高；同时为了满足各种成品的尺寸要求，设计了接近的SOP、SSOP、TSSOP、MSOP等等多种封装结构；并且用现在的封装结构封装当今的小尺寸芯片的产品，由于引线比较长，频率特性下降、内阻明显增加、功耗及热耗大、产品寿命下降。随着芯片制造技术从微米级向亚微米，甚至纳米级(16纳米已经成熟，可以规模化生产)推进，芯片面积以几何级数减小，同时，对芯片的功耗、频率特性等提出了更高的要求，对封装结构也提出了更高的要求。
发明内容
为了适用芯片制造技术从微米级向亚微米，甚至纳米级的发展的需要，克服现有技术中的封装结构在电路体积大、产品电热性能差，严重影响产品可靠性、频率特性下降、制造成本高等方面的不足，本发明的目的在于提供一种高密度集成电路封装结构以及集成电路。
为了实现上述发明目的，本发明采用了以下技术方案：
一种高密度集成电路封装结构，包括：金属引线框，所述金属引线框包括引线框基岛、内引脚线和外引脚线；固定在引线框基岛上的芯片；以及芯片和内引脚线之间的微米级连接线；和密封所述金属引线框、芯片以及微米级连接线的长方体塑封结构，其特征在于：所述塑封结构的长度A1满足关系：1.20mm+(B-8)×0.30mm/2≤A1≤4.50mm+(B-8)×1.00mm/2；塑封结构的宽度A2满足关系：1.20mm≤A2≤3.50mm；塑封结构的厚度A3满足关系：A3≥0.35mm；B为外引脚线的个数，且为满足4≤B≤68的整数。
作为优选地，外引脚线的跨度B1满足2.30mm≤B1≤5.20mm；外引脚线的间距B2满足0.30mm≤B2≤1.00mm。
作为优选地，所述塑封结构的长度A1满足以下关系：A1＝2.50+(B-8)×0.53/2mm；塑封结构的宽度A2为2.60mm；塑封结构的厚度A3为0.85mm；外引脚线的跨度B1为4.00mm；外引脚线的宽度为0.20mm～0.23mm、引脚线中心间距B2为0.53mm。作为示例性地例子，外引脚线的个数可以为6、8、10、12、14、16、18、20、24个，并且塑封结构的长度A1分别为2.05mm、2.60mm、3.00mm、3.60mm、4.05mm、4.60mm、5.10mm、5.60mm、6.60mm。
作为优选地，所述封装结构中，在长方体塑封结构的底部还开设有应力释放槽，该应力释放槽的深度和宽度均为0.05mm，并且所述应力释放槽为螺旋形槽体。因为集成电路封装结构包括塑封树脂、金属引线框、硅芯片等不同的材料，由于使用的材料性质差异很大，热膨胀系数不一样，组合在一起时就会产生应力。该应力不仅会使不同材料间产生离层，影响产 品可靠性，还会使芯片产生弯曲，硅晶格扭曲大量的模拟实验表明，对于本发明的封装结构，设置如上所述的螺旋形槽体，与常规形状的应力释放槽(例如常规的网状应力释放槽)能够避免集成电路使用时温度变化以及外力作用应力矢量的叠加，从而能够有效避免硅晶格的扭曲，最大幅度的避免了应力对集成电路性能的影响。
作为优选地，为了改善集成电路的导热性能，本发明对封装结构的内部位置关系等做了进一步的改进。设计的基岛到内引脚顶端的距离为0.150mm；基岛下沉距离为0.152mm；内引脚线长度为0.400mm。通过上述设计以及合理布线，可以很好地改善了电容、电感、电阻等参数降低集成电路体内温度，进一步提高集成电路使用寿命和可靠性。
本发明的第二方面还涉及上述高密度集成电路封装结构的封装方法。
所述封装方法包括以下步骤：
提供一金属引线框，所述金属引线框包括引线框基岛、内引脚线和外引脚线；
提供一芯片，并将所述芯片粘结于所述引线框基岛上；所述芯片和内引脚线之间通过微米级连接线电性连接；
通过注塑方法形成用于密封所述金属引线框和所述芯片的长方体塑封结构。
本发明的第三方面还涉及一种集成电路。所述集成电路通过设置多个本发明上述的高密度集成电路封装结构形成。
与现有技术相比，本发明所述的高密度集成电路封装结构具有以下有益效果：
(1)内阻大大减小，改善了封装结构的电性能和热性能，而且还可以节约一半左右的金属资源和成本。
(2)缩短了电信号的传输距离，减少信号传输的延迟时间和寄生参数，大大改善频率特性。
(3)封装效率更高、封装成本较低；节省总封装材料成本约45％，由于结构的改进，生产效率可以大大提高，整体生产效率可以提高35％左右，最高的工序，如切筋、注塑工序是原来的2倍以上；可以为整机厂家减少该集成电路占有印刷线路板的面积，可减少净面积75％。
(4)可以兼容多种封装结构，如SOP、TSSOP、SSOP、MSOP及部分QFN、DFN,满足日益发展的便携式产品的需求。
附图说明
图1为本发明一个实施例的引线框基岛的结构示意图。
具体实施方式
以下将结合具体实施例对本发明所述的高密度集成电路封装结构以及集成电路做进一步 的阐述，以帮助本领域的技术人员对本发明的发明构思、技术方案有更完整、准确和深入的理解。
实施例1
如图1所示，本实施例所述的高密度集成电路封装结构包括金属引线框，金属引线框包括引线框基岛1、内引脚线2和外引脚线3；固定在引线框基岛上的芯片，以及芯片和内引脚线之间的微米级连接线；和密封金属引线框、芯片以及微米级连接线的长方体塑封结构；所述内引脚线和外引脚线相连接，在实施中，引脚线和外引脚线之间也可以通过银合金镀层连接。所述塑封结构的长度A1满足关系：1.20mm+(B-8)×0.30mm/2≤A1≤4.50mm+(B-8)×1.00mm/2；塑封结构的宽度A2满足关系：1.20mm≤A2≤3.50mm；塑封结构的厚度A3满足关系：A3≥0.35mm；B为外引脚线的个数，B为满足4≤B≤68的整数。以下将以外引线脚的个数为8的封装结构为例，对本发明的高密度集成电路封装结构做进一步的阐述。本发明的封装结构被本发明称之为CPC系列封装结构，即CPC4、CPC6、CPC8…………等。下面为了表述方便，本发明以CPC8代表本发明的外引线脚的个数为8的封装结构。
在本实施例中，所述塑封结构采用环氧树脂组合物封装而成，作为优选地所述环氧树脂组合物由双酚F型环氧树脂(DGEBF)、苯乙烯-马来酸酐共聚物(SMA1000)、聚乙醇二缩水甘油醚、聚丙二醇聚四氢呋喃端羟基聚酯、聚丁烯基琥珀酰亚胺、白炭黑、硅烷偶联剂和脱模剂。作为优选地，所述环氧树脂组合物由25～27.5wt％的苯乙烯-马来酸酐共聚物(SMA1000)、28～30wt％的熔融硅石、10～12wt％的聚丙二醇聚四氢呋喃端羟基聚酯、5.5～6.0wt％的白炭黑、3.5～4.0wt％的聚乙醇二缩水甘油醚、1.5～2.0wt％的聚丁烯基琥珀酰亚胺、0.5～0.8wt％的硅烷偶联剂、脱模剂，和余量的双酚F型环氧树脂(DGEBF)组成。在本实施例中所述双酚F型环氧树脂的环氧当量为171～175，25℃时的黏度为4000～6000mPa·s。所述白炭黑的比面积为100～300m2/g，粒径为10～50nm。熔融硅石的颗粒尺寸优选为1～50μm。所述硅烷偶联剂优选为γ-缩水甘油醚氧丙基三甲氧基硅烷、γ-甲基丙烯酰氧基丙基三甲氧基硅烷、γ-甲基丙烯酰氧基丙基三乙氧基硅烷或γ-甲基丙烯酰氧基甲基二甲氧基硅烷中的至少一种。所述脱模剂可选择有机硅系脱模剂或硬脂酸金属盐。在本实施例中通过添加聚丙二醇聚四氢呋喃端羟基聚酯和聚丁烯基琥珀酰亚胺出人意料的改善了抗回焊性和耐潮湿性，而且固化后的封装结构模量较小，能够有效吸收界面形变而产生的应力，基本没有观察到芯片分层和内部龟裂的情形，封装效果好。
在本实施例中，所述微米级连接线为直径为10～25μm的合金线，所述铜合金中含有2.50～3.05wt％的Ag、0.08～0.10wt％的In、0.05～0.06wt％的Ge、0.01～0.02wt％的Nb、0.003～0.005wt％的Zr和余量的Cu。所述微米级连接线可通过常规的铸锭、连铸、粗拔、退火、 精拔、退火处理工艺制备得到，并且所述铜合金线表面上镀覆有银保护层，该微米连接线具有优异的抗氧化性能，有利于缩短焊接间距，特别适合于本发明所述的高密度、多引脚的集成电路封装。所述微米级连接线与芯片，以及所述微米级连接线与内引脚线之间通过软钎焊电性连接。软钎焊使用无铅钎料，并且所述无铅钎料含有3.2～3.6wt％的In、1.3～1.5wt％的Ag、0.5～0.6wt％的Bi、0.25～0.30wt％的Cu、0.10～0.15wt％的Ge，和余量的Sn。所述无铅钎料的熔化温度为201～206℃，其可焊性与可靠性好，抗剪切强度大于35.5MPa，电导率为10.2～10.5％IACS，适合于本发明所述的高密度、多引脚的集成电路封装。另外，微米级连接线采用纯铜线，微米级连接线与芯片，以及所述微米级连接线与内引脚线之间在高温情况下，也能通过原子吸引结合。进一步的，引脚线与PCB之间可以通过软钎焊电性连接；软钎焊使用无铅钎料，并且所述无铅钎料含有3.2～3.6wt％的In、1.3～1.5wt％的Ag、0.5～0.6wt％的Bi、0.25～0.30wt％的Cu、0.10～0.15wt％的Ge，和余量的Sn。
塑封体宽度的确定：
通过对减小封装内阻的专门研究，本发明得知，引线框基岛到引线脚间距为0.15mm以内时，电性能明显改善，生产效率、生产合格率、成本等综合效果较好。根据可靠性研究得知塑封体宽度为2.60mm左右时，可靠性、电性能、通用性等综合性能较好。现有技术中的芯片生产技术，针对这种封装形式的芯片，制造工艺一般在0.6微米以下，所产出的芯片尺寸通常在0.5×0.5mm2～1.5×1.8mm2之间，这就要求引线框的基岛尺寸为≤1.5×1.8mm2之间。基岛的边缘到内引线顶端的间距取决于材料厚度、刀具材料和加工精度，目前的技术要求达到0.10以上，考虑效率、刀具寿命后最合理的间距为0.15mm左右。内引线顶端到塑封体边缘的距离应为0.20～0.40mm，由引线脚的强度和可靠性决定。所以，如果只考虑产品的通用性的情况下，塑封体宽度应大于2.0mm。如果只考虑引线框生产技术，最小基岛为0.762×0.762mm2，塑封体宽度只需1.40mm，这样可以满足约40％左右的产品，比2.60mm塑封体宽度，塑封树脂可以减少15％，占总材料成本的1.0％，考虑投资成本，标准化应用需求，单独开发封装结构是不可取的。同样，将宽度增加到3.5mm，成本将增加约7.0％，生产效率下降，性能和通用性等其它特性没有改善，不应考虑。综上所述，塑封体宽度应为2.60mm。宽度在1.4mm到3.5mm之间的其它宽度与宽度为2.60mm比较，综合成本提高但没有本质差别，品质没有任何改善，所以不可取，但同样应该属于本发明保护范围。
塑封体长度的确定：
为减少集成电路在印刷线路板上占有的空间、减轻集成电路的重量、减少集成电路封装材料、提高集成电路生产时的效率(注：集成电路越短，用来排列集成电路的引线框就可以容纳更多的产品，生产效率就越高)、降低成本，设计集成电路塑封体时要尽量减少它的长 度，塑封体越短越好。考虑到整机厂的应用中PCB板的制造，线宽在0.20mm以上、间距在0.30mm以上时，生产成本最低、效率最高、品质稳定，所以引线脚间距为0.50mm以上，考虑到电性能、机械加工要求，引线脚宽度为0.20mm～0.23mm，相应PCB板线宽以0.22～0.23较好，即引线脚间距为0.53mm是效率和综合成本最好的。小于以上尺寸的品质会下降，效率会降低，PCB板成本大幅度提高；所以封装和整机厂使用的综合成本反而提高，从封装成本与整机厂使用成本来考虑，引线脚间距确定为0.53mm。脚间距0.35mm到0.53mm之间没有改善性能，但综合成本反而提升，脚间距0.53mm到1.00mm之间，成本提高，性能没有改善。综上所述，引线脚间距确定为0.53mm。间距为0.35mm到1.00mm之间的其它尺寸，虽然可行，品质在规范内，成本提高，应该属于本发明保护范围。其相应的塑封体长度确定为2.60mm，塑封体长度从1.20mm到4.50mm之间的其它尺寸，同样应该属于本发明保护范围。
塑封体厚度的确定：
为满足终端产品轻、薄化要求，应该越薄越好；从减少塑封料用量考虑，塑封体也是越薄越好。考虑到芯片的厚度一般为0.19mm以上，芯片表面到塑封体表面距离考虑焊线的安全高度在0.2mm，基岛底面到塑封体底面的高度为0.2mm以上，引线框厚度为0.11mm以上，因此塑封体的厚度应大于0.70mm以上。但考虑到芯片减薄成本、线弧控制难易程度对品质的影响、电阻和强度对引线框厚度的要求、引线脚成型时产生的应力、塑封材料的气密性和通用性，本发明对成本和品质综合考虑后确定厚度为0.85mm。厚度0.35mm～0.85mm，生产难度增加，综合成本提高；厚度大于0.85mm以上,则用料增加，成本明显提高。综上所述，厚度确定为0.85mm。厚度在0.35mm以上的其它尺寸虽然可行，与这一尺寸相比，优点没有明显差异，综合效果较差，应该属于本发明保护范围。
塑封体高度方向的角度及棱角：
一般不作研究，由模具企业根据脱模需求和外观美观确定。
在长方体塑封结构的底部还开设有应力释放槽，该应力释放槽的深度和宽度均为0.05mm，该应力释放槽的长度和长方体塑封结构的宽度相等，并且所述应力释放槽为螺旋形槽体。在所述螺旋形槽体内填充有聚丁烯基琥珀酰亚胺和氨基聚酰胺树脂的组合物，并在40-50℃固化处理3.0-5.0min，其中：聚丁烯基琥珀酰亚胺和氨基聚酰胺树脂的质量比为3:1。因为集成电路封装结构包括塑封树脂、金属引线框、硅芯片等不同的材料，由于使用的材料性质差异很大，热膨胀系数不一样，组合在一起时就会产生应力。该应力不仅会使不同材料间产生离层，影响产品可靠性，还会使芯片产生弯曲，硅晶格扭曲大量的模拟实验表明，对于本发明的封装结构，设置如上所述的结构，与常规形状的应力释放槽(例如常规的网状应力释放槽)能够避免集成电路使用时温度变化以及外力作用应力矢量的叠加，而且能够使得应力向无方 向性耗散，从而能够有效避免硅晶格的扭曲，最大幅度的避免了应力对集成电路性能的影响。
现有技术中的SOP、TSSOP、SSOP、MSOP封装形式与本实施例的产品CPC8最为接近，可以看成是最为接近的现有技术。
本发明中其它引线脚产品，在具体推出时，我司会综合考虑电性能、热性能、功耗、可靠性及生产效率、品质等情况，在本发明范围内选择最优的具体结构尺寸。
CPC8相比现有SOP8，具有以下优点：
一、品质优势
1.可靠性明显改善
本发明提出的应力槽理论、基岛表面结构、短流道结构很好地解决了外形变形、不同物质间的分层、芯片变形、塑封体与不同物质间的结合、塑封体的分子结构、以及注塑过程中流体对微连线的损坏等等，产品可靠性提高，品质得以保障。应力释放槽为螺旋形槽体，可将螺纹形的结构特性极佳的应用到应力的力学设计中。
2.电、热性能、频率特性明显改善，满足线宽日益缩小的芯片要求
缩短微米级连线、缩短引线脚，封装内阻及热阻明显下降，改善了电热性能及频率特性，也提高了可靠性。
二、成本优势明显
1.SOP8的塑封体体积是：长4.9mm*宽3.9mm*厚1.5mm＝28.7mm3，本发明以8脚的为例子，CPC8的塑封体尺寸是长2.60mm*宽2.60mm*厚0.85mm＝5.746mm3，可节省塑封树脂为80％,全中国年生产量500亿只以上产品，可节省人民币为：500*0.008*0.80(每只树脂成本价)＝3.20亿元。
2.SOP8的金属引线框平面展开体积是：(宽7.8mm*长4.9mm*厚0.203)＝7.76mm3,CPC8的金属引线框的平面展开体积是：(5.00mm*2.60mm*0.154mm)＝2.00mm3,可以节省金属材料74％，全中国年生产量500亿只以上产品，铜的价格每公斤50元，铜的密度为8.93，则可节省人民币为：500*(7.76-2.13)*8.93/1000/1000*50＝1.26亿元。
3.可以减少电镀面积，从而减少用锡量，减少包装、运输成本，由于引线框密度大幅提高，生产综合效率可以提高35％以上。
综上所述，本发明所发明产品的应用将为人类节省大量宝贵资源，为生产和使用企业节省能耗、提高效率、创造效益，为终端用户节约支出。每年仅本产品成本即可节省价值达到人民币5亿元以上。本发明首期推出的产品为CPC8、CPC12、CPC14、CPC16、CPC20、CPC24六款(目前用量最大的六款产品)，即可节省人民币10亿元以上。推出本发明的所有系列产品，每年将为人类节省数十亿元人民币。
三、其它优点
1.由于体积的微型化，占用整机印刷线路板的空间小了，使整机体积可以做得更小；同样大小的印刷线路板可以容纳更多的电子元件，使相同体积的整机功能更强。
2.由于体积微型化，产品的重量变轻，可以使焊接有集成电路印刷线路板的重量变轻。
综上所述，采用本发明封装的产品不仅经济效益明显，产品品质、功能、产业链效率及效益等等都有很大改善。
CPC8和TSSOP8、SSOP、MSOP8、部分QFN、DFN相比：
一、品质优势
1.可靠性明显改善
本发明提出的应力槽理论、基岛表面结构、短流道结构很好地解决了外形变形、不同物质间的分层、芯片变形、塑封体与不同物质间的结合、塑封体的分子结构、以及注塑过程中流体对微连线的损坏等等，产品可靠性提高，品质得以保障。
2.电、热性能、频率特性有明显改善
缩短微米级连线、缩短引线脚，封装内阻及热阻明显下降，改善了电性能，也提高了可靠性。
二、成本等其它优势
1.铜、树脂、锡材料较大幅度减少。
2.生产效率明显提升。
3.适用范围更广。
4.相比QFN、DFN生产难度下降，材料制造成本下降更明显。
综上所述，有些本来只能使用以上对照的封装产品，采用本发明的封装形式，具有较高的经济效益。
现代社会人工成本高涨，资源匮乏，原材料价格越来越贵，低碳是社会趋势也是社会的必然。本发明的发明满足了时代的要求，节省了宝贵的自然资源和人力资源，符合低碳、绿色的社会发展要求。
对于本领域的普通技术人员而言，具体实施例只是对本发明进行了示例性描述，显然本发明具体实现并不受上述方式的限制，只要采用了本发明的方法构思和技术方案进行的各种非实质性的改进，或未经改进将本发明的构思和技术方案直接应用于其它场合的，均在本发明的保护范围之内。

Claims (10)

  1. 一种高密度集成电路封装结构，包括：金属引线框，所述金属引线框包括引线框基岛、内引脚线和外引脚线；固定在引线框基岛上的芯片；以及芯片和内引脚线之间的微米级连接线；和密封所述金属引线框、芯片以及微米级连接线的长方体塑封结构，其特征在于：所述塑封结构的长度A1满足关系：1.20mm+(B-8)×0.3mm/2≤A1≤4.50mm+(B-8)×1.00mm/2；塑封结构的宽度A2满足关系：1.20mm≤A2≤3.50mm；塑封结构的厚度A3满足关系：A3≥0.35mm；B为外引脚线的个数，且为满足4≤B≤68的整数。
  2. 根据权利要求1所述的一种高密度集成电路封装结构，其特征在于：所述外引脚线的跨度B1满足2.30mm≤B1≤5.20mm；外引脚线的间距B2满足0.30mm≤B2≤1.00mm。
  3. 根据权利要求1所述的一种高密度集成电路封装结构，其特征在于：所述塑封结构的长度A1满足以下关系：A1＝2.50+(B-8)×0.53/2mm；塑封结构的宽度A2为2.60mm；塑封结构的厚度A3为0.85mm；外引脚线的跨度B1为4.00mm；外引脚线的宽度为0.20mm～0.23mm、引脚线中心间距B2为0.53mm。
  4. 根据权利要求1所述的一种高密度集成电路封装结构，其特征在于：所述长方体塑封结构的底部开设有应力释放槽，所述应力释放槽为螺旋形槽体。
  5. 根据权利要求4所述的一种高密度集成电路封装结构，其特征在于：该应力释放槽的深度和宽度均为0.05mm。
  6. 根据权利要求1所述的一种高密度集成电路封装结构，其特征在于：所述引线框基岛到内引脚顶端的距离为0.150mm；基岛下沉距离为0.152mm；内引脚线长度为0.400mm。
  7. 根据权利要求1所述的一种高密度集成电路封装结构，其特征在于：所述塑封结构采用环氧树脂组合物封装而成，所述环氧树脂组合物由双酚F型环氧树脂、苯乙烯-马来酸酐共聚物、聚乙醇二缩水甘油醚、聚丙二醇聚四氢呋喃端羟基聚酯、聚丁烯基琥珀酰亚胺、白炭黑、硅烷偶联剂和脱模剂组成。
  8. 根据权利要求1所述的一种高密度集成电路封装结构，其特征在于：所述微米级连接线与芯片，以及所述微米级连接线与内引脚线之间通过软钎焊电性连接；软钎焊使用无铅钎料，并且所述无铅钎料含有3.2～3.6wt％的In、1.3～1.5wt％的Ag、0.5～0.6wt％的Bi、0.25～0.30wt％的Cu、0.10～0.15wt％的Ge，和余量的Sn。
  9. 根据权利要求1-8任一项所述的一种高密度集成电路封装结构的封装方法，其特征在于：包括以下步骤：提供一金属引线框，所述金属引线框包括引线框基岛、内引脚线和外引脚线；提供一芯片，并将所述芯片粘结于所述引线框基岛上；所述芯片和内引脚线之间通过微米级连接线电性连接；通过注塑方法形成用于密封所述金属引线框和所述芯片的长方体塑封结构。
  10. 一种集成电路，其特征在于：所述集成电路通过设置权利要求1-8任一项所述的高密 度集成电路封装结构形成。
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