CN103270590A - 用于芯片的电源/接地布局 - Google Patents

用于芯片的电源/接地布局 Download PDF

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Publication number
CN103270590A
CN103270590A CN201180061291XA CN201180061291A CN103270590A CN 103270590 A CN103270590 A CN 103270590A CN 201180061291X A CN201180061291X A CN 201180061291XA CN 201180061291 A CN201180061291 A CN 201180061291A CN 103270590 A CN103270590 A CN 103270590A
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metal layer
chip
metal level
island portion
layer
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CN103270590B (zh
Inventor
S·萨塔德加
韩忠群
李维旦
游淑华
郑全成
吴亚伯
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Kaiwei International Co
Marvell International Ltd
Marvell Asia Pte Ltd
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Mawier International Trade Co Ltd
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Abstract

本发明的实施例提供一种芯片，该芯片包括形成在第一半导体管芯(104)之上的基部金属层(102)，以及形成在基部金属层之上的第一金属层(110)。第一金属层包括多个岛部(112)，该岛部(112)被配置为在芯片中路由(i)接地信号或(ii)电源信号中的至少一个。芯片还包括形成在第一金属层之上的第二金属层(118)。第二金属层包括多个岛部(120)，该岛部(120)被配置为在芯片中路由(i)接地信号或(ii)电源信号中的至少一个。

Description

用于芯片的电源/接地布局
相关申请的交叉引用
本公开要求2011年10月19日提交的美国专利申请13/277,140的优先权，该美国专利申请要求2010年10月20日提交的美国临时专利申请61/405,099的优先权，出于所有目的，除了与本说明书不一致的那些段落(如果有的话)，前述两件申请的整个说明书通过引用的方式全部合并于此。
技术领域
本发明的实施例涉及芯片封装领域，并且更具体地，涉及利用引线键合封装的电源/接地布局。
背景技术
随着社会变得更加具有移动性，更小的电子设备逐渐流行。更小的电子设备的流行产生了对提供高性能和良好可靠性的小而轻的器件的需求。为了帮助满足该需求，要减小电子封装组件(用于这样的更小的电子设备中)中的半导体管芯或芯片的尺寸大小。然而，减小的尺寸大小对电子封装组件中的半导体管芯或芯片的电源信号和/或接地信号的传统路由配置提出了挑战。
此外，另一挑战是要增加输入/输出(I/O)功能，以适应在这样的更小的电子设备中使用的先进技术。该先进技术依赖于I/O功能的增加，以避免跨过半导体管芯或芯片中的接触器或连接件的电压的下降。然而另一挑战是，在针对这些挑战提供解决方案的同时，要将半导体管芯或芯片的生产制造成本保持相对较低。此外，倒装芯片封装布置可能是昂贵的。利用引线键合技术可以帮助降低各种封装结构的成本。
发明内容
本发明提供一种制造芯片的方法。该方法包括在第一半导体管芯之上形成基部金属层，在基部金属层之上形成第一金属层，以及在第一金属层中创建多个岛部，以在芯片中路由(i)接地信号或(ii)电源信号中的至少一个。该方法还包括在第一金属层之上形成第二金属层，在第二金属层中创建多个岛部，以在芯片中路由(i)接地信号或(ii)电源信号中的至少一个。
本发明还提供一种芯片，该芯片包括形成在第一半导体管芯之上的基部金属层以及形成在基部金属层之上的第一金属层。第一金属层包括多个岛部，该岛部被配置为在芯片中路由(i)接地信号或(ii)电源信号中的至少一个。该芯片还包括形成在第一金属层之上的第二金属层。第二金属层包括多个岛部，该岛部被配置为在芯片中路由(i)接地信号或(ii)电源信号中的至少一个。
附图说明
通过下文的详细描述并结合附图，将很容易理解本发明的实施例。为便于描述，同样的参考标号表示相同的结构元件。此处，在附图中以示例的方式而不是限定的方式描述了实施例。
图1A至图1G示出了用于制造芯片的电源/接地布局的各个阶段的横截面侧视图。
图2示出了图1A至图1G的芯片的俯视图。
图3示出了包括图1A至图1G的芯片的电子封装组件的横截面侧视图。
图4示出了图1A至图1G的芯片的横截面侧视图，另一管芯堆叠在该芯片的顶部上。
图5示出了图1A至图1G的芯片的另一布置的横截面侧视图，另一管芯堆叠在该芯片的顶部上。
图6示出了制造图1A至图1G的芯片的电源/接地布局的方法的工艺流程图。
具体实施方式
很多电子设备(例如蜂窝电话、计算机、收音机、常见的家用电器等)均含有集成电路或芯片。芯片包括由半导体材料制成的半导体管芯，电子电路实现在该半导体管芯中。芯片还包括容纳半导体管芯，并且包括多种材料的封装，以提供芯片与外部电子元器件的电互连。例如，引线键合是本公开中的工艺，其提供针对芯片的电连接。
图1A至图1G示出用于制造芯片100的电源/接地布局的各个阶段的横截面侧视图。图1A示出了形成在半导体管芯104之上的基部金属层102。基部金属层102例如可以包括铝(Al)、铝-铜合金、铜(Cu)或镍(Ni)。半导体管芯104例如包括硅(Si)、硅锗(SiGe)、锗(Ge)、镓砷(GaAs)等。在一些实施例中，基部金属层102可以通过例如电沉积、蒸发或溅射工艺来沉积。在另一实施例中，基部金属层102可以是经化学平面化和机械平面化的。本领域技术人员熟悉这些工艺，并且因此在此将不描述这些工艺。
在一个实施例中，基部金属层102提供用于芯片100(并且更具体地是半导体管芯104)的输入/输出(I/O)功能。基部金属层102还用作芯片100的重分布层(RDL)。因此，基部金属层102配置有多条迹线和线以传导电信号。基部金属层102和半导体管芯104彼此电连接，使得电信号可以在它们之间通过。
图1B示出形成在基部金属层102之上的绝缘层106。绝缘层106可以由任意电介质材料形成，包括环氧树脂、聚酰亚胺、低介电常数的电介质、二氧化硅(SiO2)等。绝缘层106将芯片100的导电部分或导电层彼此隔开，并保护基部金属层102避开芯片100的其他的导电金属层。
一些器件特征可以形成在绝缘层106中。器件特征例如可以包括可键合迹线、多条线和多个通孔108。如图所示，通孔108用作绝缘层106中的连接件，以允许芯片100的不同层之间的导电连接。例如，通过将基部金属层102连接至不同导体(例如芯片100的附加金属层)，通孔108用作接触器。正如本领域已知的，在一个实施例中，通孔108由金属形成。
图1C示出形成在绝缘层106之上的第一金属层110。第一金属层110例如可以包括铜(Cu)、铝(Al)、铝-铜合金、铝-硅合金或镍(Ni)。
在一些实施例中，电镀工艺、电化学沉积工艺或溅射工艺将第一金属层110沉积在绝缘层106之上。在另一实施例中，镶嵌工艺将铜的薄层沉积，其用作绝缘层106上方的第一金属层110。在一些实施例中，第一金属层110可以被化学平面化和机械平面化。本领域技术人员熟悉这些工艺，因此在此不描述这些工艺。
由一个或多个开口113限定的多个岛部112形成在第一金属层110中。如果需要的话，岛部112可以具有相对于彼此不同的尺寸和/或形状。例如，多个岛部112通常具有基本上长方的形状。在一些实施例中，多个岛部112的形状可以包括但不限于基本上正方的形状、基本上椭圆的形状和基本上圆形的形状。
在一个实施例中，多个岛部112位于第一金属层110的中心。多个岛部112提供了芯片100的层之间的电通路。正如在此更加详细地讨论的，多个岛部112以及开口113还提供了相对于第一金属层110的应力消除(stress relief)。对于多个岛部112的中心位置带来了层之间较短的电通路。基于正在创建的较低的电感和电阻，较短的电通路带来较好的电性能。
在一个实施例中，第一金属层110是固态的接地(GND)平面。第一金属层110将GND平面的顶部上的信号与GND平面以下的信号隔绝。具体地，第一金属层110在半导体管芯104中为信号隔绝下方的噪声，尤其是在大电流切换的过程中。正如在此更加地详细讨论的，第一金属层110中的多个岛部被配置为连接信号，例如将来自另一层的VDD经过第一金属层110连接至半导体管芯104，或者连接来自基部金属层102的I/O信号。用作固态的GND平面的第一金属层110有助于减小芯片100中的电压的下降。
图1D示出了电介质层114形成在第一金属层110之上。电介质层114可以由任意电介质材料形成，包括例如环氧树脂、聚酰亚胺、低介电常数的电介质、二氧化硅(SiO2)等。电介质层114将芯片100中的导电部分或导电层彼此隔开，并保护第一金属层110避开其他的导电金属层。在一个实施例中，电介质层114是层间电介质层。
一些器件特征可以形成在电介质层114中。器件特征例如可以包括可键合迹线、多条线和多个通孔116。通孔116是电介质层114中的连接件，以将第一金属层110和基部金属层102连接至不同导体，例如芯片100中的附加金属层。正如本领域已知的，在一个实施例中，通孔116由金属形成。
在一个实施例中，电介质层114中的通孔116所在的位置可以对应于绝缘层106的通孔108以及岛部112的位置。换句话说，通孔108、116和岛部112可以位于它们各自的层中的相似位置，使得它们基本上对齐。
图1E示出了形成在电介质层114上的第二金属层118。第二金属层118可以包括例如铝(Al)、铝-铜合金、铝-硅合金、镍或铜(Cu)。在一些实施例中，第二金属层118可以使用公知的合适工艺形成在电介质层114上，例如物理气相沉积(PVD)工艺、溅射过程、电沉积或蒸发沉积。本领域技术人员熟悉这些工艺，因此在此将不描述这些工艺。
多个岛部120形成在第二金属层118上，以提供应力消除，并且提供电通路。如果需要的话，岛部120可以具有相对于彼此不同的尺寸和/或形状。例如，多个岛部120具有基本上长方的形状。在一些实施例中，多个岛部120的形状包括但不限于基本上正方的形状、基本上椭圆的形状和基本上圆形的形状。
在一个实施例中，多个岛部120位于第二金属层118的中心。正如在此更加详细地讨论的，对于多个岛部120的中心位置提供了从第二金属层118到堆叠在芯片100的顶部上的管芯的较短的电通路。基于正在生成的较低的电感和电阻，较短的电通路提供较好的电性能。在一个实施例中，第二金属层118中的多个岛部120中的一些的位置对应于第一金属层110的多个岛部112中的一些的位置。换句话说，多个岛部120、112中的一些在它们各自的金属层118、110上位于相似的位置，使得它们基本上对齐。
在一个实施例中，第二金属层118用作电源平面，其被配置为在芯片100的顶部供电。第二金属层118经过引线键合连接从外部器件(未示出)接收的电能，且经过通孔108、116及与通孔108、116对齐的岛部112和120，以及经过基部金属层102向半导体管芯104供电，基部金属层102用作RDL。
图1F示出了形成在第二金属层118之上的钝化层122。钝化层122可以由任意合适的材料形成，其例如包括氧化物、氮化物、二氧化硅、氮化硅等。钝化层122通常是被化学平面化或机械平面化的。钝化层122防止下面的金属层与精细线金属相互连接。钝化层122还防止移动离子和其他污染物的渗透。
图1G示出了钝化层122中的一个或多个开口124。钝化层122中的一个或多个开口124暴露第二金属层118中的接触点以减少热量，从而为芯片100提供更好的散热能力。一个或多个开口124还暴露岛部120。另外，正如在此进一步讨论的，一个或多个开口124暴露第二金属层118，以便与另一管芯(未示出)电连接，另一管芯能够堆叠在芯片100上。
由此，正如可以看出的，芯片100包括单独的接地平面和电源平面(例如，分别为第一金属层110和第二金属层118)，以向半导体管芯104提供接地信号和/或电源信号。正如在此进一步描述的，单独的接地平面和电源平面还能够向其他管芯提供接地信号和/或电源信号。
图2示出了图1的芯片100的俯视图。为清楚起见，在图2中没有描绘钝化层122。该俯视图示出了基部金属层102的暴露的部分、第二金属层118、第一金属层110的暴露的部分，以及第二金属层118中的多个岛部120和钝化层122中的一个或多个开口124。基部金属层102及第一金属层110的暴露的部分位于沿芯片100的周缘，以允许到各个层的引线键合连接。
多个岛部120提供电通路且提供应力消除。相似地，一个或多个开口124提供应力消除。例如，第二金属层118中的应力来自热膨胀的区别或者来自第二金属层118的微结构(本征应力)。对于多个岛部120的位置仅示出为示例，而不是实际的位移位置。多个岛部120还代表这样的示例，即不对可以形成在第二金属层118中的数量进行限制，也不对尺寸、大小或形状进行限制。
图2还示出了多个接触点的示例。例如，接触点提供了与在多个位置耦合至键合线212的焊盘(bond pad)206、208、210的电连接。焊盘206、208、210通常在各个金属层102、110和118的暴露的部分上沿半导体管芯104的外周边缘定位。例如，焊盘206位于第二金属层118上，焊盘208位于第一金属层110的暴露的部分上，而焊盘210位于基部金属层102的暴露的部分上。
在一个实施例中，来自外部器件(未示出)的VDD电源经过键合线212在位于第二金属层118上的焊盘206处被接收。VDD电源经过由通孔116、岛部112和通孔108限定的通路(如图1B至图1E所示)从第二金属层118提供至基部金属层102。VDD电源接着经过基部金属层102和半导体管芯104之间的电连接(未示出)从基部金属层102提供至半导体管芯104。在芯片100中提供绝缘，以避免元器件彼此间不必要的相互作用。例如，通孔108、116与第一金属层110接触，作为无限的接地电势，第一金属层110用作信号的GND平面。
在另一实施例中，GND信号经过键合线212在第一金属层110的焊盘208处被接收。GND信号能够接着经过通孔108提供至基部金属层102，并由此提供至半导体管芯104。另外，多个岛部120提供了GND信号从第一金属层110到能够堆叠在芯片100的顶部上的另一管芯的电通路。例如，正如在此所进一步描述的，GND信号的电通路可以包括第一金属层110到通孔116(在图1E至图1G的横截面图中所示)，到岛部120，经过钝化层122中的开口124以及到堆叠在芯片100的顶部上的另一管芯。
另外，I/O信号能够经过键合线212，从外部器件(未示出)或从半导体管芯104在基部金属层102的焊盘210处被接收。同样，I/O信号能够经过基部金属层102从半导体管芯104被送到第二金属层118和/或被送到堆叠在芯片100的顶部上的另一管芯。例如，I/O信号的电通路在基部金属层102开始，经过通孔108(在图1B至图1E的横截面图中所示)，并且经过第一金属层110(即GND平面)中的岛部。电通路还经过通孔116(在图1E至图1G的截面图中所示)，到第二金属层118(即电源平面)，并且到堆叠在芯片100的顶部上的另一管芯。
图3示出了包括芯片100的电子封装组件300的横截面图。在一个实施例中，电子封装组件300包括安装在引线框302上的芯片100、一个或多个键合线212、位于第二金属层118上的一个或多个焊盘206、一个或多个引线指304，以及模制复合物306。
引线框302可以由金属框形成，以支撑用于封装的半导体管芯104。引线框302可以由铜或铜合金(但不限于铜或铜合金)制成。因为芯片100包括接地平面(例如第一金属层110)和电源平面(例如第二金属层118)，所以引线框302不需要包括接地平面或电源平面。
键合线212可以形成在焊盘206和引线指304之间。正如本领域已知的，键合线212的端头可以是球形物、楔形物或另一配置，并且键合线212的端头可以用引线键合机形成。键合线212可以由以下材料(但不限于这些材料)形成，该材料包括铝(Al)、铜(Cu)、金(Au)、银(Ag)、锡-铅合金或铝合金。焊盘206可以由铝(Al)、铜(Cu)或已知具有导电特性的另一合适的材料形成。
模制复合物306封住键合线212和半导体管芯104。模制复合物306通常包括电绝缘材料(例如热固树脂)，该电绝缘材料被布置为保护半导体管芯104免受与操作有关的湿气、氧化或碎屑的侵害。在另一实施例中，模制复合物306被布置为基本上填充在第二金属层118和另一管芯之间的区域。
图3示出了具有有源侧308(例如前侧)和无源侧310(例如背侧)的半导体管芯104，该有源侧是其上构建有集成电路的表面，该无源侧是其上没有构建任何电路的表面。经由位于基部金属层102的暴露的部分处的焊盘206(如图2所示)，集成电路是可访问的。键合线212被设置为，将芯片100的基部金属层102上的焊盘206连接至引线框302的合适的引线指304。此外，半导体管芯104的有源侧308基本上平行于第一金属层110和第二金属层118。
在一个实施例中，正将在此进行进一步地讨论的，第一金属层110中的多个岛部112中的一些被配置为，经过通孔116、108和岛部120，从基部金属层102到其他的堆叠管芯应用，将I/O信号连接至有源侧308和/或提供对有源侧308的访问。此外，第二金属层118中的多个岛部120中的一些被配置为，经过通孔116，将GND信号从第一金属层110连接至其他的堆叠管芯应用，如314所示的通路并且正如在此进一步的讨论。该其他的堆叠管芯应用例如可以包括动态随机访问存储器(DRAM)、闪存堆栈管芯或倒装芯片。经过由通孔116、岛部120和通孔108限定的通路316，VDD电源从第二金属层118被提供至基部金属层102。
第一金属层110和第二金属层118的作用可以互换，从而使得第一金属层110是电源平面而第二金属层是GND平面。因此，第一金属层110中的多个岛部112和第二金属层118中的多个岛部120的作用将会互换，从而使得第一金属层110中的多个岛部112被配置为将GND信号路由经过其他层，并且第二金属层118中的多个岛部120被配置为将电源和I/O信号路由经过金属层。为清楚起见，具体实施方式部分将继续描述第一金属层110是GND平面而第二金属层118是电源平面的实施例。
图4示出了封装结构400的横截面侧视图，其中第二管芯402堆叠在芯片100的顶部上。在给定的封装中容纳一个以上的管芯被称为“系统级封装”(SIP)或三维集成电路。通过将多个独立制造的执行不同功能的管芯组装到单个封装中以生产复杂的电子消费产品，这样的封装结构极大地节省了空间。图4示出了以竖直方式堆叠的两个管芯，但是可以包括以竖直和水平的集成布置堆叠的多个管芯的管芯堆栈。
钝化层122提供了一个或多个开口124，以暴露第二金属层118中的接触点404。接触点404位于从第二金属层118到第二管芯402供电的点。接触点404还位于相应的岛部120处，以允许接地信号从第一金属层110被提供至第二管芯402，以及允许I/O信号在第二管芯402和基部金属层102(并由此是半导体管芯104)之间提供。互连结构406(例如块、垫、杆、柱、球或者将芯片100电耦合至第二管芯402的任何合适的结构)可以用于在接触点404和第二管芯402之间路由电信号。第二管芯402经过键合线212连接至引线框302。第二管芯能够经由例如倒装芯片工艺堆叠到芯片100上。如图4所示，第二管芯402利用焊接块408(焊接块408耦合至垫410)形式的互连结构406被耦合至芯片100。
图5示出了芯片100的封装结构500的另一横截面侧视图，其中第二管芯502堆叠在芯片100的顶部上。图5示出了以竖直方式堆叠的两个管芯，但是可以包括以竖直和水平的集成布置堆叠的多个管芯的管芯堆栈。
钝化层122创建了一个或多个开口124，以暴露第二金属层118中的接触点504。接触点504位于从第二金属层118到第二管芯502供电的点。接触点504还位于相应的岛部120处，以允许接地信号从第一金属层110被提供至第二管芯502，以及允许I/O信号在第二管芯502和基部金属层102(并由此是半导体管芯104)之间提供。互连结构506(例如块、杆、柱、球或者将芯片100电耦合至第二管芯502的任何合适的结构)可以用于在接触点504和第二管芯502之间路由电信号。第二管芯502经过键合线212连接至引线框302。第二管芯502能够经由例如倒装芯片工艺堆叠到芯片100上。如图5所示，第二管芯502利用焊接块508和柱510形式的互连结构506耦合至芯片100。
尽管只有两个半导体管芯(例如104和402或502)描绘在图4和图5的电子封装组件中，然而在其他实施例中，附加的半导体管芯可以以堆叠的配置或并排的配置被布置在电子封装组件中。附加的半导体管芯能够类似地耦合至基部金属层102或第二金属层118，以使用在此描述的技术路由电源信号和/或接地信号。例如，焊盘206可以使用在此描述的技术来帮助附加的管芯与第二金属层118的电耦合。
通过经由键合线212在基部金属层102、第一金属层110和第二金属层118上提供用于I/O、GND和/或电源信号的多个焊盘位点，芯片100的电源/接地布局增加了I/O功能。此外，通过以更有效的方式提供用于电连接至不同层的机构，作为GND平面的第一金属层110减小了电压的下降。总体上，该电子封装组件减小了电压下降，并且保持了电子封装的小尺寸，同时增加了I/O功能并保持成本降低。
图6示出了制造芯片100的电源/接地布局的方法的工艺流程图600。为简洁起见，形成绝缘层106、电介质层114、钝化层122以及层中的通孔108、116的方法通过引用被作为对形成金属层的讨论的一部分来提及。
在602，方法包括在半导体管芯104之上形成基部金属层102。作为半导体管芯104的制造的一部分或者基于已知的封装或组装工艺，基部金属层102被耦合至半导体管芯104。绝缘层106被形成在基部金属层102之上，以保护基部金属层102避开其他导电层。接着，多个通孔108形成在绝缘层106中，以提供用于将基部金属层102连接至不同导电层的机构。
在604，方法包括在绝缘层106之上形成第一金属层110，绝缘层106形成在基部金属层102之上。正如所讨论的，第一金属层110用作GND平面，以隔离下面的信号噪声，尤其是在大电流切换的过程中。
在606，方法包括在第一金属层110中形成多个岛部112。多个岛部112促进了经过各个层的电连接。电介质层114在第一金属层110之上形成，以保护第一金属层110避开其他导电层。接着，多个通孔116在电介质层114中形成，以提供用于将第一金属层110连接至不同导电层的机构。
在608，方法进一步包括在电介质层114之上形成第二金属层118，电介质层114在第一金属层110之上形成。正如所讨论的，第二金属层118用作电源平面。
在610，方法进一步包括在第二金属层118中形成多个岛部120。多个岛部120将GND信号从第一金属层110连接至堆叠的管芯402、502，并且将I/O信号从基部金属层102连接至堆叠的管芯402、502。
在612，钝化层122在第二金属层118之上形成，以保护第二金属层118避开其他导电层。一个或多个开口124在钝化层122中形成，以暴露第二金属层118并且提供将第一金属层110连接至堆叠的管芯402、502的机构。例如，用于半导体制造的工艺是65纳米(nm)工艺或45nm工艺，以生产65nm或45nm或更小的芯片尺寸。
描述可以使用基于视角的描述，例如上方/下方。这样的描述仅仅是为了便于讨论，而不是旨在将在此描述的实施例的应用限制在任何特定的方向。
术语芯片、管芯、集成电路、单片器件、半导体器件和芯片在微电子领域通常是可交换使用的。本发明可适用于上述所有术语，因为它们在本领域是被广泛理解的。
本公开所称的短语“A/B”表示A或B。本公开所称的短语“A和/或B”表示“(A)、(B)或(A和B)”。本公开所称的短语“A、B和C中的至少一个”表示“(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或(A、B和C)”。本公开所称的短语“(A)B”表示“(B)或(AB)”，即A是可选的元件。
以最有助于理解要求保护的主题的方式将各项操作描述为依次进行的多个分立的操作。然而，描述的顺序不应解释为暗示这些操作必须依赖于顺序。具体地，这些操作可以不以呈现的顺序执行。所描述的操作可以以与所描述的实施例不同的顺序执行。可以执行各种其他的操作和/或在另外的实施例中可以省略所描述的操作。
说明书使用了短语“在一个实施例中”、“在一些实施例中”或类似的语言，它们中的每一个可以指相同的或不同的实施例中的一个或多个。此外，针对本公开的实施例所使用的术语“包括”、“包含”、“具有”等的含义是相同的。
尽管在此已经示出和描述了某些实施例，然而在不背离本公开的范围的情况下，可以用于实现相同目的的很多可替换和/或等同实施例或实施方式来代替所示出和描述的实施例。本发明旨在覆盖在此讨论的实施例的任何修改或变化。因此显然的是，旨在仅由权利要求及其等同物对在此描述的实施例进行限定。

Claims (20)

1.一种制造芯片的方法，所述方法包括：
在第一半导体管芯之上形成基部金属层；
形成与所述基部金属层隔开的第一金属层；
在所述第一金属层中创建多个岛部，以在所述芯片中路由(i)接地信号或(ii)电源信号中的至少一个；
形成与所述第一金属层隔开的第二金属层；以及
在所述第二金属层中创建多个岛部，以在所述芯片中路由(i)所述接地信号或(ii)所述电源信号中的至少一个。
2.根据权利要求1所述的方法，其中(i)所述第一金属层至少包括下述之一：铜(Cu)、铝(Al)、铝-硅合金、铝-铜合金或镍(Ni)，并且(ii)所述第二金属层至少包括下述之一：铜(Cu)、铝(Al)、铝-硅合金、铝-铜合金或镍(Ni)。
3.根据权利要求1所述的方法，还包括在(i)所述第一金属层和(ii)所述第二金属层中的至少一个内限定开口，以提供应力消除。
4.根据权利要求1所述的方法，还包括在所述第二金属层中提供一个或多个焊盘，以在所述芯片和一个或多个外部器件之间传输信号。
5.根据权利要求1所述的方法，还包括提供电通路，以经由所述第一金属层中的所述多个岛部将所述电源信号从所述第二金属层连接至所述基部金属层。
6.根据权利要求1所述的方法，还包括提供电通路，以经由所述第二金属层中的所述多个岛部将所述接地信号从所述第一金属层连接至堆叠的管芯。
7.根据权利要求1所述的方法，还包括：
将所述芯片定位在封装的引线框上；以及
将第二半导体管芯堆叠在所述芯片的顶部。
8.根据权利要求1所述的方法，还包括：
在所述第二金属层之上形成钝化层；
在所述钝化层中创建一个或多个开口，以暴露所述第二金属层中的接触点；以及
将第二半导体管芯堆叠在所述钝化层中的所述一个或多个开口处，从而将所述第二管芯电耦合至所述芯片。
9.根据权利要求8所述的方法，其中所述第二半导体管芯通过焊接块电耦合至所述第二金属层。
10.根据权利要求8所述的方法，其中所述第二半导体管芯通过铜柱和焊接块电耦合至所述第二金属层。
11.一种芯片，包括：
形成在第一半导体管芯之上的基部金属层；
与所述基部金属层隔开的第一金属层，所述第一金属层具有多个岛部，所述多个岛部被配置为在所述芯片中路由(i)接地信号或(ii)电源信号中的至少一个；以及
与所述第一金属层隔开的第二金属层，所述第二金属层具有多个岛部，所述多个岛部被配置为在所述芯片中路由(i)所述接地信号或(ii)所述电源信号中的至少一个。
12.根据权利要求11所述的芯片，其中(i)所述第一金属层至少包括下述之一：铜(Cu)、镍、铝(Al)、铝-硅合金或铝-铜合金，并且(ii)所述第二金属层至少包括下述之一：铜(Cu)、镍、铝(Al)、铝-硅合金或铝-铜合金。
13.根据权利要求11所述的芯片，其中(i)所述第一金属层和(ii)所述第二金属层中的至少一个包括限定在其中的开口，以提供应力消除。
14.根据权利要求11所述的芯片，其中所述第一金属层中的所述多个岛部被配置为与所述第二金属层中的所述多个岛部对齐。
15.根据权利要求11所述的芯片，其中所述第一金属层被配置为在所述第一金属层的中心位置形成多个开口。
16.根据权利要求11所述的芯片，其中所述第一金属层中的所述多个岛部被配置为提供电通路，以将所述电源信号从所述第二金属层连接至所述基部金属层。
17.根据权利要求11所述的芯片，其中所述第二金属层中的所述多个岛部被配置为提供电通路，以将所述接地信号从所述第一金属层连接至堆叠在所述芯片的顶部的第二半导体管芯。
18.根据权利要求11所述的芯片，其中：
所述第一金属层是接地平面，并且
所述第二金属层是电源平面。
19.根据权利要求11所述的芯片，还包括：
绝缘层，被配置为将所述基部金属层与所述第一金属层隔开；
电介质层，被配置为将所述第一金属层与所述第二金属层隔开；以及
钝化层，被配置为保护所述第二金属层免于暴露。
20.根据权利要求11所述的芯片，还包括：
形成在所述第二金属层之上的钝化层，所述钝化层被配置为在所述钝化层中形成一个或多个开口，以暴露所述第二金属层中的接触点；以及
第二半导体管芯，所述第二半导体管芯被配置为堆叠在所述钝化层中的所述一个或多个开口上，从而将所述第二半导体管芯电耦合至所述芯片，
其中所述第二半导体管芯通过(i)焊接块或(ii)铜柱和焊接块之一被电耦合至所述第二金属层。
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