CN102790030A - 具有偏置钝化以减少电迁移的半导体结构 - Google Patents

具有偏置钝化以减少电迁移的半导体结构 Download PDF

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Publication number
CN102790030A
CN102790030A CN2012101562647A CN201210156264A CN102790030A CN 102790030 A CN102790030 A CN 102790030A CN 2012101562647 A CN2012101562647 A CN 2012101562647A CN 201210156264 A CN201210156264 A CN 201210156264A CN 102790030 A CN102790030 A CN 102790030A
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tsv
conductive
conductive gasket
semiconductor structure
gasket
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CN102790030B (zh
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M·J·英特兰特
G·拉封唐
M·J·沙皮罗
T·A·瓦西克
B·C·韦伯
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Sony Corp
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International Business Machines Corp
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Abstract

一种半导体结构，其中包括三维结构的多个堆叠的半导体芯片。第一半导体芯片与第二半导体芯片相接触。第一半导体芯片包括：延伸穿过第一半导体芯片的硅通孔(TSV)；第一半导体芯片表面上的导电衬垫，TSV以接触到导电衬垫的第一侧面而终止；覆盖导电衬垫的钝化层，钝化层具有多个开口；以及形成在多个开口内并且与导电衬垫的第二侧面相接触的多个导电结构，多个导电结构与导电衬垫的接触相对于TSV与导电衬垫的接触而偏置。

Description

具有偏置钝化以减少电迁移的半导体结构
背景技术
示范性实施例主要涉及三维半导体集成结构，并且更具体地涉及具有硅通孔结构和偏置钝化以减少电迁移的三维半导体集成结构。
在半导体技术中，硅通孔(TSV)，也被称为基板通孔，是一种在半导体基板(晶片/芯片)内形成的导电特征。TSV特征垂直穿过半导体基板，提供堆叠晶片/芯片的封装方法并允许在独立晶片或芯片内的电路之间的电连接。
现有多种用于制作TSV的方法。通常，在半导体基板内蚀刻出孔，并且有时孔也要穿过互连的结构。孔随后即可内衬以各种绝缘层和/或各种金属层。孔随后被填充有通常是铜(Cu)的导电材料，这些导电材料就成为TSV的主要部分。某些TSV与半导体基板电接触，而另一些TSV则被电绝缘。蚀刻孔内的任何材料均可被认为是TSV的一部分，因此完整的TSV可以包括Cu加内衬，并且或许还可以包括绝缘层。
TSV可以终止于接合衬垫。焊球，也被称为C-4连接，可以接触接合衬垫并将一个半导体芯片的接合衬垫连接至另一个半导体芯片或封装的接合衬垫。用这种方式，即可在封装上堆叠多个芯片以构成三维的硅集成结构。
尽管常规通孔与硅通孔共享有一定的名称类似性，但这是基本无关的不同结构。常规通孔连接管芯或互连结构(例如封装)内的导线并且可以仅穿过单个介电层。常规通孔处于它们所连接的金属线的尺寸量级，通常在最坏情况下也在厚度的三倍到四倍因数以内。TSV则必须穿过整个半导体基板，可以比常规通孔的直径大三十倍。
电迁移可以在承载电流的任何导电材料例如TSV结构或金属化层中发生。电迁移是由电子在导体内的渐进移动造成的材料移位。这种材料移位可能最终会在导电材料中造成导致其他连接点处电阻更高的间隙或空洞，或者会在所有连接失效时造成开路故障。为了减少这种空洞的出现，已有限制导电材料中所允许电流量的规则。这样的电迁移基本规则在本领域内是公知的。
发明内容
如上和如下所述示范性实施例的各种优点和用途通过根据示范性实施例的第一种应用提供一种半导体结构来实现，其中包括延伸穿过半导体结构的硅通孔(TSV)；半导体结构表面上的导电接合衬垫，TSV以接触到导电接合衬垫的第一侧面而终止；覆盖导电接合衬垫的钝化层，钝化层具有多个开口；以及形成在多个开口内并且与导电接合衬垫的第二侧面相接触的多个导电结构，多个导电结构与导电接合衬垫的接触相对于TSV与导电接合衬垫的接触而偏置。
根据示范性实施例的第二种应用，提供了一种半导体结构，其中包括三维结构的多个堆叠的半导体芯片。第一半导体芯片与第二半导体芯片相接触。第一半导体芯片包括延伸穿过第一半导体芯片的硅通孔(TSV)；第一半导体芯片表面上的导电接合衬垫，TSV以接触到导电接合衬垫的第一侧面而终止；覆盖导电接合衬垫的钝化层，钝化层具有多个开口；以及形成在多个开口内并且与导电接合衬垫的第二侧面相接触的多个导电结构，多个导电结构与导电接合衬垫的接触相对于TSV与导电接合衬垫的接触而偏置。
根据示范性实施例的第三种应用，提供了一种减少半导体芯片内的电迁移的方法。所述方法包括：获取一种半导体结构，其中包括延伸穿过半导体结构的硅通孔(TSV)，半导体结构表面上的导电接合衬垫，TSV以接触到导电接合衬垫的第一侧面而终止，以及覆盖导电接合衬垫的钝化层；在钝化层内形成多个开口；然后将多个导电结构形成在多个开口内并且与导电接合衬垫的第二侧面相接触，多个导电结构与导电接合衬垫的接触相对于TSV与导电接合衬垫的接触而偏置。
附图简要说明
示范性实施例中确信为新颖的特征和示范性实施例中的要素特征均在所附权利要求中予以具体阐述。附图仅仅是为了进行图解而并非按比例绘制。既涉及结构又涉及操作方法的示范性实施例可以通过参照以下结合附图给出的详细说明而得到更好的理解，在附图中：
图1示出了常规的三维(3-D)半导体集成结构。
图2是可以在图1的3-D集成结构中使用的常规半导体芯片的截面图。
图3是图2中的常规半导体芯片将焊球移除后的底视图。
图4是可以在图1的3-D集成结构中使用的半导体芯片示范性实施例的截面图。
图5是图4中的半导体芯片将焊球移除后的底视图。
图6示出了用于图2和图3中的常规半导体芯片的电迁移模型。
图7示出了用于图3和图4中的半导体芯片示范性实施例的电迁移模型。
具体实施方式
更加详细地参照附图，并且具体参照图1，示出了常规的3-D半导体集成结构100，其中可以包括互连结构或封装102，连接至封装102的第一半导体芯片104以及堆叠在第一半导体芯片104上的至少一个附加的半导体芯片106。
封装102可以是包括塑料封装、FR-4封装和陶瓷封装在内的任意常规的半导体封装。在封装102底部上可以有用于连接至下一级封装例如母板的焊球108。在封装102顶部上可以有用于容纳第一半导体芯片104的衬垫(未示出)。应该理解的是，尽管3-D集成结构100包括封装102，但是存在或者缺少任何类型的封装对于示范性实施例来说并不重要。
第一半导体芯片104可以包括用于将半导体芯片104连接至封装102上的衬垫(未示出)的焊球。半导体芯片104还可以包括一个或多个贯通的TSV 112，用于在封装102和第二半导体芯片106之间提供功率或信号连接。
第一半导体芯片104上堆叠的是第二半导体芯片106，它也可以具有用于将第二半导体芯片106连接至第一半导体芯片104上的衬垫(未示出)的焊球114。第二半导体芯片106也可以具有一个或多个TSV 116，用于在第一半导体芯片104和可以在3-D半导体集成结构100中存在的任何附加的半导体芯片120之间提供功率或信号连接。任何附加的半导体芯片120也都可以具有这样的TSV。
现参照图2，示出了常规半导体芯片200放大的截面图。半导体芯片200可以是图1中为了说明而非限制性地示出的任何半导体芯片，半导体200示出了第一半导体芯片104的一部分。半导体芯片200可以包括接合衬垫202，在接合衬垫202上界定出开口206的钝化层204以及用于将半导体芯片200连接至封装或另一个半导体芯片的焊球208。构成衬垫202和钝化层204的材料通常可以分别是金属材料(例如铜)和非金属材料(例如氮化物或氧化物)，并且对于示范性实施例来说并不重要。
半导体芯片200进一步包括终止在接合衬垫202第一侧上一端的TSV 210。TSV 210在另一端也可以终止于接合衬垫(未示出)。开口206位于接合衬垫202的第二侧上。应该注意的是，TSV 210的印迹大致与开口206的中心对齐，正如图3中清楚看到的那样。
图3示出了半导体芯片200的移除焊球208后的底视图。钝化层204中的开口206暴露出接合衬垫202用于与焊球208相连。以虚线示出的TSV 210的印迹处于开口206内。
半导体芯片200的设计在接合衬垫202上造成可能会导致电迁移问题的高电流密度。
芯片到芯片和芯片到封装连接中的电迁移和高电流在大功率微电子学中可能会成为问题。因为底部芯片可能承载用于叠层内所有其他芯片的全部功率，所以该问题在3D半导体集成结构中可能会恶化。3D半导体集成结构中的另一个问题可能是TSV经常对齐在衬垫正下方。因为在芯片的外层和TSV的末端之间几乎没有连线，所以电流会集中至TSV区域。
示范性实施例被设计用于解决常规3-D半导体集成结构的电迁移问题。
现参照图4，示出了半导体芯片400的示范性实施例放大的截面图。半导体芯片400可以替代图1中所示的任何或全部的半导体晶片。最优选的是，半导体芯片400作为3-D半导体集成结构中的底部芯片，原因在于此处接合衬垫上的电流密度可能最高并且因此电迁移可能最大。半导体芯片400可以包括接合衬垫402，在接合衬垫404上界定出开口406的钝化层404以及用于将半导体芯片400连接至封装或另一个半导体芯片的焊球408。构成接合衬垫402和钝化层404的材料通常可以分别是金属材料(例如铜)和非金属材料(例如氮化物或氧化物)，并且对于示范性实施例来说并不重要。
半导体芯片400进一步包括终止在接合衬垫402第一侧416上一端的TSV 410。TSV 410在另一端也可以终止于接合衬垫(未示出)。开口406位于接合衬垫402的第二侧418上。在示范性实施例中，TSV 410的印迹相对于开口406偏置，正如图5中清楚看到的那样。TSV 410的印迹可以被界定为接合衬垫402的第一侧416上的接触区域，与接合衬垫402的第二侧418并置，就像TSV 410是与接合衬垫402的第二侧418相接触一样。
图5示出了半导体芯片400的移除焊球408后的底视图。钝化层404中的开口406暴露出接合衬垫402用于与焊球408相连。以虚线示出的TSV 410的印迹相对于开口406偏置并且由钝化层404覆盖。为了说明而非限制性地，在图5中示出了四个开口406。可以有多于四个开口406或者少于四个开口406，但是最少也应该有至少两个这样的开口406。
开口406可以对称地设置在TSV 410的印迹周围。也就是说，开口406可以用如箭头412所示的尺寸与TSV 410的印迹相等地间隔开，以及用如箭头414所示的尺寸与接合衬垫402的边缘相等地间隔开。开口406必须与TSV 410的印迹间隔至少一定的距离412以避免电流集中导致电迁移问题的恶化。
根据示范性实施例，来自TSV 410的电流将在接合衬垫402处离开，沿接合衬垫402横向(水平)行进并随后通过开口406离开进入焊球408内。因此即可避免TSV 410接触接合衬垫402的地方出现任何的电流集中。
为了说明而非限制性地，TSV 410可以具有约20微米的直径并且因此也可以在接合衬垫402的第二侧418上具有约20微米的印迹。为了说明而非限制性地，图5中示出的四个开口406可以相应地具有约18微米的直径，与TSV 410的印迹间隔约5微米(图5中的尺寸412)并且与接合衬垫402的边缘间隔约4微米(图5中的尺寸414)。
根据本发明的教导，本领域技术人员可以选择开口406的最佳尺寸、与TSV 410印迹的间隔(尺寸412)以及与接合衬垫402的边缘的间隔(尺寸414)。同样，为了避免任何集中的电流进入接合衬垫402的中心，尺寸412不能为使得开口与TSV 412的印迹接触或重叠的零或负值。
进行电迁移建模用于设计，其中类似于图2和图3中所示常规的设计，钝化层内的开口在TSV印迹正上方。TSV在仿真中被假定为具有300mA(毫安)的电流和20μm(微米)的直径。TSV上的钝化层内的开口具有45μm的直径。图6中示出了电迁移模型的结果。图6左侧的表框示出了图6中不同位置的电流密度，其中电流密度在图6的中心最大。图6中的接合衬垫在电流集中在接合衬垫中心时对于300mA的电流具有112μA/μm2(微安每平方微米)的最大电流密度，或者对于150mA的电流具有56μA/μm2的最大电流密度。
对另一种电迁移进行建模以用于设计，其类似于图4和图5中所示示范性实施例，在钝化层内具有相对于TSV印迹偏置的四个开口。TSV在仿真中被假定为具有150mA(毫安)的电流和20μm(微米)的直径。钝化层具有直径约为18μm的四个开口，其中每一个开口都与TSV的印迹间隔约5μm(图5中的尺寸412)并且与接合衬垫的边缘间隔约4μm(图5中的尺寸414)。图7中示出了电迁移模型的结果。图7左侧的表框示出了图7中不同位置的电流密度，其中最大的电流密度从图7的中心偏离。图7中的接合衬垫对于150mA的电流具有36μA/μm2的电流密度，其中电流在接合衬垫上更加分散。
将图6中的现有技术实施例与图7中的示范性实施例相比，电流密度减小了约35%。
对于已经理解了本公开的本领域技术人员而言，显而易见的是可以在本文中具体介绍的那些实施例以外得到示范性实施例的其他变形而并不背离本发明的实质。因此，应该认为这样的变形是落在本发明仅由所附权利要求限定的保护范围内。

Claims (16)

1.一种半导体结构，包括：
延伸穿过半导体结构的硅通孔TSV；
半导体结构表面处的导电衬垫，TSV以接触到导电焊盘的第一侧而终止；
覆盖导电衬垫的钝化层，所述钝化层具有多个开口；以及
形成在多个开口内并且与所述导电衬垫的第二侧相接触的多个导电结构，所述多个导电结构与导电衬垫的接触相对于TSV与所述导电衬垫的接触偏置。
2.如权利要求1所述的半导体结构，其中多个导电结构与导电衬垫的边缘以预定的距离间隔开。
3.如权利要求1所述的半导体结构，其中多个导电结构相对于TSV以预定的距离偏置。
4.如权利要求1所述的半导体结构，其中TSV具有相对于导电衬垫的印迹，印迹被界定为TSV在导电衬垫第一侧上的接触区域，与导电衬垫第二侧并置，就像TSV是与导电衬垫的第二侧相接触一样，并且其中多个导电结构不接触或覆盖TSV的印迹。
5.如权利要求1所述的半导体结构，其中多个导电结构包括至少两个这样的导电结构。
6.如权利要求1所述的半导体结构，其中电流从半导体结构穿过TSV沿导电衬垫横向行进预定距离并随后穿过多个导电结构。
7.一种半导体结构，包括：
三维结构的多个堆叠的半导体芯片；
与第二半导体芯片相接触的第一半导体芯片，所述第一半导体芯片包括：
延伸穿过所述第一半导体芯片的硅通孔TSV；
第一半导体芯片表面处的导电衬垫，所述TSV以接触到导电衬垫的第一侧而终止；
覆盖导电衬垫的钝化层，所述钝化层具有多个开口；以及
形成在多个开口内并且与导电衬垫的第二侧相接触的多个导电结构，多个导电结构与导电衬垫的接触相对于TSV与导电衬垫的接触偏置。
8.如权利要求7所述的半导体结构，其中第二半导体芯片包括：
延伸穿过第二半导体芯片的硅通孔TSV；
第二半导体芯片表面处的导电衬垫，所述TSV以接触到导电衬垫的第一侧而终止；
覆盖导电衬垫的钝化层，所述钝化层具有多个开口；以及
形成在多个开口内并且与导电衬垫的第二侧相接触的多个导电结构，所述多个导电结构与导电衬垫的接触相对于所述TSV与导电衬垫的接触偏置。
9.如权利要求7所述的半导体结构，其中多个导电结构与导电衬垫的边缘以预定的距离间隔开。
10.如权利要求7所述的半导体结构，其中多个导电结构相对于所述TSV以预定的距离偏置。
11.如权利要求7所述的半导体结构，其中TSV具有相对于导电衬垫的印迹，印迹被界定为TSV在导电衬垫第一侧上的接触区域，与导电衬垫第二侧并置，就像TSV是与导电衬垫的第二侧相接触一样，并且其中多个导电结构并不接触或覆盖TSV的印迹。
12.如权利要求7所述的半导体结构，其中多个导电结构包括至少两个这样的导电结构。
13.如权利要求7所述的半导体结构，其中电流从半导体结构穿过TSV，沿导电衬垫横向行进预定距离并随后穿过多个导电结构。
14.如权利要求7所述的半导体结构，其中多个导电结构与第二半导体芯片形成电接触。
15.如权利要求7所述的半导体结构，进一步包括封装基板，并且其中多个导电结构与封装基板形成电接触。
16.一种减少半导体芯片内的电迁移的方法，所述方法包括：
获取一种半导体结构，其中包括延伸穿过半导体结构的硅通孔TSV，半导体结构表面处的导电衬垫，TSV以接触到导电衬垫的第一侧而终止，以及覆盖导电衬垫的钝化层；
在钝化层内形成多个开口；以及
将多个导电结构形成在多个开口内并且与导电衬垫的第二侧相接触，多个导电结构与导电衬垫的接触相对于TSV与导电衬垫的接触偏置。
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