TWI566366B - 晶片的電源／接地佈局 - Google Patents

晶片的電源／接地佈局 Download PDF

Info

Publication number
TWI566366B
TWI566366B TW100138127A TW100138127A TWI566366B TW I566366 B TWI566366 B TW I566366B TW 100138127 A TW100138127 A TW 100138127A TW 100138127 A TW100138127 A TW 100138127A TW I566366 B TWI566366 B TW I566366B
Authority
TW
Taiwan
Prior art keywords
metal layer
wafer
layer
islands
aluminum
Prior art date
Application number
TW100138127A
Other languages
English (en)
Other versions
TW201225240A (en
Inventor
秀文 周
韓忠群
李维旦
游淑華
鄭全成
亞伯 吳
Original Assignee
馬維爾國際貿易有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 馬維爾國際貿易有限公司 filed Critical 馬維爾國際貿易有限公司
Publication of TW201225240A publication Critical patent/TW201225240A/zh
Application granted granted Critical
Publication of TWI566366B publication Critical patent/TWI566366B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/45111—Tin (Sn) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/45116—Lead (Pb) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48624—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48647—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48717—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48724—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48699—Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48738—Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48747—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48817—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
    • H01L2224/48824—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48799—Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838—Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48847—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06527—Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10252—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1027—IV
    • H01L2924/10271—Silicon-germanium [SiGe]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Description

晶片的電源/接地佈局 【相關申請的交叉引用】
本申請要求於2010年10月20日提交的美國臨時專利申請61/405,099的優選權，其整個說明書在這裏通過引用全部併入本文，除了那些與本說明書不一致的部分，如果有的話。
本發明實施方案涉及晶片封裝領域，更具體地，涉及使用引線結合封裝的電源/接地佈局。
隨著社會變得更有流動性，較小電子裝置越來越普及。該較小電子裝置的普及創建了提供高性能和良好可靠性的小型照明裝置的需求。為了幫助滿足該需求，將縮減用於這樣較小電子裝置中的電子封裝元件內的半導體晶片或晶片的大小尺寸。然而，該削減的大小尺寸挑戰用於該電子封裝元件中半導體晶片或晶片的電源和/或接地信號的常規路由配置。
另外，另一挑戰是增加輸入/輸出(I/O)功能以容納用在這樣的小型電子裝置中所使用的先進技術。該先前技術依靠該I/O功能的增長以避免在該半導體晶片或晶片中接觸件或連接件兩端電壓的下降。還有，另一挑戰是保持該半導體晶片或晶片的製造成本相對低，當提供解決方案給這些挑戰時候。另外，倒裝晶片封裝設置會是昂貴的。引線結合技術的使用能夠幫助減少各種封裝設置的成本。
本發明提供了一種製作晶片的方法。該方法包括在第一半導體晶片上形成基層金屬層，在該基層金屬層上形成第一金屬層並在該第一金屬層中創建各個島以路由在該晶片中的(i)接地信號或(ii)電源信號的至少一個。該方法進一步包括在該第一金屬層上的第二金屬層，創建了該第二金屬層中的多個島以路由在該晶片中的(i)接地信號或(ii)電源信號的至少一個。
本發明也提供了一種包括形成在第一半導體晶片上的基層金屬層和形成在該基層金屬層上的第一金屬層的晶片。該第一金屬層包括多個島，配置用來路由在該晶片中的(i)接地信號或(ii)電源信號的至少一個。該晶片進一步包括形成在該第一金屬層上的第二金屬層。該第二金屬層包括多個島，配置用來路由在該晶片中的(i)接地信號或(ii)電源信號的至少一個。
附圖簡要說明
通過結合附圖的下列具體說明將更輕易地理解本發明的實施方案。為了促進該說明，相同參考編號指示相同結構元件。在該附圖的各個圖中通過實例的方式而不是限制性的方式來描述此處的實施方案。
圖1A-1G描述了製造晶片電源/接地佈局的各個階段的代表性側視圖。
圖2描述了圖1A-1G的晶片的頂視圖。
圖3描述了包括圖1A-1G的晶片的電子封裝元件的代表性視圖。
圖4描述了具有堆在頂部的另一晶片的圖1A-1G的晶片的代表性側視圖。
圖5描述了具有堆在頂部的另一晶片的圖1A-1G的晶片的另一設置的代表性側視圖。
圖6描述了用來製造圖1A-1G的晶片的電源/接地佈局的方法的過程流程圖。
積體電路或晶片包含在許多電子裝置中如，例如，手機，電腦，收音機，普通家用電器等。晶片包括半導體晶片，其由其中實施電子電路的半導體材料所製成。該晶片也包括容納該半導體晶片並包括各種材料以將該晶片的電子互連提供給外部電子元件的封裝。例如，引線結合是提供該晶片電子互連的本發明中的過程。
圖1A-1G描述了製造晶片100的電源/接地佈局的各個階段的代表性側視圖。圖1A描述了形成在半導體晶片104上的基層金屬層102。該基層金屬層102可包括，例如，鋁(Al)，鋁銅合金，銅(Cu)，或鎳(Ni)。該半導體晶片104包括，例如，矽(Si)，矽鍺(SiGe)，鍺(Ge)，砷化鎵(GaAs)等。在實施方案中，可通過如，例如電沉積，蒸發或噴鍍過程的過程來沉積該基層金屬層102。在另一實施方案中，可化學地和機械地平面化該基層金屬層102。本領域技術人員熟悉這樣的過程並因而，此處將不對這些過程進行描述。
在實施方案中，該基層金屬層102提供該晶片100、更具體地該半導體晶片104的輸入/輸出(I/O)功能。該基層金屬層102也用作該晶片100的再分配層(RDL)。因而，使用各個描記線和線條配置該基層金屬層102以處理電子信號。該基層金屬層102和半導體晶片104電性地相互連接使得該電子信號能夠通過他們之間。
圖1B描述了形成在該基層金屬層102上的絕緣層106。可使用包括環氧樹脂，聚醯亞胺，低介電常數介電材料，二氧化矽(SiO2)等任意介電材料來形成該絕緣層106。該絕緣層106將該晶片100的導電部分或層相互分開並包含該基層金屬層102離開該晶片100的其他導電金屬層。
多個裝置特徵可形成於該絕緣層106中，該裝置特徵可包括，例如，可粘結描記線，多個線條和多個通孔108。如圖所示，該通孔108用作該絕緣層106中的連接件以允許在該晶片100的不同層之間的導電連接。例如，該通孔108用作由該基層金屬層102到不同導體如該晶片100的附加基層金屬層的接觸件。在實施方案中，該通孔108由金屬構成，如本領域已知的一樣。
圖1C描述了形成在該絕緣層106上的第一金屬層110。該第一金屬層110可包括，例如，銅(Cu)，鋁(Al)，鋁銅合金，鋁矽合金，或鎳(Ni)。
在實施方案中，電鍍過程，電化學沉積過程，或噴鍍過程將該第一金屬層110沉積在該絕緣層106上。在又一實施方案中，鑲嵌金屬過程沉積用作該絕緣層106上第一金屬層110的銅薄層。在一些實施方案中可化學地和機械地平面化該第一金屬層110。本領域技術人員熟悉這樣的過程並因而，此處將不對這些過程進行描述。
由一個或多個開口113所定義的多個島112形成於該第一金屬層110中。如果需要，這些島112可具有彼此相互不同的尺寸和/或形狀。例如，該多個島112一般具有基本上的矩形。在實施方案中，該多個島112的形狀可包括但不限於，基本上正方形，基本上橢圓形，和基本上圓形。
在實施方案中，該多個島112位於該第一金屬層110的中心。該多個島112提供了在該晶片100的層之間的電性通道。該多個島112，如該開口113一樣，也提供關於該第一金屬層110的應力消除。該多個島112的中心位置導致這些層之間的較短電性路徑，如此處將進一步具體討論的一樣。該較短電性路徑導致更好的電性性能，基於正生成的較少的電感和電阻。
在實施方案中，該第一金屬層110是穩定的接地(GND)層。該第一金屬層110將該GND層上面的信號與該GND層下面的信號隔離開。特別地，該第一金屬層110將隔離在該半導體晶片104內以下的信號的雜訊，尤其在高電流切換期間。配置該第一金屬層110中的多個島112用來連接信號，例如，如VDD，通過該第一金屬層110從另一個層島該半導體晶片104，或來自該基層金屬層102處的I/O信號，這裏將進一步進行具體討論。作為穩定的接地(GND)層的第一金屬層110有助於減少在該晶片100內電壓的下降。
圖1D描述了在該第一金屬層110上形成的介電層114。該介電層114可由任意介電材料所構成，包括，例如氧化物，聚醯亞胺，低介電常數介電材料，二氧化矽(SiO2)等。該介電層114將該晶片100內的導電部分或層相互分離並保護該第一金屬層110離開另一個導電金屬層。在實施方案中，該介電層114是夾層介電層。
在該介電層114中可形成多個裝置特徵。該裝置特徵可包括，例如，可粘結描記線，多個線條和多個通孔116。該通孔116是該介電層114中的連接件以將該第一金屬層110和該基層金屬層102連接島不同導體，如該晶片100內的附加金屬層。在實施方案中，該通孔116由金屬構成，如本領域已知的一樣。
在實施方案中，可將該介電層114中的通孔116定位在對應於該絕緣層106和島112的通孔108位置的位置中。換句話說，可將該通孔108,116和島112放在他們各自層的相同位置中使得他們基本上對齊。
圖1E描述了形成於該介電層114之上的第二金屬層118。該第二金屬層118可包括，例如，鋁(Al)，鋁銅合金，鋁矽合金，鎳(Ni)或銅(Cu)。在實施方案中，該第二金屬層118可形成於該介電層114之上，使用公知的合適的過程，例如，物理氣相沉積(PVD)過程噴鍍過程，電沉積，或蒸發澱積。本領域技術人員熟悉這樣的過程並因而，此處將不對這些過程進行描述。
多個島120形成在該第二金屬層118上以提供應力消除並提供電性通道。如果需要，該島120可具有彼此相互不同的大小和/或形狀。例如，該多個島120具有基本上的矩形。在實施方案中，該多個島120的形狀可包括但不限於，基本上正方形，基本上橢圓形，和基本上圓形。
在實施方案中，該多個島120位於該第二金屬層118的中心。該多個島120的中心位置提供了從該第二金屬層118到推積在該晶片100頂部之上的晶片的較短電性路徑，如此處將進一步具體描述的一樣。該較短電性途徑提供了較好的電性性能，基於正生成的較少電感和電阻。在實施方案中，將在該第二金屬層118中的多個島120的一些定位在對應該第一金屬層110的多個島112一些的位置的位置中。換句話說，將該多個島120,112的一些定位在他們各自金屬層118,110每一個上的相同位置中使得他們基本對齊。
在實施方案中，該第二金屬層118用作電源層，將其配置用來在該晶片100頂部上提供電源。該第二金屬層118從外部裝置(未示出)處通過引線結合連接來接收電源並通過該通孔108,116和採用該通孔108,116對齊的島112和120以及通過該基層金屬層102將電源提供給該半導體晶片104，其用作為RDL。
圖1F描述了形成於該第二金屬層118之上的鈍化層122。可使用包括例如氧化物，氮化物，氧化矽，氮化矽等的任意合適材料來形成該鈍化層122。一般可化學地和機械地平面化該鈍化層122。如果需要，該鈍化層122不需要被平面化。該鈍化層122保護該下層的金屬層和該精細線路的金屬互連。該鈍化層122也組織預防該移動離子的穿透和其他污染。
圖1G描述了在該鈍化層122中的一個或多個開口124。在該鈍化層122中的一個或多個開口124露出該第二金屬層118中的接觸點以減少熱量來為該晶片100提供較好的散熱能力。該一個或多個開口124也露出島120。另外，該一個或多個開口124露出該第二金屬層118以電性連接可被堆積在該晶片100上的另一晶片(未圖示)，如此處將進一步討論的一樣。
因而，如可看到的一樣，該晶片100包括分開的接地和電源層(如，分別地，該第一金屬層110和該第二金屬層118)以將接地和/或電源信號提供給該半導體晶片104。該分開的接地和電源層也將接地和/或電源信號提供給其他晶片，如此處將進一步具體描述的一樣。
圖2描述了圖1的晶片100的頂視圖。該鈍化層122在圖2中為了清晰目的而未被繪出。該頂視圖描述了該基層金屬層102的露出部分，該第二金屬層118，和該第一金屬層110的露出部分，如該第二金屬層118中的多個島120，和該鈍化層122中的一個或多個開口124一樣。該基層金屬層102和該第一金屬層110的露出部分位於沿著該晶片100的週邊以允許到該各個層的引線結合連接。
該多個島120提供了電性通道並提供了應力消除。類似地，該一個或多個開口124提供了應力消除。例如，該第二金屬層118中的應力來自熱膨脹差異或來自該第二金屬層118的微觀結構(內在應力)。該多個島120的位置以實例來示出，而不是確切的放置位置。該多個島120進一步表示了沒有限制數量的實例，其可形成於該第二金屬層118中，如沒有限制大小，尺寸或形狀一樣。
圖2進一步描述了多個接觸點的實例。例如，該接觸點提供了在多個位置處與耦合該鍵合引線212的粘結墊206,208,210進行的電性連接。該粘結墊206,208,210一般位於沿著該半導體晶片104的外部設備的邊緣，在該各個金屬層102,110和118的露出部分上。例如，粘結墊206位於該第二金屬層118上，粘結墊208位於該第一金屬層110的露出部分上，粘結墊210位於該基層金屬層102的露出部分。
在實施方案中，在位於該第二金屬層118上的粘結墊206處通過該鍵合引線212接收來自外部裝置(未圖示)的VDD電源。從該第二金屬層118將該VDD電源提供給該基層金屬層102，通過由通孔116，島112和通孔108所定義的通道(如圖1B-1E所示)。隨後從該基層金屬層102處將該VDD電源提供給該半導體晶片104，通過在該基層金屬層102和該半導體晶片104之間的電性連接(未圖示)。在該晶片100中提供隔離以避免不需要的元件之間的互動。例如，該通孔108，116形成與該第一金屬層110的接觸，其用作向這些信號表現為無窮的接地電勢的GND層。
在另一實施方案中，在該第一金屬層110的粘結墊208處通過該鍵合引線212來接收該GND信號。隨後可將該GND信號提供給該基層金屬層102，通過通孔108，並據此提供給該半導體晶片104。另外，該多個島120提供了從該第一金屬層110島到可堆積在該晶片100頂部上的另一晶片處的GND信號的電性通道。例如，該GND信號的電性通道包括該第一金屬層110到該通孔116(在代表性視圖的圖1E-1G中所述)，到島120，通過在該鈍化層122中的開口124，並到堆積在該晶片100頂部上的另一晶片，如此處將進一步描述的一樣。
另外，可在該基層金屬層102的粘結墊210處通過該鍵合引線212來接收I/O信號，或來自外部裝置(未圖示)或來自該半導體晶片104。同樣，可將I/O信號從該半導體晶片104處通過該基層金屬層102到該第二金屬層118和/或到堆積在該晶片100頂部上的另一晶片。例如，該I/O信號的電性通道開始於該基層金屬層102處，通過該通孔108(在代表性視圖的圖1B-1G中所述)，並通過該第一金屬層110(即該GND層)中的島112。該電性通道進一步通過該通孔116(在代表性視圖的圖1E-1G中所述)，到該第二金屬層118(即該電源層)，並到堆積在該晶片100頂部上的另一晶片。
圖3描述了包括該晶片100的電子封裝元件300的代表性視圖。在實施方案中，該電阻封裝元件300包括安裝在引線框302上的晶片100，一個或多個鍵合引線212，一個或多個位於該第二金屬層118上的粘結墊206，一個或多個引線手指304，和模塑膠306。
該引線框302可由金屬框構成以支撐該用於封裝的半導體晶片104。可採用但不限於銅或銅合金來製造該引線框302。因為該晶片100包括接地層(如，第一金屬層110)和電源層(如，第二金屬層118)，引線框302不需要包括接地層或電源層。
可在該粘結墊206和該引線手指304之間形成該鍵合引線212。該鍵合引線212的終點可以是球，楔，或其他配置，如本領域已知的一樣，並使用引線接合機器來形成。該鍵合引線212可由包括但不限於，鋁(Al)，銅(Cu)，金(Au)，銀(Ag)，錫鉛合金或鋁合金的材料構成。該粘結墊206可由鋁(Al)，銅(Cu)或其他導電特性已知的合適材料構成。
模塑膠306封裝該鍵合引線212和該半導體晶片104。該模塑膠306一般包括電性絕緣材料，如熱固性樹脂，其被處理用來保護該半導體晶片104避免潮氣，氧化或與處理相關的切斷。在另一實施方案中，處理該模塑膠306用來基本填滿在該第二金屬層118和另一晶片之間的區域。
圖3描述了包括具有構建其上的積體電路的表面的活性側308(如，前側)和沒有任意構建其上的電路的表面的非活性側310(如，後側)的半導體晶片104。通過位於該基層金屬層102的露出部分的粘結墊206(如圖2所示)電性地可訪問該積體電路。提供該鍵合引線212以將該晶片100的基層金屬層102上的粘結墊206連接到該引線框302的合適引線手指304。另外，該半導體晶片104的活性側308基本上與該第一金屬層110和該第二金屬層118平行。
在實施方案中，配置在該第一金屬層110中的多個島112的一些用來將I/O信號連接到和/或提供訪問到該晶片104的活性側308，從該基層金屬層102到其他堆積的晶片應用，通過通孔116,108和島120，如由作為通道的312所述之一樣。這將在此處進一步討論。另外，配置該第二金屬層118中的多個島120的一些以將來自該第一金屬層110處的GND信號連接島其他堆積晶片應用，通過通孔116，如由作為通道的314所述之一樣，並如在此處將進一步討論的一樣。該其他堆積的晶片應用可包括，例如，動態隨機訪問記憶體(DRAM)，快閃記憶體堆積晶片，或倒裝晶片。將該VDD電源信號從該第二金屬層118處提供給該基層金屬層102，通過由通孔116，島112和通孔108所定義的通道316。
該第一金屬層110和該第二金屬層118的作用可能對調使得該第一金屬層110是該電源層，該第二金屬層118是該GND層。因而，該第一金屬層110中的多個島112和該第二金屬層118中的多個島120的作用將對調使得配置該第一金屬層110中的多個島112以將該GND信號通過其他層路由，配置該第二金屬層118中的多個島120以將該電源和I/O信號通過該金屬層路由。為了清晰，該具體說明將繼續以該第一金屬層110是該GND層和該第二金屬層118是該電源層的方式來描述該實施方案。
圖4描述了其中將第二晶片402堆積在該晶片100頂部上的封裝設置400的代表性側視圖。將在給定封裝中容納超過一個晶片稱為“系統封裝”(SIP)或三維積體電路。這樣的封裝設置提供了極大的空間節省，通過將多個分別製造的實施不同功能的晶片組裝到單個封裝中以產生複雜電子消費品。圖4描述了以垂直方式堆積的兩個晶片，但可包括以垂直和水準集成設置堆積的多個晶片的晶片堆積。
該鈍化層122提供了一個或多個開口124以露出在該第二金屬層118中的接觸點404。該接觸點404位於將電源從該第二金屬層118提供到該第二晶片402處的點。該接觸點404也位於相應的島120處以允許接地信號從該第一金屬層110處被提供給該第二晶片402並允許I/O信號被提供在該第二晶片402和該基層金屬層102並據此該半導體晶片104之間。互利結構406如，例如，凸塊，墊，立柱，支柱，球或電性將該晶片100耦合該第二晶片402的任意適合結構，可用來路由在該接觸點404和該第二晶片402之間的電性信號。該第二晶片402通過該鍵合引線212連接到該引線框302。可將該第二晶片402堆積在該晶片100上，通過，例如，倒裝晶片過程。如圖4中可看到的一樣，該第二晶片402耦合該晶片100，使用以耦合墊410的焊接凸塊408的形式的互聯結構406。
圖5描述了其中將第二晶片502堆積在該晶片100頂部上的封裝設置500的另一代表性側視圖。圖5描述了兩個以垂直方式堆積的晶片，但可包括在垂直和/或水準集成設置中的多個晶片的堆積。
該鈍化層122創建了該一個或多個開口124以露出在該第二金屬層118中的接觸點504。該接觸點504位於將電源從該第二金屬層118提供到該第二晶片502的點。該接觸點504也位於相應的島120處以允許接地信號從該第一金屬層110處被提供給該第二晶片502並允許I/O信號被提供在該第二晶片502和該基層金屬層102並據此該半導體晶片104之間。互利結構506如，例如，凸塊，立柱，支柱，球或電性將該晶片100耦合該第二晶片502的任意適合結構，可用來路由在該接觸點504和該第二晶片502之間的電性信號。該第二晶片502通過該鍵合引線212連接到該引線框302。可將該第二晶片502堆積在該晶片100上，通過，例如，倒裝晶片過程。如圖5中可看到的一樣，該第二晶片502耦合該晶片100，使用以焊接凸塊508和支柱510的形式的互聯結構506。
儘管在圖4和5的電子封裝元件中僅僅繪出了兩個半導體晶片(如104和402或502)，在其他實施方案中的堆積配置中或相互支援的配置中的電子封裝元件內可處置附加的半導體晶片。該附加的半導體晶片通用可耦合該基層金屬層102或該第二金屬層118用來此處所述之技術路由電源和/或接地信號。例如，該粘結墊206可實施使用此處所述技術從該附加晶片到該第二金屬層118的電性耦合。
該晶片100的電源/接地佈局提升了該I/O功能，通過將多個粘結墊位置提供在該基層金屬層102，該第一金屬層110，和用於該I/O、GND和/或電源信號的第二金屬層118之上，通過該鍵合引線212。另外，作為該GND層的第一金屬110減少了該電壓的下降，通過以更有效方式將電性連接的機制提供給該不同層。總之，該電性封裝元件減少了電壓的下降並保持該電子封裝的小的大小，當增加I/O功能並保持開銷下降時。
圖6描述了用來製造晶片100的電源/接地佈局的方法的過程流程圖600。為了簡潔，將使用作為該金屬層形式中的討論的一部分的參考，來提及形成絕緣層106，介電層114，鈍化層122和這些層中通孔108,116的方法。
在602處，該方法包括在半導體晶片104上形成基層金屬層102。將該基層金屬層102耦合該半導體晶片104，作為該半導體104的構造物的一部分或基於已知封裝或組裝過程。該絕緣層106形成於該基層金屬層102之上以保護該基層金屬層102離開其他導電層。下一步，在該絕緣層106中形成多個通孔以提供將該基層金屬層102連接到這些不同導電層的機制。
在604處，該方法包括在該絕緣層106上形成第一金屬層110，其在該基層金屬層102上形成。如所討論的一樣，該第一金屬層110用作該GND層以將下面的信號雜訊分離，特別是在高強度電流切換期間。
在606處，該方法包括在該第一金屬層110中形成多個島112。該多個島112促進通過該各個層的電性連接。在該第一金屬層110上形成介電層114用來保護該第一金屬層110離開其他導電層。下一步，在該介電層114中形成多個通孔116以提供將該第一金屬層110連接到不同導電層的機制。
在608處，該方法進一步包括在該介電層114上形成第二金屬層118，其形成於該第一金屬層110之上。如所討論的一樣，該第二金屬層118用作該電源層。
在610處，該方法進一步包括在該第二金屬層118中形成多個島120。該多個島120將來自該第一金屬層110處的GND信號連接到該堆積的晶片402,502，且將來自該基層金屬層102處的I/O信號連接到該堆積的晶片402,502。
在612處，在該第二金屬層118上形成鈍化層112用來保護該第二金屬層118離開其他導電層。該一個或多個開口124形成於該鈍化層122中以露出該第二金屬層118並提供機制以將該第一金屬層110連接到該堆積的晶片402,502。例如，該半導體構造物的過程是65納米(nm)過程或45nm過程以產生65nm或45nm或更小的晶片大小。
本說明書可使用如上/下的基於透視圖的說明。這樣的說明僅僅用來促進該討論而不打算將此處所述實施方案的應用限制於任意特定方向。
該術語晶片，晶片，積體電路，單塊積體電路裝置，半導體裝置，和晶片經常可互換地用於該微電子領域中。本發明可應用於上述所有，當他們在本領域中一般是可理解的時。
因本發明起見，該短語“A/B”意為A或B。因本發明起見，該短語“A和/或B”意為“(A)，(B)，或(A和B)”。因本發明起見，該短語“A，B和C的至少一個”意為“(A)，(B)，(C)，(A和B)，(A和C)，(B和C)或(A，B和C)”。因本發明起見，該短語“(A)B”意為“(B)或(AB)”，即，A是可選元件。
將各種操作描述為輪流的多個分離操作，以最有助於該請求主題的理解的方式。然而，不應將說明的順序構建用來暗示這些操作是必須基於順序的。特別地，不可以該展現的順序來這些操作。可以不同於所述實施方案的順序來實施所述之操作。可實施各種附加操作和/或可在附加實施方案中省略所述之操作。
該說明書使用短語“在實施方案中”，“在多個實施方案中”或類似語言，其每一個可能指的是一個或多個相同或不同的實施方案。而且，該術語“包含”，“包括”，“具有”等，在使用于本發明的實施方案時，是同義的。
儘管此處已經描述和說明了某些實施方案，計畫用來獲得相同目的的較多種類的替換和/或等同實施方案或實施方式可取代所述和所說明的實施方案而不背離本發明的範圍。本發明計畫覆蓋此處所討論的實施方案的任意適應或變化。因此，明顯計畫的是，僅僅通過該請求項和其等同體來限定此處所述之實施方案。

Claims (19)

  1. 一種製造晶片的方法，該方法包括：在第一半導體晶片上形成基層金屬層；形成獨立於該基層金屬層的第一金屬層；創建在該第一金屬層中的一第一島以路由該晶片中的(i)接地信號或(ii)電源信號的至少一個，其中該第一島是由圍繞該第一島之該第一金屬層中的一開口所定義；形成一介電材料於(i)該第一金屬層上及(ii)該第一金屬層之該開口中，使得該第一金屬層中的該第一島經由該介電材料圍繞沿著該第一島的整個周邊；形成獨立於該第一金屬層的第二金屬層；和創建在該第二金屬層中的一第二島以路由該晶片中的(i)接地信號或(ii)電源信號的至少一個，其中該第二島是由圍繞該第二島之該第二金屬層中的一開口所定義。
  2. 如請求項1所述之方法，其中(i)該第一金屬層包括銅(Cu)，鋁(Al)，鋁矽合金，鋁銅合金，或鎳(Ni)的至少一種，以及(ii)該第二金屬層包括銅(Cu)，鋁(Al)，鋁矽合金，鋁銅合金，或鎳(Ni)的至少一種。
  3. 如請求項1所述之方法，進一步包括將開口限制在(i)該第一金屬層和(ii)該第二金屬層的至少一個內以提 供應力消除。
  4. 如請求項1所述之方法，進一步包括在該第二金屬層中提供一個或多個粘結墊以在該晶片和一個或多個外部裝置之間傳送信號。
  5. 如請求項1所述之方法，進一步包括提供電性通道以將來自該第二金屬層處的電源信號連接到該基層金屬層，通過在該第一金屬層中的多個島。
  6. 如請求項1所述之方法，進一步包括通過在該第二金屬層中的多個島，提供電性通道以將來自該第一金屬層處的接地信號連接到堆積晶片。
  7. 如請求項1所述之方法，進一步包括：將該晶片定位在封裝的引線框上；和在該晶片頂部堆積第二半導體晶片。
  8. 如請求項1所述之方法，進一步包括：在該第二金屬層上形成鈍化層；在該鈍化層中創建一個或多個開口以露出在該第二金屬層中的接觸點；和在該鈍化層中的一個或多個開口處堆積第二半導體晶片以據此將該第二晶片電耦合到該晶片。
  9. 如請求項8所述之方法，其中將該第二半導體晶片通過焊接凸塊電耦合到該第二金屬層。
  10. 如請求項8所述之方法，其中將該第二半導體晶片通過銅支柱和焊接凸塊電耦合到該第二金屬層。
  11. 一種晶片包括：形成在第一半導體晶片上的基層金屬層；獨立於該基層金屬層的第一金屬層，該第一金屬層具有多個島，配置用來路由該晶片中的(i)接地信號或(ii)電源信號的至少一個；和獨立於該第一金屬層的第二金屬層，該第二金屬層具有多個島，配置用來路由該晶片中的(i)接地信號或(ii)電源信號的至少一個；其中配置該第一金屬層中的多個島以對齊該第二金屬層中的多個島；以及其中至少一些該第一金屬層中的多個島經由通孔連接至少一些該第二金屬層中的多個島。
  12. 如請求項11所述之晶片，其中(i)該第一金屬層包括銅(Cu)，鎳，鋁(Al)，鋁矽合金，或鋁銅合金的至少一個，以及(ii)該第二金屬層包括銅(Cu)，鎳，鋁(Al)，鋁矽合金，或鋁銅合金的至少一個。
  13. 如請求項11所述之晶片，其中(i)該第一金屬層和(ii)該第二金屬層的至少一個包括定義於其中的開口以提供來自該第一金屬層或該第二金屬層之熱膨脹的應力消除。
  14. 如請求項13所述之晶片，其中該些開口位在(i)該第一金屬層或(ii)該第二金屬層的一中心位置。
  15. 如請求項11所述之晶片，其中配置該第一金屬層中的多 個島以提供將來自該第二金屬層處的電源信號連接到該基層金屬層的電子通道。
  16. 如請求項11所述之晶片，其中配置該第二金屬層中的多個島以提供將來自該第一金屬層處的接地信號連接到該晶片頂部上堆積的第二半導體晶片的電子通道。
  17. 如請求項11所述之晶片，其中：該第一金屬層是接地層，和該第二金屬層是電源層。
  18. 如請求項11所述之晶片，進一步包括：絕緣層，配置用來將該基層金屬層隔離於該第一金屬層；介電層，配置用來將該第一金屬層隔離於該第二金屬層；和鈍化層，配置用來保護該第二金屬層免於露出。
  19. 如請求項11所述之晶片，進一步包括：鈍化層，形成在該第二金屬層上，配置該鈍化層以形成在該鈍化層中的一個或多個開口用來露出該第二金屬成中的接觸點；和第二半導體晶片，配置用來堆積在該鈍化層中的一個或多個開口上以據此電性地將該第二半導體晶片耦合到該晶片，其中將該第二半導體晶片電性耦合到該第二金屬層，通過下列之一：(i)焊接凸塊或(ii)銅支柱和焊接凸 塊。
TW100138127A 2010-10-20 2011-10-20 晶片的電源／接地佈局 TWI566366B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US40509910P 2010-10-20 2010-10-20
US13/277,140 US8946890B2 (en) 2010-10-20 2011-10-19 Power/ground layout for chips

Publications (2)

Publication Number Publication Date
TW201225240A TW201225240A (en) 2012-06-16
TWI566366B true TWI566366B (zh) 2017-01-11

Family

ID=45972314

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100138127A TWI566366B (zh) 2010-10-20 2011-10-20 晶片的電源／接地佈局

Country Status (5)

Country Link
US (2) US8946890B2 (zh)
KR (1) KR101888176B1 (zh)
CN (1) CN103270590B (zh)
TW (1) TWI566366B (zh)
WO (1) WO2012054711A2 (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5686128B2 (ja) * 2012-11-29 2015-03-18 トヨタ自動車株式会社 半導体装置
US9607938B2 (en) 2013-06-27 2017-03-28 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with embedded pad on layered substrate and method of manufacture thereof
KR102161736B1 (ko) 2014-08-13 2020-10-05 삼성전자주식회사 시스템 온 칩, 시스템 온 칩을 포함하는 전자 장치 및 시스템 온 칩의 설계 방법
US10217708B1 (en) 2017-12-18 2019-02-26 Apple Inc. High bandwidth routing for die to die interposer and on-chip applications
US10607982B2 (en) * 2018-07-10 2020-03-31 Samsung Electronics Co., Ltd. Layout connection isolation technique for improving immunity to jitter and voltage drop in a standard cell

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5497033A (en) * 1993-02-08 1996-03-05 Martin Marietta Corporation Embedded substrate for integrated circuit modules
US20020048930A1 (en) * 1998-12-21 2002-04-25 Mou-Shiung Lin Top layers of metal for high performance IC'S

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2836542B2 (ja) * 1995-10-17 1998-12-14 日本電気株式会社 半導体装置の製造方法
US6143611A (en) * 1998-07-30 2000-11-07 Micron Technology, Inc. Semiconductor processing methods, methods of forming electronic components, and transistors
TWI313507B (en) * 2002-10-25 2009-08-11 Megica Corporatio Method for assembling chips
CN1314115C (zh) * 2002-03-15 2007-05-02 台湾积体电路制造股份有限公司 多重金属层内连线结构
US6770971B2 (en) * 2002-06-14 2004-08-03 Casio Computer Co., Ltd. Semiconductor device and method of fabricating the same
TWI221330B (en) * 2003-08-28 2004-09-21 Phoenix Prec Technology Corp Method for fabricating thermally enhanced semiconductor device
DE102006023123B4 (de) * 2005-06-01 2011-01-13 Infineon Technologies Ag Abstandserfassungsradar für Fahrzeuge mit einem Halbleitermodul mit Komponenten für Höchstfrequenztechnik in Kunststoffgehäuse und Verfahren zur Herstellung eines Halbleitermoduls mit Komponenten für ein Abstandserfassungsradar für Fahrzeuge in einem Kunststoffgehäuse
US7675157B2 (en) * 2006-01-30 2010-03-09 Marvell World Trade Ltd. Thermal enhanced package
TWI328423B (en) * 2007-09-14 2010-08-01 Unimicron Technology Corp Circuit board structure having heat-dissipating structure
JP4539773B2 (ja) * 2008-03-07 2010-09-08 株式会社デンソー 半導体装置およびその製造方法
US7781883B2 (en) * 2008-08-19 2010-08-24 International Business Machines Corporation Electronic package with a thermal interposer and method of manufacturing the same
US8034661B2 (en) * 2009-11-25 2011-10-11 Stats Chippac, Ltd. Semiconductor device and method of forming compliant stress relief buffer around large array WLCSP

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5497033A (en) * 1993-02-08 1996-03-05 Martin Marietta Corporation Embedded substrate for integrated circuit modules
US20020048930A1 (en) * 1998-12-21 2002-04-25 Mou-Shiung Lin Top layers of metal for high performance IC'S

Also Published As

Publication number Publication date
WO2012054711A2 (en) 2012-04-26
TW201225240A (en) 2012-06-16
US20150155202A1 (en) 2015-06-04
US20120098127A1 (en) 2012-04-26
KR20130130722A (ko) 2013-12-02
CN103270590A (zh) 2013-08-28
US8946890B2 (en) 2015-02-03
WO2012054711A3 (en) 2012-06-14
KR101888176B1 (ko) 2018-08-14
CN103270590B (zh) 2016-10-26

Similar Documents

Publication Publication Date Title
US7829998B2 (en) Semiconductor wafer having through-hole vias on saw streets with backside redistribution layer
US7902638B2 (en) Semiconductor die with through-hole via on saw streets and through-hole via in active area of die
US8227910B2 (en) Apparatus for thermally enhanced semiconductor package
CN109216219A (zh) 具有双侧金属布线的半导体封装件
US7880285B2 (en) Semiconductor device comprising a semiconductor chip stack and method for producing the same
JPWO2005101476A1 (ja) 半導体素子及び半導体素子の製造方法
US8361857B2 (en) Semiconductor device having a simplified stack and method for manufacturing thereof
TW200929480A (en) Semiconductor chip and method for fabriating semiconductor chip
US7122748B2 (en) Semiconductor device having packaging structure
US20100327448A1 (en) Semiconductor with Bottom-Side Wrap-Around Flange Contact
TWI566366B (zh) 晶片的電源／接地佈局
US8878354B1 (en) Method and apparatus for supplying power to a system on a chip (SOC)
KR100919860B1 (ko) Ｔｓｖ를 가지는 반도체 칩 디바이스 및 그 제조방법
US9721928B1 (en) Integrated circuit package having two substrates
US9640457B2 (en) Power amplifier package and method thereof
US8796839B1 (en) Semiconductor package including a power plane and a ground plane
KR101601793B1 (ko) 멀티칩 모듈들을 위한 개선된 전기적 연결들
TW202414748A (zh) 半導體裝置
CN117878093A (zh) 半导体封装体、半导体接合结构及其形成方法