CN1269212C - 将电路和引线框的功率分布功能集成到芯片表面上的电路结构 - Google Patents

将电路和引线框的功率分布功能集成到芯片表面上的电路结构 Download PDF

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CN1269212C
CN1269212C CNB011355816A CN01135581A CN1269212C CN 1269212 C CN1269212 C CN 1269212C CN B011355816 A CNB011355816 A CN B011355816A CN 01135581 A CN01135581 A CN 01135581A CN 1269212 C CN1269212 C CN 1269212C
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chip
circuit
group
line segment
metal
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CN1355567A (zh
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T·R·埃弗兰德
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

一种安装在引线框上的集成电路芯片，具有沉积在芯片表面上的功率分布线网络，使它们直接位于电路的有源元件之上；以及导电且垂直地连接到分布线之下的所选有源元件的分布线，还有连接到引线框的线段的导体，由此节省电路功率分布线和导体衬垫所消耗的硅地盘量，增加电路设计灵活性和组装制造能力，减少线段的输入/输出数目。

Description

将电路和引线框的功率分布功能集成到芯片表面上的电路结构
                         技术领域
本发明一般涉及半导体器件和工艺过程领域，尤其涉及能够把引线框的功率分布功能集成到芯片表面的集成电路。
                         背景技术
半导体器件的引线框是作为预先制备的低成本部件而发明的(美国专利3,716,764和4,034,027)，其作用是同时满足半导体器件及其工作的几方面需要：首先，引线框提供稳定的支承衬垫，用于对半导体芯片，通常指集成电路(IC)芯片牢固地定位。由于包含衬垫的引线框由导电材料制成，在需要时可以将衬垫偏置到半导体器件牵涉的网络所需的任何电位，尤其是地电位。
其次，引线框提供多个导电线段，将各种电导体引入芯片附近。线段的(“内部”)末端与IC表面上接合衬垫之间的剩余间隙通常被薄的金属线桥接，金属导线被分别地接合到IC接触衬垫和引线框线段上。这种解决方案的结果是，线段、接合衬垫和连接线具有固定的相对位置，一旦最终完成了器件设计，接合衬垫不能被方便地重排，以简化某些IC重新布局。
第三，远离IC芯片的引线线段的端部(“外部”末端)需要与“其他部件”或“外部世界”(例如组件式印刷电路板)作电气和机械连接。在压倒多数的电子应用中，这种附着是通过焊接实现的。
通常实践一直是用薄的金属片(厚约120至250μm)制备单片引线框。由于易于制造的缘故，通常所选的初始金属为铜、铜合金、铁镍合金(例如所谓的“合金42”)以及殷钢。从原始的金属片刻蚀或压印出所需形状的引线框。以这种方式，引线框的各个线段取薄金属条的形式，其特定几何形状是通过设计确定的。对大多数用途而言，典型线段的长度比其宽度大得多。
通常实践进一步是让多个线段专用于把电信号提供给设计的芯片输入/输出端，而让另外多个线段专用于把功率电流提供给设计的芯片输入/输出端。
半导体技术在漫长历史上的两个独立趋势迫切地需要本发明。第一个技术趋势涉及对越来越多的信号和功率端子因此和引线框线段的需求迅速增长。已经引出了更细线段尺寸的引线框。然而，它们已经简单地被对芯片上数目越来越多且间隔越来越紧密的接合衬垫的迅速增长需要而压倒。这种趋势导致对所有接合和线尺寸的更加苛刻的限制以及对获得球接合和针脚接合焊接的极为严格的精确度要求。这种趋势现在正在向技术可行极限推进。
第二个技术趋势涉及通过节约半导体“地盘(real estate)”而节省制造成本。为了容纳接合线或焊剂的球，硅IC上典型接合衬垫必须具有足够的尺寸，典型尺寸范围为45×45μm见方至150×150μm见方。因此，根据接合衬垫的数目和IC的尺寸，它们消耗了电路面积的约在1至20％之间的面积，有时甚至最高达到45％。为了制造和组装缘故，接合衬垫沿电路周边排成行，通常沿芯片的四边排成一列。
迄今为止，由于在接合过程中发生的不可避免的机械力和冶金应力所造成的对电路结构损伤的高风险，制造出的所有半导体器件不得不把被接合衬垫覆盖的面积排除在用于部署实际电路图案之外。显然地，如果能够将电路图案置于接合衬垫金属之下，便能够相当大地节省硅地盘。实现这个特征的一种方法则是建立另一金属化层面，主要专用于接合衬垫形成。这个层面则是建立在覆盖有源电路区的保护涂层之上。然而，在现有技术中，在保护涂层与外金属层之间不得不施加一层昂贵的聚酰亚胺应力缓冲层，正如K.G.Heinen等人所表明的(“在有源电路上的线接合”，IEEE第44次电子元件技术会议会刊，1994，pp922-928)。
在1998年7月14日提交的美国专利申请60/092,961(Saran，“在有源集成电路上的接合的系统和方法”)中提出了现有技术中的一种不同方法。为了使得接合衬垫的强度足以能够承受在引线接合过程中所需的机械力，描述了接合衬垫下方的加强系统，它利用实际IC的专门部分作为加强接合衬垫下方弱介质层的手段。这种方法需要专门设计或重新设计IC，不太适合于标准线性和逻辑IC，这种IC通常具有众多的接合衬垫，但是电路面积相对较小。
在1997年10月28日提交的美国专利申请08/959,410、2000年7月7日提交的09/611,623(Shen等人，“在有源电路上具有接合层的集成电路”)、2000年7月27日提交的60/221,051(Efland等人，“具有分布接合和电流流动的集成功率电路”)描述了在有源电路部分上形成接合线的另一种方法，本发明与这些专利申请相关。至电路的顶部金属化层的通孔涂覆籽晶金属，然后电镀相继的金属层，由此填充通孔并形成引线接合或焊剂球的应力吸收附着表面。
在1999年12月10日提交的美国专利申请09/458,593(Zuniga等人，集成电路上接合的系统和方法)中描述了在有源电路部分之上形成接合的另一种方法，本发明与该专利申请相关。可接合和应力吸收的金属层与机械特性强的电绝缘层的组合分开了接合衬垫与位于接合衬垫之下的一部分集成电路。
在有源电路上形成接合的这些方法中没有一种提出解决细节距接合衬垫、细节距引线框、紧密限制的接合制造能力与改善器件性能之间冲突问题的基本方案。因此迫切地需要一种低成本、可靠的结构和方法，该结构和方法可节省硅地盘以及放松引线和焊剂球接合的制造能力、放松引线框设计、增加IC布局的自由度以及明显改善IC特性。系统应当提供无应力的、简单的、无附加成本的接触衬垫，即使在接触衬垫位于一个或多个在结构和机械上弱的介质层上时也能提供柔性的容忍的接合处理。系统和方法应当可应用于宽广的设计范围、材料和处理不同情况中，导致显著地节省硅，以及提高器件特性和可靠性和加工产额。较佳地，利用已安装的工艺方法和设备应当能实现这些创新特性，因此不需要对新的制造机器上作投资。
                         发明内容
安装在引线框上的集成电路(IC)芯片具有沉积在芯片表面上的功率分布线网络，使得这些线位于IC有源元件之上，由填充金属的通孔垂直地连接到线路下方的所选有源元件，以及通过导体还连接到引线框的线段上。
沉积并形成图案的可接合线路网络提供若干个显著优点。
●网络将大部分传统功率分布互连线从电路层面重新定位到新建立的表面网络，因此大大节省硅地盘量并允许缩小IC面积。
●网络通过填充金属的通孔被电连接到所选有源元件，由于这些通孔易于被重新设计到其他位置，IC设计人员得到新的设计自由度。
●网络将专用于供电的大多数接合衬垫从沿芯片周边的传统排列重新定位在新建立的可接合线上，又大大节省了硅地盘量并使接合机器从其极为紧密的连接器布置和附着规则到更加放松的接合程序。
●网络是在基片加工过程沉积的和形成专门适合于提供功率电流和地电位的一系列金属层的图案的。
●作为本发明的较佳实施例，将具有可附着的最外侧金属表面的网络线路布置成使它们在便于附着焊线和焊剂球的位置上形成衬垫。
在本发明的较佳实施例中，半导体器件的芯片具有制备在第一芯片表面(“有源”表面)上的集成电路；该集成电路包括有源元件、至少一层金属层和一层机械特性强的电绝缘的保护涂层，该涂层具有多个填充金属的通孔和多个窗口，前者用于接触所述至少一层金属层，后者用于露出电路接触衬垫。芯片进一步具有沉积在保护涂层上的一叠导电膜，使这叠导电膜形成图案构成基本上垂直在有源元件之上的线路网络。该叠层包括与通孔接触的最底部膜、至少一层应力吸收膜和一层不可腐蚀且冶金附着的最外层膜。使该网络形成图案以分配功率电流和地电位。将芯片的第二(“无源”)表面附着到引线框的安装衬垫，引线框也具有提供电信号的第一组多个线段和提供电功率和接地的第二组多个线段。用所述第一组多个线段使电导体与芯片接触衬垫连接，用所述第二组多个线段使电导体与网络线连接。
本发明的一个方面是通过减小被电路功率分布线以及被功率连接的芯片接触衬垫所消耗的硅面积而降低IC芯片的成本。
本发明的另一个方面是通过以几何上最短的路径将功率连接到有源元件而达到电路设计灵活性的新的程度，且不以再设计为代价。
本发明的另一个方面是通过放松引线接合和焊剂接合中球附着的紧密布置规则而改善组装制备能力。
本发明的另一个方面是通过把引线框的多数功率分布功能派遣到定位在芯片表面上的创新的功率分布线路网络上而减少功率输入/输出所需的引线框线段的数目。
本发明的另一个方面是通过提供衬垫金属层以及分离接触衬垫与电路的绝缘层，在厚度上足以可靠地吸收机械、热和碰撞应力，而提高半导体探查和引线接合和焊剂附着组件的工艺过程和工作可靠性。
本发明的另一个方面是取消对探查和引线接合和焊剂附着的工艺过程的限制，因此即使对非常脆的电路介质也能使造成裂纹损伤风险减至最小。
本发明的另一个方面是提供设计和布局概念和工艺方法，所述概念和方法是灵活的，因此能够将它们应用于许多类半导体IC产品，以及是通用的，因此能够将它们应用于几代产品。
本发明的另一个方面是提供一种低成本和高速的制备、测试和组装的工艺过程。
本发明的另一个方面是仅仅使用在IC器件制备中最常采用和采纳的设计概念和工艺过程，因此避免了新的资本投资的成本以及利用已安装的制备设备基础。
这些诸方面已经通过对本发明的有关设计概念和适合于大批量生产的工艺流的教导而实现。各种改进已经成功地被用于满足产品几何学和材料的不同选择。
当结合附图以及所附权利要求书中设定的新颖特征考虑时，从对本发明较佳实施例的以下描述中，本发明所代表的技术进步及其目的将变得显而易见。
                         附图说明
图1是根据现有技术的集成电路芯片一部分的简化示意透视图，集成电路芯片具有附着于接合衬垫并连接于部分引线框的焊接线。
图2是根据本发明的集成电路芯片一部分的简化示意透视图，集成电路芯片具有集成了电路和引线框的功率分布功能的表面结构。
                       具体实施方式
本发明涉及1997年10月28日提交的08/959,410美国专利申请、2000年7月7日提交的09/611,623美国专利申请(Shen等人，“在有源电路上具有焊接层的集成电路”)和2000年7月27日提交的60/221,051美国专利申请(Efland等人，“具有分布焊接和电流流动的集成功率电路”)，这里将其引作参考。
通过突出现有技术的缺点最容易地理解本发明的作用。图1示出集成电路(IC)芯片一部分的简化示意透视图，以数字100表示，具有现有技术的设计和制备特征。半导体衬底101(通常为硅，厚度在约225与475μm之间)具有第一(“有源”)表面101a和第二(“无源”)表面101b。第二表面101b附着于预先制备的引线框架(通常为铜、铜合金或镍铁合金，厚度约100至300μm)的芯片安装衬垫(图1中未示出)上。在数个引线(通常在14至600多个)当中，图1仅仅示出引线框几个内引线的末端120a、120b……，采用这些引线来供电。
嵌入在芯片第一表面101a中的是IC的多个有源元件(在现代IC中，有源元件的数目较大，常常超过一百万个，在横向和垂直维度上再微型化)。在表面101a中还包括至少一层金属化层(通常为纯的或合金铝，厚度在0.4与1.5μm之间，在有些IC中，存在6层以上的金属化层的分层结构)。形成连接IC的有源元件与无源元件和接触衬垫的金属线图案。对于传导电功率的金属线，线宽通常在约20至250μm的范围。图1中示意的是一小部分金属图案，作为在有源元件与接触衬垫之间分布电功率的弯曲线的布局。
为了说明起见，将图1中示出的有源元件分类为两个不同的电回路。一个回路包括以102a至102n表示的有源元件，另一个回路包括有源元件103a至103n。互连功率线104和105分别组织这两个回路。回路104有两个端子106a和106b，将它们制备成适合于电导体的接触衬垫，连接接触衬垫与引线框的引线末端110。根据最经常生产的类型的器件，接触衬垫的数目可以在14与600多之间变化。在图1中，选择引线接合(通常为金线，直径约20至28μm)作为电学互连线。将球体108a和108b分别附着于接触衬垫106a和106b，将针脚110a和110b分别附着于引线末端120a和120b。同样，回路105有两个端子107a和107b，也将它们制备成适合于线球接合的接触衬垫。将球109a和109b分别附着于接触衬垫107a和107b，将针脚111a和111b分别附着于引线末端120c和120d。为了避免导线下垂或导线掠过的问题，导线跨距140的长度较佳地保持小于2.5mm。
正如图1中所示，半导体衬底101的第一表面101a被保护涂层130均匀覆盖。接触衬垫106a、106b等作为这个保护涂层中的窗口敞开。通常，保护涂层厚度在0.8μm与1.2μm之间，机械强度大，电绝缘，一般不透湿的，较佳的材料包括氮化硅和氧氮化硅。
为了使IC的信号输入/输出工作，需要保护涂层中的附加窗口，露出下方的接触衬垫金属。图1中未示出这些窗口及其各个引线接合。
正如从图1可以推断的，已知技术在IC设计、引线框和器件设计、制备过程和产生制造能力上存在数个问题和限制。
-将功率输入/输出端子置于芯片周边附近迫使当前困难
-用长的功率线来互连有源电路；
-沿功率分布线补偿不可避免的电压降；
-接受不灵活的对有源IC元件定位的设计规则；以及
-接受贵重的硅地盘的损失。
-将大量接合衬垫置于芯片周边周围消耗宝贵的硅地盘。
-将大量接合衬垫置于芯片周边周围迫使当前趋势
-缩小接合衬垫区；
-缩小接合衬垫节距；
-缩小引线球从而使它们配合到减小的接合衬垫区中；以及
-严格自动焊接机的程序以便于精确地将球定位在衬垫区的中心。
-预先制备数目更多的引线的引线框引起当前困难
-缩小内部引线的宽度；
-缩小内部引线的节距；以及
-将针脚接合衬垫置于微小的内部引线上。
为了补救现有技术的上述缺点，图2综合了本发明的创新。图2是采用本发明所揭示的设计和制备特征的IC芯片(标为200)一部分的简化示意透视图。半导体衬底201具有第一(“有源”)表面201a和第二(“无源”)表面201b。第二表面201b附着于预先制备的引线框架(通常为铜、铜合金、镍铁合金、殷钢或铝，厚度约100至300μm)的芯片安装衬垫(图2中未示出)上。在数个引线(通常在14至600多个)当中，图2仅仅示出很少几个引线框线段的末端220a、220b……，它们被用于供电并位于IC芯片附近。
嵌入在芯片第一表面201a中的是IC的多个有源元件(在现代IC中，有源元件的数目较大，常常超过一百万个，在横向和垂直维度上再微型化)。根据本发明，图2中所示的有源元件202a至202n和203a至203n是根据它们共享的供电而组织到IC功能允许这样的程度。所有的有源元件202a至202n共享一个功率电流端子(例如，输入端子)，所有的有源元件203a至203n共享另一个端子(例如，输出端子)。在图2中，功率电流从元件202a流到元件203a，……，从元件202n流到元件203n。图2中用虚轮廓线示出互连线。例如，从有源元件202a到有源元件203a的互连表示为204a，……，从有源元件202n到元件203n的互连表示为204n。
正如图2所示，半导体衬底201的第一表面201a以及嵌入在该表面中的IC被保护涂层230均匀地覆盖。较佳地，保护涂层厚度在0.4μm与1.5μm之间，机械强度大，电绝缘，不透湿的，较佳的材料包括氮化硅、氧氮化硅、硅碳合金及其夹层薄膜。在某些应用中可用聚酰亚胺层。
功率分布线的网络沉积在保护涂层230的露出表面之上，直接且基本上垂直地位于IC的有源元件上，对于本发明而言是极为重要的。在图2中，图中示出的功率分布线之一表示为251，图中示出的另一个表示为252。以下描述材料结构和组分以及制备过程。
此外，功率分布线之下的所选有源元件与功率线导电且垂直连接，对本发明而言是很重要的。较佳地，这一连接是通过填充金属的通孔260提供的，它们与有源元件的金属线和功率分布线相接触。通孔260是利用标准光刻技术通过形成图案和蚀刻而形成。然后结合以下描述的功率线金属化的沉积，用金属填充通孔。
沉积线251和252的最外层金属选自可粘合(和可焊接，见下文)的材料。电导体连接该最外层金属与引线框的引线末端。在图2中，选择引线接合(引线较佳地是纯的或合金的金、铜或铝，直径约20至30μm)作为电学互连的较佳技术。将球208和209分别附着于线251和252，将针脚210和211分别附着于引线末端220a和220b。引线接合技术的近期进展现在允许形成紧密控制的引线回路和回路形状，这对于本发明是重要的。举例来说，图2中示出的回路240比回路241要长得多。用当今的焊接机可实现7.5mm甚至更长的引线长度。例如在美国Kuliche & Soffa公司的计算机化焊接机8020中或者在美国德克萨斯仪器公司的ABACUS SA中可以看到这些进展。以预定和计算机控制的方式通过空气移动毛细管将产生精确限定形状的引线回路。例如，能够形成圆形、梯形、直线形和特定的回路。
沉积的分布金属线251和252的较佳结构由附着于保护涂层230的籽晶金属层和通孔260的底部构成，随后是第一相对较薄应力吸收金属层、第二相对较厚应力吸收层、和最后的最外层可粘合金属层。较佳地，籽晶金属层选自由钨、钛、氮化钛、钼、铬及其合金组成的一组材料。籽晶金属层是导电的，提供与IC有源元件和保护涂层的金属线二者的粘合，允许其上表面的露出部分被电镀，以及阻止接下来的应力吸收金属迁移到元件金属化层中。籽晶金属层的厚度在约100至500μm之间。另一方面，籽晶金属层可以由两个金属层组成，第二金属的例子是铜，因为它为接下来电镀提供一个合适表面。
对于本发明应当指出，单个籽晶层较佳地由耐热金属制成，其厚度大到足以可靠地起应力吸收缓冲体的作用。厚度在约200与500μm之间是令人满意的，较佳地约为300μm。最佳应力吸收的厚度不仅依赖于所选金属，而且还依赖于所选的沉积技术、沉积速率和在沉积期间硅衬底的温度，因为这些参数决定着沉积层的微观结晶性。例如，已经发现，当利用钨的溅射沉积时，层的形成较佳地是以约4至5nm/s速率在环境温度下形成在硅衬底上，当厚度达到至少300μm时温度增大到约70℃。如此产生的钨微晶具有平均尺寸和分布，以致于在组装中在引线接合过程期间它们可靠地起应力吸收“弹簧”的作用。
对于沉积应力吸收层，采用电镀工艺是有利的。第一应力吸收金属层的一个例子是铜，其厚度在约2至35μm的范围内，使它成为接下来附着诸如接合引线的连接导体的机械性强的支承层。第二应力吸收金属层的一个例子是镍，其厚度在约1至5μm的范围内。
最外层是冶金上可接合和/或可焊接的。如果引线接合是所选的连接方法(正如图2中所示)并且最外层应当是可接合的，较好的金属选择包括纯的或合金的铝、金、钯和银。如果焊接是所选的连接方法且最外层应当是可焊接的，较好的金属选择包括钯、金、银和铂。在两种情况中，厚度均在500至2800μm范围内。可以理解，层的数目、材料及其厚度的选择以及沉积工艺可以改变以便适合特定器件的需要。
网络或分布线的电镀图案可以形成任何所需布局图。正如在图2的例子中看到的，连接体线路图案可以为细长或直线形式。然而其功能是在通孔上垂直延伸到元件金属化布线。否则，它可以从几何上延伸到通孔区以外，例如延伸到加宽部分中，该加宽部分提供足够的表面面积以容纳超大直径的接合引线或焊球。这些附着“衬垫”同样地非常适合于附着楔形接合或针脚接合。
正如以上指出的，最外层线路层可以如此选择，使得它是可焊接的。然后通过标准回流技术可以将焊球附着于其上。然而，在以上引用的美国专利申请09/611,623和60/221,051中描述的是，通常建议采用附加焊剂掩模或每个焊球有一个开口的聚酰亚胺层，以便保持限定区域内的倒装片冲撞和在冲撞形成期间的形状，接下来附着于外部封装或板。
应当说明的是，为了改善IC有源元件所释放热能的耗散，可以开拓分布线的定位。当采用焊剂冲撞作为至“外部世界”的连接手段时更是如此，以使热耗散的热通路和热阻减至最小。
为了使IC的信号输入/输出工作，需要用保护涂层的附加窗口来露出下方接触衬垫金属化布线，然后可以将引线接合或焊球固定于这些接触窗口。这些窗口及其各个引线接合在图2中未示出。
应当进一步说明的是，可以对沉积在保护涂层上的分布网络的至少一些线路或部分形成图案并专用于提供地电位的分布。
其他实施例
虽然参考示例性实施例描述了本发明，但是不希望将这一描述作有限意义的解释。在参考这一描述时，对于本领域专业技术人员而言显然能够对示例性实施例以及本发明其他实施例作出各种改进和组合。
作为一个例子，本发明涵盖以硅、硅锗、砷化镓或在集成电路制造中所用的任何其他半导体材料作为衬底制作的集成电路。
作为另一个例子，本发明一般地涵盖半导体集成电路，它包括将电路的功率分布功能集成到IC芯片表面中的电路结构以及连接于其他部件或“外部世界”的装置。将功率分布线的位置选择成这样，它们对分布线垂直下方的有源元件提供功率电流的控制和分布。
因此希望所附的权利要求书包含任何这样的改进或实施例。

Claims (22)

1.一种在芯片表面上具有附加导体网络的半导体器件，其特征在于，集成电路的功率分布与引线框的功率分布相结合，所述半导体器件包括：
具有第一和第二相对表面的半导体芯片；
制备在所述第一芯片表面上的集成电路，所述集成电路具有有源元件、接触衬垫、至少一层金属层、和机械性能强、电绝缘的保护涂层，所述涂层具有多个填充金属的通孔，与所述至少一层金属层相接触；
沉积在所述涂层上并形成图案到基本上垂直在所述有源元件上的分布线路网络中的基本共面、横向设置的导电膜，所述导电膜与所述通孔接触并具有附着于所述电绝缘涂层和所述填充金属的通孔的一层导电籽晶金属层，在所述籽晶金属层上的厚度足以可靠地吸收机械、热和碰撞应力的至少一层应力吸收膜，和一层非腐蚀和冶金可附着于导电层的最外层薄膜；
为分布功率电流和地电位形成图案的所述网络；
具有一个芯片安装衬垫、提供电信号的第一组多个线段和提供电功率和地电位的第二组多个线段的引线框；
所述第二芯片表面附着于所述芯片安装衬垫上；
连接所述芯片接触衬垫与所述第一组多个线段的电导体；以及
连接所述网络线与所述第二组多个线段的电导体。
2.如权利要求1所述的器件，其特征在于，所述芯片选自由硅、硅锗、砷化镓和电子器件制备中常用的任何其他半导体材料组成的一组材料。
3.如权利要求1所述的器件，其特征在于，所述电路包括水平和垂直排列的多个有源和无源电子元件。
4.如权利要求1所述的器件，其特征在于，所述集成电路包括多层金属化布线，所述层中至少有一层由纯或合金的铜、铝、镍或耐热金属制成。
5.如权利要求1所述的器件，其特征在于，所述涂层包括选自由氮化硅、氮氧化硅、硅碳合金、聚酰亚胺及其夹层薄膜构成的一组材料。
6.如权利要求1所述的器件，其特征在于，所述引线框是由选自铜、铜合金、铝、镍铁合金或殷钢构成的一组片状材料预先制备的。
7.如权利要求1所述的器件，其特征在于，进一步包括封装所述芯片、芯片安装衬垫、电导体和至少部分所述引线框线段的封壳。
8.如权利要求7所述的器件，其特征在于，所述封壳包括用转移注模工艺制备的聚合物化合物。
9.如权利要求7所述的器件，其特征在于，不包含在所述封壳中的引线框线段部分形成引线或引脚的形状，可焊接到外部部件上。
10.如权利要求1所述的器件，其特征在于，所述线和接触衬垫通过焊球附着于外部部件上。
11.如权利要求1所述的器件，其特征在于，所述冶金附着包括线球和针脚接合、带状接合和焊接。
12.如权利要求1所述的器件，其特征在于，所述导电膜包括至少一层选自由铜、镍、铝、钨、钛、钼、铬及其合金构成的一组材料的应力吸收金属层
13.如权利要求1所述的器件，其特征在于，所述最外侧金属层选自由纯的或合金的金、钯、银、铂和铝构成的一组材料。
14.如权利要求1所述的器件，其特征在于，所述导体是接合线、接合带或焊球。
15.如权利要求14所述的器件，其特征在于，所述接合线选自由纯的或合金的金、铜和铝构成的一组材料。
16.如权利要求14所述的器件，其特征在于，所述焊球选自由纯锡、包括锡/铜、锡/铟、锡/银、锡/铋、锡/铅的锡合金、以及导电粘合化合物构成的一组材料。
17.如权利要求1所述的器件，其特征在于，所述的线路网络被进一步电连接至适合于外部电接触的所选线段。
18.如权利要求1所述的器件，其特征在于，所述的线路网络与所述填充金属的通孔一起提供所述有源电路元件之间的功率分布功能。
19.一种制备半导体芯片具有第一和第二表面的半导体器件的方法，其特征在于，所述方法包括以下步骤：
在所述第一芯片表面上形成集成电路，所述电路包括有源元件、至少一层金属层和一层机械性强的电绝缘的保护涂层；
形成多个穿过所述涂层的通孔，以接近所述至少一层金属层；
通过在所述涂层上沉积一叠金属膜填充所述通孔，所述一叠金属膜具有附着于所述电绝缘涂层和所述填充金属的通孔的一层导电籽晶金属层、在所述籽晶金属层上的厚度足以可靠地吸收机械、热和碰撞应力的至少一层应力吸收膜和一层不腐蚀且冶金上可附着于导电层的最外侧膜；
将所述膜形成图案到线路网络中，使得所述线基本上垂直位于所述有源元件之上并适合于功率电流分布；
在所述涂层中形成多个窗口，露出电路接触衬垫；
提供一个包括芯片安装衬垫、适用于电信号的第一组多个线段和适用于电功率和接地的第二组多个线段；
将所述芯片附着到所述芯片安装衬垫上；
将电导体附着到所述电路接触衬垫和所述第一组多个线段上；以及
将电导体附着到所述线路网络和所述第二组多个线段上。
20.如权利要求19所述的方法，其特征在于，将电导体附着于所述接触衬垫和所述线路网络的所述步骤包括或是用接合线或接合带到所述接触衬垫和线路网络，或是用焊球回流到所述接触衬垫和线路网络的步骤。
21.如权利要求19所述的方法，其特征在于进一步包括将所述芯片、所述安装衬垫、电导体和至少一部分所述引线框线段封装在封壳中的步骤。
22.如权利要求19所述的方法，其特征在于进一步包括通过焊球将所述电路接触衬垫和所述线路网络附着于外部部件的步骤。
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