CN101379602B - 高电流半导体装置中低电阻低电感互连的制造方法 - Google Patents

高电流半导体装置中低电阻低电感互连的制造方法 Download PDF

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CN101379602B
CN101379602B CN2006800402802A CN200680040280A CN101379602B CN 101379602 B CN101379602 B CN 101379602B CN 2006800402802 A CN2006800402802 A CN 2006800402802A CN 200680040280 A CN200680040280 A CN 200680040280A CN 101379602 B CN101379602 B CN 101379602B
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copper
window
line
bump
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CN101379602A (zh
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伯恩哈德·P·朗格
安东尼·L·科伊尔
广·X·麦
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Texas Instruments Inc
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Texas Instruments Inc
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

本发明提供一种制造用于高电流半导体倒装芯片产品的低电阻低电感装置的方法。生产一结构，其包括具有金属化迹线(102)的半导体芯片(101)、与所述迹线接触的铜线，和铜凸块，所述铜凸块以有序且重复的布置位于每一线上，使得一条线的所述凸块定位在相邻线的相应凸块之间的中间位置附近。提供具有细长铜引线的衬底，所述引线具有第一和第二表面，所述引线与所述线成直角定向。使用焊接元件将每一引线的所述第一表面连接到交替线的所述相应凸块。最后，将组装件封装在模制化合物中，使得所述第二引线表面保持未经封装。

Description

高电流半导体装置中低电阻低电感互连的制造方法
技术领域
本发明大体上涉及半导体装置和工艺的领域；且更特定来说，涉及一种制造具有低电阻且可提供高功率、低噪声和高速度的高性能倒装芯片半导体装置的方法。
背景技术
在集成电路(IC)技术的当前趋势中存在向更高度的集成、缩小的组件特征尺寸和更高的速度发展的动力。此外，存在控制成本/性能比的无情压力，其通常转化为对追求更低成本解决方案的动力。更高水平的集成包含对更高数量的信号线和电力线的需要，但更小的特征尺寸使得越来越难以保持无相互干扰的清楚信号。
这些趋势和要求不仅支配了并入有IC的半导体芯片，而且也支配容纳且保护IC芯片的封装。
与传统的线接合组装相比，倒装芯片组装在硅集成电路(IC)装置的制造工艺流程中的日益风行受到若干事实的推动。首先，当降低了与常规线接合互连技术相关的寄生电感时，可共同改进半导体装置的电性能。第二，倒装芯片组装与线接合相比通常在芯片与封装之间提供更高的互连密度。第三，在许多设计中，倒装芯片组装比线接合消耗更少的硅“不动产(real estate)”，且因此有助于节省硅面积且降低装置成本。且第四，当采用并发群接合(concurrent gang-bonding)技术而非连续的个别接合步骤时，通常可降低制造成本。
在制造工艺中球形接合的标准方法使用焊球和其回流技术。这些互连方法比线接合更昂贵。此外，在焊球所附接装置的某些应力和寿命测试中存在严重的可靠性问题。产品管理者要求倒装芯片组装产品的更高性能，但也要求线接合装置的更低成本和更高可靠性。另外，倒装芯片组装产品的更高性能即使在在小型化装置中仍应延续，其目前遇到由使用常规焊球技术引起的严重技术困难。
发明内容
本发明申请人认识到需要开发一种考虑由半导体芯片、装置封装和外部板组成的完整系统以提供优越产品特征的技术方法，所述优越产品特征包含低电阻低电感、高可靠性和低成本。最小电感和噪声是高速度的先决条件，且减小的电阻是高功率的先决条件。组装的整个系统方法也应提供机械稳定性和较高的产品可靠性，尤其在加速应力测试(温度循环、坠落测试等)中。制造方法应足够灵活以适用于具有缩小的几何形状的半导体产品系列，其包括衬底和板，以及较广范围的设计和工艺变化。
本发明的一个实施例是一种用于制造用于高电流半导体倒装芯片产品的低电阻低电感互连结构的方法。提供半导体晶片，其具有金属化迹线、由覆层保护的晶片表面，和所述覆层中用以暴露金属化迹线的部分的窗。优选通过电镀在所述覆层上形成铜线；所述线通过使用金属填充所述窗来与所述迹线接触。接着，在所述线和剩余晶片表面上沉积光可成像绝缘材料层。在所述绝缘材料中打开窗以暴露所述线的部分，在每一线上以有序且重复的布置选择所述窗的位置，使得一条线的窗定位在相邻线的相应窗之间的中间位置附近。铜凸块优选通过电镀而形成于所述窗中，且与所述线接触。
某些装置特征在制造流程中服务于多个目的。光可成像绝缘层兼用作在组装工艺中对流动焊料的保护。启用电镀步骤所需的光致抗蚀剂层兼用作对进行电镀的铜元件的厚度控制。
本发明的另一实施例是一种用于制造用于高电流半导体倒装芯片产品的低电阻低电感装置的方法。提供一结构，其包括具有金属化迹线的半导体芯片、与所述迹线接触的铜线，和铜凸块，所述铜凸块以有序且重复的布置位于每一线上，使得一条线的凸块定位在相邻线的相应凸块之间的中间位置附近。另外，提供具有细长铜引线的衬底，所述引线具有第一和第二表面且经定向为与所述线成直角。使用焊接元件将每一引线的第一表面连接到交替线的相应凸块。最后，将组装件封装在模制化合物中，使得第二引线表面保持未经封装。
本发明的另一实施例是一种用于制造用于高电流半导体倒装芯片装置的低电阻低电感互连系统的方法。提供如上所述经封装的装置，其中引线表面未经封装。另外，提供电路板，其具有平行于所述引线的铜接触衬垫。使用焊接层将装置引线表面附接到板衬垫。
附图说明
图1A是半导体晶片的一部分的横截面，其描绘在晶片覆层中打开窗以暴露金属化迹线的一部分。
图1B是经图案化金属迹线的俯视图，其作为说明如图1A中所示选择要打开的窗的数目和位置的实例。
图1C是经图案化金属迹线的透视图，其作为说明如图1A中所示选择要打开的窗的数目和位置的实例。
图2到图5是示范性制造方法的步骤中图1的晶片部分的横截面。
图6A是图2到图5的晶片部分的横截面，其描绘第一光致抗蚀剂层、势垒层和种子层的移除。
图6B是图1B的经图案化金属迹线的部分的俯视图，其作为说明铜线的数目和位置的实例。
图6C是图1C的经图案化金属迹线的部分的透视图，其作为说明铜线的数目和位置的实例。
图7是图6A的晶片部分的横截面，其描绘光可成像绝缘材料层在晶片表面上的沉积和暴露。
图8A是图7的晶片部分的横截面，其描述在绝缘材料中打开窗以暴露所述线的一部分。
图8B是图6B的经图案化金属迹线的部分的俯视图，其作为说明如图8A中所示选择要打开的绝缘窗位置的实例；未展示绝缘材料。
图8C是图8B的晶片部分的透视图，其说明绝缘窗位置的选择；展示了绝缘材料。
图9到图12是图8A的晶片部分的横截面，其展示示范性制造方法中的步骤。
图13A是图12的晶片部分的横截面，其描绘第二光致抗蚀剂层、势垒层和种子层的移除。
图13B是图8C的晶片部分的示意性透视图，其说明沉积在选定绝缘窗中的铜凸块。
图14A是图13B的晶片部分的示意性透视图，其说明将铜凸块组装到衬底引线。
图14B是图14A的倒装组装件的示意性横截面。
图15是图14B的倒装组装件的示意性横截面，其说明将所述组装件封装在模制化合物中。
具体实施方式
本发明涉及2006年8月16日申请的标题为“具有低电阻和低电感的高电流半导体装置系统(High Current Semiconductor Device System Having Low Resistance AndInductions)”的PCT/US06/31933。
图1A到图15说明适合高电流半导体装置和系统的低电阻低电感互连的制造方法中的某些工艺步骤。图1A展示半导体晶片101的一部分，其具有金属化迹线102，且由覆层103来保护。对于许多装置来说，半导体晶片是硅或锗化硅，但对于其它装置来说，晶片可为砷化镓或半导体产品制造中所使用的任何其它化合物。用于许多装置的金属化迹线是铝或铝合金，对于其它装置来说，其为铜或铜合金；厚度范围通常为0.5到1μm。在许多装置中，迹线102的金属化水平是所述装置的若干金属化水平中的最高水平。覆层通常为氮化硅或氮氧化硅，其厚度范围为从约0.7到1.2μm；在某些装置中，覆层为若干层的堆叠，例如半导体上的二氧化硅和作为最外层的氮化硅或氮氧化硅。堆叠的厚度通常在0.7与1.5μm之间。
在覆层103中打开宽度为104的窗以暴露金属化迹线102的一部分。图1B的俯视图所提供的实例为一装置的平行金属化迹线110、111，......，11n以及用以暴露所述金属化迹线的覆层开口110a、110b，......，11na、11nb，......的数目和分布。图1C以透视图重现图1B的金属化迹线。
如图2所示，一对金属层201和202沉积在晶片表面上，其包含窗104；优选沉积方法为溅镀技术。层201为例如钛/钨合金的势垒金属，其厚度大约为0.5μm或以下。层202为厚度范围为约0.5到0.8μm的种子金属层，优选为铜。层201和202的堆叠适于为电镀步骤提供一致电位。
在图3中，第一光致抗蚀剂层301沉积在所述晶片的种子金属层202上。选择所述光致抗蚀剂层301的厚度301a，使其与铜线的既定高度相称，所述铜线将使用光致抗蚀剂层301来制造。图3进一步指示具有开口302a的光掩模302，所述开口302a用于通过暴露所述掩模下的晶片来界定铜线宽度。
图4说明经曝光和显影的光致抗蚀剂层301。在第一光致抗蚀剂层301中打开多个窗401，从而暴露部分的种子层202。图5展示下一工艺步骤：将铜501沉积在窗中。优选使用电镀将铜或铜合金沉积在光致抗蚀剂窗中，以将所述窗填充到所述光致抗蚀剂的厚度301a，从而产生具有高度501a的铜线501。或者，可沉积优选具有高电导率的其它导电材料；实例为银或银合金，或碳纳米管。
在图6A所展示的下一工艺步骤中，移除第一光致抗蚀剂层。使用镀铜结构501作为蚀刻掩模，随后在铜线501外部蚀刻掉势垒(或粘附)金属层201和种子金属层202。多个经电镀铜线的一部分展示于图6B的俯视图和图6C的透视图中。在这些图的实例中，将铜线描绘为与晶片金属化迹线110和111成直角。如先前所述，在其它装置中，铜线501可与所述金属化迹线平行，或成其它任一角度。
在图7中，优选使用旋涂技术用例如聚酰亚胺的光可成像绝缘材料701涂覆所述晶片。如图7中示意性地指示，通过此技术，使几何表面台阶或不规则部分平滑，包含由铜线501引起的台阶。绝缘体厚度在约10与20μm之间。相对更薄的绝缘体层形成于所述铜线表面上。所述绝缘材料的主要功能在稍后用于附接的回流焊接元件的组装步骤中变得可操作；所述绝缘材料防止邻近导体的意外电短路。
图7进一步展示应用于绝缘层的光掩模702。此光掩模702具有开口702a，其允许暴露线501的部分。光掩模702中的开口702a不同于光掩模302中的开口302a。开口702a意欲界定用以形成与铜线501接触的铜凸块的窗。
在每一线501上以有序且重复的布置选择所述窗702a的位置，使得一条线501的窗702a定位在相邻线的相应窗之间的中间位置附近。图8A说明绝缘层701的显影、绝缘层701中打开的窗801，和所述绝缘材料(聚酰亚胺)的固化。图8C以透视图指示绝缘层701中打开的窗801。图8B表示X射线俯视图，窗801相对于铜线501的阵列的定位突出了所述有序且重复的布置：一条线501的窗801定位在相邻线502、503的相应窗802、803之间的中间位置附近。
如图9所指示，一对金属层901、902沉积在所述晶片表面上，其包含窗801；优选沉积方法是溅镀技术。层901是例如钛/钨合金的势垒金属，其厚度为约0.5μm或以下。层902为厚度范围为约0.5到0.8μm的种子金属层，优选为铜。层901和902的堆叠适于为电镀步骤提供一致的电位。
在图10中，第二光致抗蚀剂层1001沉积在所述晶片的种子金属层902上。选择所述光致抗蚀剂层1001的厚度1001a，使其与所述铜凸块的既定高度相称，所述铜凸块将使用光致抗蚀剂层1001来制造。图10进一步指示具有开口1002a的光掩模1002，所述开口1002a用于暴露所述掩模下的晶片。光掩模1002不同于光掩模302和702；开口1002a界定既定铜凸块的长度和宽度。
图11说明经曝光和显影的第二光致抗蚀剂层1001。在光致抗蚀剂层1101中打开多个窗1101，从而暴露种子层902的一部分。图12展示下一工艺步骤：将铜凸块1201沉积在窗中。优选使用电镀将铜或铜合金沉积在光致抗蚀剂窗中，产生具有高度1201a的铜凸块1201。凸块高度1201a可等于光致抗蚀剂层厚度1001a，或者，其可略小，如图12中所指示。在此情况下，可(优选通过电镀)沉积一个或一个以上额外金属层1202，其促进焊料附着。这些金属层的实例为镍、钯和金；与铜凸块相比，这些层较薄。
在图13A中展示的接下来的几个工艺步骤中，移除第二光致抗蚀剂层。使用经电镀的铜凸块结构1201作为蚀刻掩模，随后在铜凸块1201外部蚀刻掉势垒(或粘附)金属层901和种子金属层902。多个经电镀铜凸块1201的一部分展示于图13B的透视图中。每一凸块1201具有至少一个可焊接金属层的盖1202，其通常具有作为最外层的锡钯层。
下一工艺步骤为单个化步骤，优选涉及旋转钻石锯，通过所述旋转钻石锯将所述晶片分成单独的芯片。随后可通过将芯片组装到衬底或引线框来进一步处理每一芯片。
在下一工艺步骤中，提供具有细长铜引线的衬底，所述引线具有第一和第二表面。优选实例为具有单独引线的金属引线框；优选引线框金属为铜或铜合金，但在特定装置中可使用铁/镍合金或铝。其它实例包含具有细长铜引线的绝缘衬底。如图6A到图6C所示，所述引线与所述铜线501成直角定向。随后使用焊接元件将每一引线的第一表面连接到交替线的相应凸块。图14A和图14B示意性地说明此组装件。
在图14A中，芯片1401由绝缘材料701覆盖，且具有多个铜凸块1201。衬底铜引线1410的第一表面1410a展示为附接到铜凸块1201(图14A中未展示所述芯片表面上的铜线501；引线1410与线501成直角)。引线1410的第二表面1410b背对凸块1201。
翻转图14A的组装件会产生图14B的定向，其显示衬底上芯片组装件的横截面。芯片1401具有由绝缘材料701覆盖的铜线501。在交替的线上展示了铜凸块1201，所述铜凸块通过焊接元件1420附接到引线1410的第一表面1410a。即使焊接元件1420会沿凸块1201的整个表面蔓延，绝缘材料701也防止与邻近导体的电短路。
将图14A/图14B的组装件提交到块模具(block mold)，在所述块模具中在一批模制工艺中封装多个经组装的单元。使第二引线表面1410b保持未经封装且暴露，以用于进一步的附接，例如用以将焊接层附接到电路板。最后，使用锯来分割单独的产品单元。图15说明封装在模制化合物1501中的此类经单个化的装置。所述装置的侧壁1501a是直的，因为其已由锯切工艺产生。
从引线表面1410b到芯片电路，存在经由铜连接器的连续电路径(焊接元件1420除外)。因此，图15中显示的装置的电阻和电感较低。图15的装置因此适于高电流(30A和更高)应用。可通过将第二引线表面1410b压按或焊接到电路板来进一步利用此特征，所述电路板具有平行于引线1410且与其数目和位置匹配的铜接触衬垫。优选的附接方法是通过使用焊接层来焊接。
尽管已参考说明性实施例描述了本发明，但并不希望在限制意义上解释此描述。参考所述描述，所属领域的技术人员将明白说明性实施例的各种修改和组合，以及本发明的其它实施例。作为一实例，衬底可为具有第一和第二表面的铜引线的绝缘条带。作为另一实例，铜凸块可比图中所说明的短得多；还将不存在由蔓延的焊接元件引起的电短路的危险。

Claims (5)

1.一种用于制造用于半导体倒装芯片产品的互连结构的方法，其包括以下步骤：
提供半导体晶片，所述半导体晶片具有金属化迹线、由覆层保护的晶片表面，和所述覆层中用以暴露所述金属化迹线的若干部分的窗；
在所述覆层上形成铜线，通过用金属填充所述窗来接触所述迹线；
将光可成像绝缘材料层沉积在所述铜线和剩余的晶片表面上；
在所述绝缘材料中打开窗以暴露所述铜线的若干部分，在每一线上以有序且重复的布置选择所述窗的位置，使得一条线的所述窗定位在相邻线的相应窗之间的中间位置附近；以及
在所述窗中形成与所述线接触的铜凸块；
其中所述形成铜线的步骤包括以下步骤：
将势垒金属层沉积在所述晶片表面上；
将种子金属层沉积在所述势垒金属层上；
将第一光致抗蚀剂层以与既定铜线的高度相称的高度沉积在所述种子金属层上；
在所述光致抗蚀剂层中打开窗，使得所述窗按照所述既定铜线成形；
沉积铜以填充所述光致抗蚀剂窗且形成铜线；
移除所述第一光致抗蚀剂层；以及
移除所述种子金属层和所述势垒金属层的若干部分，所述若干部分在移除所述第一光致抗蚀剂层后暴露。
2.根据权利要求1所述的方法，其中所述形成铜凸块的步骤包括以下步骤：
将势垒金属层沉积在所述晶片表面上；
将种子金属层沉积在所述势垒金属层上；
将第二光致抗蚀剂层以与既定铜凸块的高度相称的高度沉积在所述种子金属层上；
在所述光致抗蚀剂层中既定用于铜凸块的位置中打开窗，且所述窗的宽度与所述既定铜凸块的宽度相称；
通过沉积铜来填充所述光致抗蚀剂窗以形成铜凸块；
移除所述第二光致抗蚀剂层；以及
移除所述种子金属层和所述势垒金属层的若干部分，所述若干部分在移除所述第二光致抗蚀剂层后暴露。
3.根据权利要求1或2所述的方法，其中所述沉积铜的步骤包括电镀技术。
4.一种用于制造用于半导体倒装芯片产品的互连装置的方法，其包括以下步骤：
提供一结构，所述结构包括半导体芯片，所述半导体芯片具有金属化迹线、与所述迹线接触的铜线，和铜凸块，所述铜凸块以有序且重复的布置位于每一线上，使得一条线的所述凸块定位在相邻线的相应凸块之间的中间位置附近；
提供具有细长铜引线的衬底，所述引线具有第一和第二表面，所述引线与所述线成直角定向；
使用焊接元件将每一引线的所述第一表面连接到交替线的相应凸块；以及将组装件封装在模制化合物中，使得所述第二表面保持未经封装。
5.一种用于制造用于半导体倒装芯片装置的互连系统的方法，其包括以下步骤：提供低电阻低电感互连装置，所述互连装置包括：
半导体芯片结构，其包含与芯片金属化迹线接触的铜线和以有序且重复的布置位于每一线上的铜凸块，一条线的所述凸块定位在相邻线的相应凸块之间的中间位置附近；
具有细长铜引线的衬底，所述引线具有第一和第二表面，所述引线与所述线成直角，所述第一表面通过焊接元件而连接到交替线的所述相应凸块；以及
所述芯片结构和衬底经封装，使得所述第二表面保持未经封装；
提供具有平行于所述引线的铜接触衬垫的电路板；以及
使用焊接层将所述装置引线的所述第二表面附接到所述铜接触衬垫。
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