KR101107659B1 - 반도체 패키지 - Google Patents

반도체 패키지 Download PDF

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Publication number
KR101107659B1
KR101107659B1 KR1020100010900A KR20100010900A KR101107659B1 KR 101107659 B1 KR101107659 B1 KR 101107659B1 KR 1020100010900 A KR1020100010900 A KR 1020100010900A KR 20100010900 A KR20100010900 A KR 20100010900A KR 101107659 B1 KR101107659 B1 KR 101107659B1
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South Korea
Prior art keywords
connection
pad
semiconductor package
connection pad
resistance member
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KR1020100010900A
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English (en)
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KR20110091188A (ko
Inventor
김기영
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020100010900A priority Critical patent/KR101107659B1/ko
Priority to US13/016,611 priority patent/US20110193204A1/en
Publication of KR20110091188A publication Critical patent/KR20110091188A/ko
Application granted granted Critical
Publication of KR101107659B1 publication Critical patent/KR101107659B1/ko

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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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    • F21V23/0471—Arrangement of electric circuit elements in or on lighting devices the elements being switches activated by means of a sensor, e.g. motion or photodetectors the sensor detecting the proximity, the presence or the movement of an object or a person
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Abstract

반도체 패키지가 개시되어 있다. 개시된 반도체 패키지는, 상면 및 상기 상면과 대향하는 하면을 갖는 기판 몸체, 상기 상면에 형성되는 제1접속패드, 상기 상면에 제1접속패드와 이격되어 형성되는 제2접속패드를 포함하는 기판과, 제1본딩패드 및 제2본딩패드가 형성된 반도체 칩과, 상기 제1접속패드와 상기 제1본딩패드를 연결하는 제1연결부재와, 상기 제2접속패드 및 상기 제2본딩패드 중 어느 하나에 형성되는 저항부재와, 상기 저항부재가 형성되지 않은 나머지 다른 하나와 상기 저항부재를 연결하는 제2연결부재를 포함하는 것을 특징으로 한다.

Description

반도체 패키지{SEMICONDUCTOR PACKAGE}
본 발명은 반도체 패키지에 관한 것으로, 보다 상세하게는 저항을 내장하는 반도체 패키지에 관한 것이다.
전자제품이 소형화 및 경량화되어 감에 따라 저항(resistor)이 차지하는 면적을 감소시키려는 노력이 계속되고 있으며, 이러한 노력의 일환으로 저항을 외부에 구성하지 않고 반도체 패키지의 인쇄회로기판(Printed Circuit Board, PCB)에 내장시킨 저항 내장형 인쇄회로기판(embedded resistor PCB)이 사용되고 있다.
그러나, 저항 내장형 인쇄회로기판을 제작하기 위해서는 순수한 인쇄회로기판을 형성하기 위한 공정 외에 저항으로 사용되는 물질막의 증착 공정, 식각 공정을 추가로 진행해야 하므로 인쇄회로기판의 제작 과정이 복잡해지는 문제점이 있다. 또한, 저항으로 사용되는 물질막과 인쇄회로기판을 구성하는 막간의 접착력 저하 및 저항으로 사용되는 물질막이 추가됨에 따른 인쇄회로기판의 특성 변화 등으로 인해 반도체 패키지의 신뢰성이 떨어지는 문제점이 있다.
본 발명은, 저항부재를 내장함으로 인해 유발되는 제작 과정의 어려움 및 신뢰성 저하를 방지하기 위한 반도체 패키지를 제공하는데, 그 목적이 있다.
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본 발명의 일 견지에 따른 반도체 패키지는, 상면 및 상기 상면과 대향하는 하면을 갖는 기판 몸체, 상기 상면에 형성되는 제1접속패드, 상기 상면에 제1접속패드와 이격되어 형성되는 제2접속패드를 포함하는 기판과, 제1본딩패드 및 제2본딩패드가 형성된 반도체 칩과, 상기 제1접속패드와 상기 제1본딩패드를 연결하는 제1연결부재와, 상기 제2접속패드 및 상기 제2본딩패드 중 어느 하나에 형성되는 저항부재와, 상기 저항부재가 형성되지 않은 나머지 다른 하나와 상기 저항부재를 연결하는 제2연결부재를 포함하는 것을 특징으로 한다.
상기 저항부재는 범프로 형성하는 것을 특징으로 한다.
상기 제1, 제2연결부재는 본딩 와이어로 형성하는 것을 특징으로 한다.
본 발명의 다른 견지에 따른 반도체 패키지는, 상면 및 상기 상면과 대향하는 하면을 갖는 기판 몸체, 상기 상면에 형성되는 제1접속패드, 상기 상면에 제1접속패드와 이격되어 형성되는 제2접속패드를 포함하는 기판과, 제1본딩패드 및 제2본딩패드가 형성된 반도체 칩과, 상기 제1접속패드와 상기 제1본딩패드를 연결하는 제1연결부재와, 상기 제2접속패드 상에 형성되는 제1저항부재와, 상기 제2본딩패드 상에 형성되는 제2저항부재와, 상기 제1저항부재와 상기 제2저항부재를 연결하는 제2연결부재를 포함하는 것을 특징으로 한다.
상기 제1저항부재 및 상기 제2저항부재는 범프로 형성하는 것을 특징으로 한다.
상기 제1, 제2연결부재는 본딩 와이어로 형성하는 것을 특징으로 한다.
본 발명의 또 다른 견지에 따른 반도체 패키지는, 상면 및 상기 상면과 대향하는 하면을 갖는 기판 몸체, 상기 상면에 형성되는 제1접속패드, 상기 상면에 제1접속패드와 이격되어 형성되는 제2접속패드 및 상기 상면에 제1, 제2접속패드와 이격되어 형성되는 서브 접속패드를 포함하는 기판과, 제1본딩패드 및 제2본딩패드가 형성된 반도체 칩과, 상기 제1접속패드와 상기 제1본딩패드를 연결하는 제1연결부재와, 상기 제2접속패드와 상기 서브접속패드 사이, 상기 서브접속패드와 상기 제2본딩패드 사이 중 어느 하나에 형성되는 제2연결부재와, 상기 제2연결부재가 형성되지 않은 나머지 다른 하나에 형성되는 저항부재를 포함하는 것을 특징으로 한다.
상기 제1, 제2 연결부재 및 상기 저항부재는 본딩 와이어로 형성하는 것을 특징으로 한다.
상기 서브 접속패드는 상기 반도체 칩과 상기 제2접속패드 사이에 배치되는 것을 특징으로 한다.
본 발명에 따르면, 저항을 내장하는 반도체 패키지의 제작이 용이해지고 신뢰성이 향상되는 효과가 있다.
도 1은 본 발명의 제 1 실시예에 따른 반도체 패키지의 평면도이다.
도 2는 본 발명의 제 1 실시예에 따른 반도체 패키지의 단면도이다.
도 3은 본 발명의 제 2 실시예에 따른 반도체 패키지의 단면도이다.
도 4는 본 발명의 제 3 실시예에 따른 반도체 패키지의 평면도이다.
도 5는 본 발명의 제 3 실시예에 따른 반도체 패키지의 단면도이다.
도 6은 본 발명의 제 4 실시예에 따른 반도체 패키지의 평면도이다.
도 7은 본 발명의 제 4 실시예에 따른 반도체 패키지의 단면도이다.
도 8은 본 발명의 제 5 실시예에 따른 반도체 패키지의 평면도이다.
도 9는 본 발명의 제 4 실시예에 따른 반도체 패키지의 단면도이다.
도 10은 본 발명의 제 6 실시예에 따른 반도체 패키지의 평면도이다.
도 11은 본 발명의 제 6 실시예에 따른 반도체 패키지의 단면도이다.
이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예들을 상세히 설명하도록 한다.
-제 1 실시예-
도 1은 본 발명의 제 1 실시예에 따른 반도체 패키지의 평면도이고, 도 2는 본 발명의 제 1 실시예에 따른 반도체 패키지의 단면도이다.
도 1 및 도 2를 참조하면, 본 발명의 제 1 실시예에 따른 반도체 패키지는, 기판(100), 반도체 칩(200), 연결부재(400) 및 저항부재(500)를 포함한다.그 외에, 봉지부(600) 및 외부접속단자(700)를 더 포함할 수 있다.
기판(100)은 기판 몸체(110), 제1, 제2접속패드(120, 130), 볼랜드(140) 및 도전성 비아(150)를 포함한다.
기판 몸체(110)는 직육면체 형상을 가질 수 있다. 직육면체 형상을 갖는 기판 몸체(110)는 상면(111), 하면(112) 및 4개의 측면(113)들을 갖는다. 기판 몸체(110)의 상면(111)은 하면(112)과 대향하고, 4개의 측면(113)들은 상면(111) 및 하면(112)을 연결한다.
제1접속패드(120)는 기판 몸체(110)의 상면(111)에 배치된다. 본 실시예에서, 제1접속패드(120)는 상면(111) 가장자리를 따라서 복수개 형성된다. 제2접속패드(130)는 기판 몸체(110)의 상면(111)에 제1접속패드(120)와 이격되어 배치된다. 본 실시예에서, 제2접속패드(130)는 제1접속패드(120)와 동일한 형태를 갖는다.
볼랜드(140)는 기판 몸체(110)의 하면(112)에 배치된다. 도전성 비아(150)는 기판 몸체(110)의 상면(111) 및 하면(112)을 관통하여 제1접속패드(120)와 볼랜드(140) 사이 및 제2접속패드(130)와 볼랜드(140) 사이를 연결한다.
반도체 칩(200)은 제1, 제2접속패드(120, 130) 안쪽 기판 몸체(110) 상면(111)에 접착부재(300)를 매개로 부착된다. 반도체 칩(200)은 기판(100)과 대향하는 일면에 제1본딩패드(210) 및 제2본딩패드(220)를 갖는다.
본 실시예에서, 제1본딩패드(210)는 기판(100)의 제1접속패드(120)들에 대응하여 반도체 칩(200) 일면 가장자리를 따라서 복수개 형성된다. 그리고, 제2본딩패드(220)는 기판(100)에 형성된 제2접속패드(130)와 대응하여 형성된다.
연결부재(400)는 제1본딩패드(210)와 제1접속패드(120)를 연결하고,저항부재(500)는 제1본딩패드(220)과 제2접속패드(130)을 연결한다.
본 실시예에서, 연결부재(400) 및 저항부재(500)는 본딩 와이어로 형성한다.
저항부재(500)는 Ni, Cr, Al Si로 이루어진 군(群)으로부터 선택되는 적어도 어느 하나로 형성될 수 있다. 예컨데, 저항부재(500)는 Cr을 20% 함유하는 Ni 및 Cr의 화합물로 형성될 수 있다.
저항부재(500)의 저항값은, 저항부재(500)의 본딩 와이어 직경(Diameter) 및 길이를 가변시키어 조절할 수 있다. 예컨데, 저항부재(500)가 큰 저항값을 갖아야 하는 경우에는 저항부재(500)를 상대적으로 작은 직경 또는/및 긴 길이로 형성한다. 반면, 저항부재(500)가 상대적으로 작은 저항값을 가져야 하는 경우에는 저항부재(500)를 상대적으로 큰 직경 또는/및 짧은 길이로 형성한다.
봉지부(600)는 반도체 칩(200)을 포함한 기판 몸체(110) 상면(111)을 밀봉하고, 외부접속단자(700)는 기판 몸체(110) 하면(112)에 형성된 볼랜드(140)에 부착된다.
-제 2 실시예-
도 3은 본 발명의 제 2 실시예에 따른 반도체 패키지의 단면도이다.
도 3을 참조하면, 본 발명의 제 2 실시예에 따른 반도체 패키지는, 기판(100), 반도체 칩(200), 연결부재(400) 및 저항부재(500)를 포함한다. 그 외에, 봉지부(600), 외부접속단자(700) 및 언더필(underfill) 부재(800)를 더 포함할 수 있다.
기판(100)은 기판 몸체(110), 제1, 제2접속패드(130), 볼랜드(140) 및 도전성 비아(미도시)를 포함한다.
기판 몸체(110)는 직육면체 형상을 가질 수 있다. 직육면체 형상을 갖는 기판 몸체(110)는 상면(111), 하면(112) 및 4개의 측면(113)들을 갖는다. 기판 몸체(110)의 상면(111)은 하면(112)과 대향하고, 4개의 측면(113)들은 상면(111) 및 하면(112)을 연결한다.
제1접속패드(120)는 기판 몸체(110) 상면(111)에 배치되고, 제2접속패드(130)는 기판 몸체(110) 상면(111)에 제1접속패드(120)와 이격되어 배치된다. 본 실시예에서, 제2접속패드(130)는 제1접속패드(120)와 동일한 형태로 형성된다.
볼랜드(140)는 기판 몸체(110) 하면(112)에 배치되고, 도전성 비아는 기판 몸체(110)의 상면(111) 및 하면(112)을 관통하여 제1접속패드(120)와 볼랜드(140) 사이 및 제2접속패드(130)와 볼랜드(140) 사이를 연결한다.
기판(100)과 대응하는 반도체 칩(200)의 일면에는 제1본딩패드(210) 및 제2본딩패드(220)가 형성된다. 제1본딩패드(210)는 제1접속패드(120)와 마주하도록 형성되고, 제 2본딩패드(220)는 제2접속패드(130)와 마주하도록 형성된다.
연결부재(400)는 제1본딩패드(210)와 제1접속패드(120) 사이에 개재되어 제1본딩패드(210)와 제1접속패드(120)를 연결한다. 본 실시예에서, 연결부재(400)는 범프로 형성된다.
저항부재(500)는 제2본딩패드(220)와 제2접속패드(130) 사이에 개재되어 제2본딩패드(220)와 제2접속패드(130)를 연결한다. 본 실시에에서, 저항부재(500)는 범프로 형성된다. 저항부재(500)는 Ni, Cr, Al Si로 이루어진 군(群)으로부터 선택되는 적어도 어느 하나로 형성될 수 있다. 예컨데, 저항부재(500)는 Cr을 20% 함유하는 Ni 및 Cr의 화합물로 형성될 수 있다.
언더필 부재(800)는 기판(100)과 반도체 칩(200) 사이의 공간에 충진되고, 봉지부(600)는 반도체 칩(200)을 포함한 기판 몸체(110) 상면(111)을 밀봉한다. 그리고, 외부접속단자(700)는 기판 몸체(110) 하면(112)에 형성된 볼랜드(140)에 부착된다.
-제 3 실시예-
도 4는 본 발명의 제 3 실시예에 따른 반도체 패키지의 평면도이고, 도 5는 본 발명의 제 3 실시예에 따른 반도체 패키지의 단면도이다.
본 발명의 제 3 실시예에 따른 반도체 패키지는, 연결부재 및 저항부재를 제외하면 앞서 도 1 및 도 2를 통해 설명된 제 1 실시예에 따른 반도체 패키지와 실질적으로 동일한 구성을 갖는다. 따라서, 동일한 구성요소에 대한 중복설명은 생략하기로 하며, 동일한 구성요소에 대해서는 동일한 명칭 및 동일한 참조 부호를 부여하기로 한다.
도 4 및 도 5를 참조하면, 본 발명의 제 3 실시예에 따른 반도체 패키지는, 기판(100), 반도체 칩(200), 제1, 제2연결부재(400A, 400B) 및 저항부재(500)를 포함한다. 그 외에, 봉지부(600) 및 외부접속단자(700)를 더 포함할 수 있다.
제1연결부재(400A)는 반도체 칩(200)의 제1본딩패드(210)와 기판(100)의 제1접속패드(120)를 연결한다. 본 실시에에서, 제1연결부재(400A)는 본딩 와이어로 형성된다.
저항부재(500)는 반도체 칩(200)의 제2본딩패드(220) 상에 형성된다.
본 실시예에서, 저항부재(500)는 범프로 형성된다. 저항부재(500)는 Ni, Cr, Al Si로 이루어진 군(群)으로부터 선택되는 적어도 어느 하나로 형성될 수 있다. 예컨데, 저항부재(500)는 Cr을 20% 함유하는 Ni 및 Cr의 화합물로 형성될 수 있다.
제2연결부재(400B)는 저항부재(500)와 기판(100)의 제2접속패드(130)를 연결한다. 본 실시예에서, 제2연결부재(520)는 본딩 와이어로 형성된다.
-제 4 실시예-
도 6은 본 발명의 제 4 실시예에 따른 반도체 패키지의 평면도이고, 도 7은 본 발명의 제 4 실시예에 따른 반도체 패키지의 단면도이다.
본 발명의 제 4 실시예에 따른 반도체 패키지는 저항부재를 제외하면 앞서 도 4 및 도 5를 통해 설명된 제 3 실시예에 따른 반도체 패키지와 실질적으로 동일한 구성을 갖는다. 따라서, 동일한 구성요소에 대한 중복설명은 생략하기로 하며, 동일한 구성요소에 대해서는 동일한 명칭 및 동일한 참조 부호를 부여하기로 한다.
도 6 및 도 7을 참조하면, 본 발명의 제 4 실시예에 따른 반도체 패키지는, 기판(100), 반도체 칩(200), 제1, 제2연결부재(400A, 400B) 및 저항부재(500)를 포함한다. 그 외에, 봉지부(600) 및 외부접속단자(700)를 더 포함할 수 있다.
본 실시예에서는, 전술한 제 3 실시예와 달리 저항부재(500)가 기판(100)의 제2접속패드(130)상에 형성된다. 본 실시예에서, 저항부재(500)는 범프로 형성된다.
제2연결부재(400B)는 저항부재(500)와 반도체 칩(200)의 제2본딩패드(220)를 연결한다. 본 실시예에서, 제2연결부재(520)는 본딩 와이어로 형성된다
-제 5 실시예-
도 8은 본 발명의 제 5 실시예에 따른 반도체 패키지의 평면도이고, 도 9는 본 발명의 제 5 실시예에 따른 반도체 패키지의 단면도이다.
본 발명의 제 5 실시예에 따른 반도체 패키지는 저항부재를 제외하면 앞서 도 4 및 도 5를 통해 설명된 제 3 실시예에 따른 반도체 패키지와 실질적으로 동일한 구성을 갖는다. 따라서, 동일한 구성요소에 대한 중복설명은 생략하기로 하며, 동일한 구성요소에 대해서는 동일한 명칭 및 동일한 참조 부호를 부여하기로 한다.
도 8 및 도 9를 참조하면, 본 발명의 제 5 실시예에 따른 반도체 패키지는, 기판(100), 반도체 칩(200), 제1, 제2연결부재(400A, 400B) 및 제1, 제2저항부재(500A, 500B)를 포함한다. 그 외에, 봉지부(600) 및 외부접속단자(700)를 더 포함할 수 있다.
제1저항부재(500A)는 반도체 칩(200)의 제2본딩패드(220) 상에 형성되고, 제2저항부재(500B)는 기판(100)의 제2접속패드(130) 상에 형성된다. 본 실시예에서, 제1, 제2저항부재(500A, 500B)는 범프로 형성된다.
제2연결부재(400B)는 제1저항부재(500A)와 제2저항부재(500B)를 연결한다. 본 실시에에서, 제2연결부재(400B)는 본딩 와이어로 형성된다.
-제 6 실시예-
도 10은 본 발명의 제 6 실시예에 따른 반도체 패키지의 평면도이고, 도 11은 본 발명의 제 6 실시예에 따른 반도체 패키지의 단면도이다.
본 발명의 제 6 실시예에 따른 반도체 패키지는 기판 및 저항부재를 제외하면 앞서 도 1 및 도 2를 통해 설명된 제 1 실시예에 따른 반도체 패키지와 실질적으로 동일한 구성을 갖는다. 따라서, 동일한 구성요소에 대한 중복설명은 생략하기로 하며, 동일한 구성요소에 대해서는 동일한 명칭 및 동일한 참조 부호를 부여하기로 한다.
도 10 및 도 11을 참조하면, 본 발명의 제 6 실시예에 따른 반도체 패키지는 기판(100), 반도체 칩(200), 제1, 제2연결부재(400A, 400B) 및 저항부재(500)를 포함한다. 그 외에, 봉지부(600) 및 외부접속단자(700)를 더 포함할 수 있다.
기판(100)은 기판 몸체(110), 제1접속패드(120), 제2접속패드(130), 볼랜드(140), 도전성 비아(150) 및 서브 접속패드(160)를 포함한다.
기판 몸체(110)는 직육면체 형상을 가질 수 있다. 직육면체 형상을 갖는 기판 몸체(110)는 상면(111), 하면(112) 및 4개의 측면(113)들을 갖는다. 기판 몸체(110)의 상면(111)은 하면(112)과 대향하고, 4개의 측면(113)들은 상면(111)과 하면(112)을 연결한다.
제1접속패드(120)는 기판 몸체(110)의 상면(111)에 배치된다. 본 실시예에서, 제1접속패드(120)는 기판 몸체(110) 상면(111) 가장자리를 따라서 복수개 형성된다. 제2접속패드(130)는 기판 몸체(110)의 상면(111)에 제1접속패드(120)와 이격되도록 배치된다. 본 실시예에서, 제2접속패드(130)는 제1접속패드(120)와 동일한 형태를 갖는다.
볼랜드(140)는 기판 몸체(110) 하면(112)에 배치된다. 도전성 비아(150)는 기판 몸체(110)의 상면(111) 및 하면(112)을 관통하여 제1접속패드(120)와 볼랜드(140) 사이 및 제2접속패드(130)와 볼랜드(140) 사이를 연결한다.
서브 접속패드(160)는 기판 몸체(110) 상면(111)에 제1, 제2접속패드(120, 130)와 이격되도록 배치된다. 서브 접속패드(160)는 제2연결부재(400B) 및 저항부재(500)를 매개로 제2본딩패드(220) 및 제2접속패드(130)와 연결된다. 저항부재(500) 및 제2연결부재(400B)의 길이를 최소화하기 위해서 서브 접속패드(160)는 반도체 칩(200)과 제2접속패드(130) 사이에 배치되는 것이 바람직하다.
제1연결부재(400A)는 제1접속패드(120)와 제1본딩패드(210)를 연결한다.
저항부재(500)는 제2접속패드(130)과 서브 접속패드(160)를 연결한다. 본 실시예에서, 저항부재(500)는 본딩 와이어로 형성된다.
저항부재(500)는 Ni, Cr, Al Si로 이루어진 군(群)으로부터 선택되는 적어도 어느 하나로 형성될 수 있다. 예컨데, 저항부재는 Cr을 20% 정도 함유하는 Ni 및 Cr의 화합물로 형성될 수 있다.
제2연결부재(400B)는 서브 접속패드(160)와 제2본딩패드(220)를 연결한다.
전술한 제 6 실시예에서는, 저항부재(500)가 제2접속패드(130)과 서브 접속패드(160) 사이에 연결되고 제2연결부재(400B)가 서브 접속패드(160)와 제2본딩패드(220) 사이에 연결되는 경우만을 설명하였으나, 이와 달리 제2연결부재(400B)가 제2접속패드(130)과 서브 접속패드(160) 사이에 연결되고 저항부재(500)가 서브 접속패드(160)와 제2본딩패드(220) 사이에 연결될 수도 있다.
이상에서 상세하게 설명한 바에 의하면, 저항 부재가 기판과 반도체 칩 사이에 연결되므로, 저항이 기판에 내장되는 구조를 갖는 종래의 반도체 패키지에서 저항으로 사용되는 물질의 형성, 식각 등의 공정이 추가됨에 따라서 인쇄회로기판 제작 공정이 복잡해지고, 저항으로 사용되는 물질과 인쇄회로기판을 구성하는 다른 막과의 접착력 저하 및 저항으로 사용되는 물질이 추가로 형성됨에 따른 특성 변화 등으로 인하여 신뢰성이 떨어지는 문제점이 해결되므로, 제작이 용이해지고 신뢰성이 향상되는 효과가 있다.
앞서 설명한 본 발명의 상세한 설명에서는 본 발명의 실시예들을 참조하여 설명하였지만, 해당 기술분야의 숙련된 당업자 또는 해당 기술분야에 통상의 지식을 갖는 자라면 후술 될 특허청구범위에 기재된 본 발명의 사상 및 기술 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.
100 : 기판
200 : 반도체 칩
500 : 저항부재

Claims (12)

  1. 삭제
  2. 삭제
  3. 삭제
  4. 상면 및 상기 상면과 대향하는 하면을 갖는 기판 몸체, 상기 상면에 형성되는 제1접속패드, 상기 상면에 제1접속패드와 이격되어 형성되는 제2접속패드를 포함하는 기판;
    제1본딩패드 및 제2본딩패드가 형성된 반도체 칩;
    상기 제1접속패드와 상기 제1본딩패드를 연결하는 제1연결부재;
    상기 제2접속패드 및 상기 제2본딩패드 중 어느 하나에 형성되는 저항부재;및
    상기 저항부재가 형성되지 않은 나머지 다른 하나와 상기 저항부재를 연결하는 제2연결부재;
    를 포함하는 것을 특징으로 하는 반도체 패키지.
  5. 제 4항에 있어서,
    상기 저항부재는 범프로 형성하는 것을 특징으로 하는 반도체 패키지.
  6. 제 4항에 있어서,
    상기 제1, 제2연결부재는 본딩 와이어로 형성하는 것을 특징으로 하는 반도체 패키지.
  7. 상면 및 상기 상면과 대향하는 하면을 갖는 기판 몸체, 상기 상면에 형성되는 제1접속패드, 상기 상면에 제1접속패드와 이격되어 형성되는 제2접속패드를 포함하는 기판;
    제1본딩패드 및 제2본딩패드가 형성된 반도체 칩;
    상기 제1접속패드와 상기 제1본딩패드를 연결하는 제1연결부재;
    상기 제2접속패드 상에 형성되는 제1저항부재;
    상기 제2본딩패드 상에 형성되는 제2저항부재;및
    상기 제1저항부재와 상기 제2저항부재를 연결하는 제2연결부재;
    를 포함하는 것을 특징으로 하는 반도체 패키지.
  8. 제 7항에 있어서,
    상기 제1저항부재 및 상기 제2저항부재는 범프로 형성하는 것을 특징으로 하는 반도체 패키지.
  9. 제 7항에 있어서,
    상기 제1, 제2연결부재는 본딩 와이어로 형성하는 것을 특징으로 하는 반도체 패키지.
  10. 상면 및 상기 상면과 대향하는 하면을 갖는 기판 몸체, 상기 상면에 형성되는 제1접속패드, 상기 상면에 제1접속패드와 이격되어 형성되는 제2접속패드 및 상기 상면에 제1, 제2접속패드와 이격되어 형성되는 서브 접속패드를 포함하는 기판;
    제1본딩패드 및 제2본딩패드가 형성된 반도체 칩;
    상기 제1접속패드와 상기 제1본딩패드를 연결하는 제1연결부재;및
    상기 제2접속패드와 상기 서브접속패드 사이, 상기 서브접속패드와 상기 제2본딩패드 사이 중 어느 하나에 형성되는 제2연결부재;및
    상기 제2연결부재가 형성되지 않은 나머지 다른 하나에 형성되는 저항부재;
    를 포함하는 것을 특징으로 하는 반도체 패키지.
  11. 제 10항에 있어서,
    상기 제1, 제2 연결부재 및 상기 저항부재는 본딩 와이어로 형성하는 것을 특징으로 하는 반도체 패키지.
  12. 제 10항에 있어서,
    상기 서브 접속패드는 상기 반도체 칩과 상기 제2접속패드 사이에 배치되는 것을 특징으로 하는 반도체 패키지.
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